slightly nicer layout

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index 7c299efddd4812b96aa82f19efc79d46abe198a0..8d4f082ee9075a38fe3ecd952315f1f797be2631 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -1,11 +1,10 @@
-\begin{longtable}{|p{0.10\textwidth}|p{0.08\textwidth}|p{0.13\textwidth}|X|}
+\begin{longtable}{|p{0.05\textwidth}|p{0.08\textwidth}|p{0.13\textwidth}|X|}
 \hline
 \textbf{Table} & \textbf{Bit} & \textbf{Name} & \textbf{Description} \\
 \hline\hline
 0 & 0 & Undefined & The feature table is not implemented in the design \\
-\hline
-1\newline Central
- & \multicolumn{3}{l|}{For a normal central FPGA design with Cts and/or GbE}\\
+\hline\hline
+1 & \multicolumn{3}{X|}{``Central'' - For a normal central FPGA design with Cts and/or GbE}\\
  & 3 -- 0   & ExtModule   & Type of external trigger module (0: none, 1: CBM MBS, 2: Mainz M2)\\ 
  & 7 -- 4   & CtsTdc      & Number of TDC channels included. Usually connected to the first trigger inputs of the CTS. 
 If a trigger module is present, the first channel will connect to its async output signal \\
@@ -25,9 +24,9 @@ CTS registers. \\
  & 51 -- 48 & TrgModule   & Type of trigger module 0: none, 1: simple or, 2: edge detect \\
  & 55 -- 52 & Clock       & Main clock source: 0: onboard 200 MHz, 1: onboard 125 MHz, 2: 200 MHz RX clock on SFP1, 3: 
 125 MHz RX clock on SFP1, 4: external clock input 200 MHz, 5: external clock input 125 MHz\\
-\hline
-2\newline TDC 
- & \multicolumn{3}{l|}{For TDC designs. Detailed information about the TDC setup can be found in register 0xc8xx}\\
+\hline\hline
+2 & \multicolumn{3}{X|}{``TDC'' - For TDC designs. Detailed information about the TDC setup can be found in register 
+0xc8xx}\\
  & 7 -- 0   & Pinout      & Which pin-out is being used for the TDC inputs. 0: flexible by multiplexers, 1: default 
 1-to-1, 2: every second input (e.g. Padiwa Amps fast-only), 3: every fourth input (HPTDC very high speed mode)\\
  & 11 -- 8  & DoubleEdge  & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same