+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk3125" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 28 18:11:11.787" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="pll_adc_clk3125.lpc" type="lpc" modified="2013 03 28 18:11:07.000"/>
- <File name="pll_adc_clk3125.vhd" type="top_level_vhdl" modified="2013 03 28 18:11:07.000"/>
- <File name="pll_adc_clk3125_tmpl.vhd" type="template_vhdl" modified="2013 03 28 18:11:07.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_clk3125
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=03/28/2013
-Time=18:11:07
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=125
-Div=4
-ClkOPBp=0
-Post=32
-U_OFrq=31.25
-OP_Tol=0.0
-OFrq=31.250000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=1
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=3.424318
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk3125 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 31.25 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
-
--- Thu Mar 28 18:11:07 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_clk3125 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_clk3125 : entity is true;
-end pll_adc_clk3125;
-
-architecture Structure of pll_adc_clk3125 is
-
- -- internal signal declarations
- signal CLKOP_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "31.250000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 32, CLKFB_DIV=> 1, CLKI_DIV=> 4,
- FIN=> "125.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
-
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_clk3125 is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
\r
begin\r
\r
- DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN;\r
+ DEBUG_OUT(0) <= CLK_IN; --NX_TIMESTAMP_CLK_IN;\r
DEBUG_OUT(1) <= parity_error;\r
DEBUG_OUT(2) <= nx_new_frame;\r
DEBUG_OUT(3) <= rs_sync_set;\r
parity_error <= '0';\r
if (nx_new_frame = '1' and nx_frame_synced = '1') then\r
-- Timestamp Bit #6 is excluded (funny nxyter-bug)\r
- parity_bits := fifo_32bit_word(31 downto 24) &\r
+ parity_bits := fifo_32bit_word(31) &\r
+ fifo_32bit_word(30 downto 24) &\r
fifo_32bit_word(21 downto 16) &\r
fifo_32bit_word(14 downto 8) &\r
fifo_32bit_word( 2 downto 1);\r
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
-
+ CLK_ADC_IN : in std_logic;
+
I2C_SDA_INOUT : inout std_logic;
I2C_SCL_INOUT : inout std_logic;
I2C_SM_RESET_OUT : out std_logic;
NX_RESET_OUT : out std_logic;
NX_TESTPULSE_OUT : out std_logic;
- ADC_FCLK_IN : in std_logic;
- ADC_DCLK_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
ADC_SC_CLK32_OUT : out std_logic;
- ADC_A_IN : in std_logic;
- ADC_B_IN : in std_logic;
- ADC_NX_IN : in std_logic;
- ADC_D_IN : in std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
REGIO_DATA_IN : in std_logic_vector(31 downto 0);
);
end component;
-component fifo_dc_8to32_dyn
+component fifo_6to6_dc
port (
- Data : in std_logic_vector(7 downto 0);
+ Data : in std_logic_vector(5 downto 0);
WrClock : in std_logic;
RdClock : in std_logic;
WrEn : in std_logic;
Reset : in std_logic;
RPReset : in std_logic;
AmEmptyThresh : in std_logic_vector(5 downto 0);
- Q : out std_logic_vector(31 downto 0);
+ Q : out std_logic_vector(5 downto 0);
Empty : out std_logic;
Full : out std_logic;
AlmostEmpty : out std_logic
);
end component;
-component fifo_dc_9to36_dyn
+component fifo_32_data
port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh: in std_logic_vector(5 downto 0);
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostEmpty : out std_logic
+ Data : in std_logic_vector(31 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
);
end component;
);
end component;
-component fifo_32_data
- port (
- Data : in std_logic_vector(31 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic
- );
-end component;
component nx_data_buffer
port (
LOCK : out std_logic);
end component;
+component pll_adc_clk32
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic
+ );
+end component;
+
+component pll_adc_clk192
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic
+ );
+end component;
+
component pll_adc_clk3125
port (
CLK : in std_logic;
DEBUG_OUT : out std_logic_vector(15 downto 0));
end component;
+-------------------------------------------------------------------------------
+-- ADC Handler
+-------------------------------------------------------------------------------
+component adc_ad9228
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic;
+ ADC_DCLK_IN : in std_logic;
+ ADC_SC_CLK32_OUT : out std_logic;
+ ADC_A_IN : in std_logic;
+ ADC_B_IN : in std_logic;
+ ADC_NX_IN : in std_logic;
+ ADC_D_IN : in std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+component adc_receiver
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ CLK_ADC_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SC_CLK32_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
-------------------------------------------------------------------------------
-- Misc Tools
-------------------------------------------------------------------------------
use work.trb_net_components.all;
use work.trb3_components.all;
use work.nxyter_components.all;
--- ADCM use work.adcmv3_components.all;
entity nXyter_FEE_board is
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- I2C Ports
- I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
- I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
- I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C StateMachine
- I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers to default
-
- -- ADC SPI
- SPI_SCLK_OUT : out std_logic;
- SPI_SDIO_INOUT : inout std_logic;
- SPI_CSB_OUT : out std_logic;
-
- -- nXyter Timestamp Ports
- NX_CLK128_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX_RESET_OUT : out std_logic;
- NX_TESTPULSE_OUT : out std_logic;
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ CLK_ADC_IN : in std_logic;
+
+ -- I2C Ports
+ I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
+ I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
+ I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine
+ I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers
+
+ -- ADC SPI
+ SPI_SCLK_OUT : out std_logic;
+ SPI_SDIO_INOUT : inout std_logic;
+ SPI_CSB_OUT : out std_logic;
+
+ -- nXyter Timestamp Ports
+ NX_CLK128_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_RESET_OUT : out std_logic;
+ NX_TESTPULSE_OUT : out std_logic;
-- ADC nXyter Pulse Hight Ports
- ADC_FCLK_IN : in std_logic;
- ADC_DCLK_IN : in std_logic;
- ADC_SC_CLK32_OUT : out std_logic;
- ADC_A_IN : in std_logic;
- ADC_B_IN : in std_logic;
- ADC_NX_IN : in std_logic;
- ADC_D_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SC_CLK32_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
-- TRBNet RegIO Port for the slave bus
REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
--
--
-- DEBUG_LINE_OUT(8) <= ADC_FCLK_IN;
--- DEBUG_LINE_OUT(9) <= ADC_DCLK_IN;
-- DEBUG_LINE_OUT(10) <= ADC_SC_CLK32_OUT;
-- DEBUG_LINE_OUT(11) <= ADC_A_IN;
-- DEBUG_LINE_OUT(12) <= ADC_B_IN;
-- ADC_DATA(1) => ADC_B_IN, -- adc_data_i,
-- ADC_DATA(2) => ADC_NX_IN, -- adc_data_i,
-- ADC_DATA(3) => ADC_D_IN, -- adc_data_i,
--- ADC_DCO(0) => ADC_DCLK_IN, -- adc_dat_clk_i,
-- ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i,
-- DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word,
-- FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco,
-- DEBUG => open
-- );
-
- adc_ad9228_1: adc_ad9228
+ adc_receiver_1: adc_receiver
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+ CLK_ADC_IN => CLK_ADC_IN,
+
ADC_FCLK_IN => ADC_FCLK_IN,
ADC_DCLK_IN => ADC_DCLK_IN,
ADC_SC_CLK32_OUT => ADC_SC_CLK32_OUT,
ADC_B_IN => ADC_B_IN,
ADC_NX_IN => ADC_NX_IN,
ADC_D_IN => ADC_D_IN,
+
--DEBUG_OUT => open,
DEBUG_OUT => DEBUG_LINE_OUT
);
+
+-- adc_ad9228_1: adc_ad9228
+-- port map (
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- ADC_FCLK_IN => ADC_FCLK_IN,
+-- ADC_DCLK_IN => ADC_DCLK_IN,
+-- ADC_SC_CLK32_OUT => ADC_SC_CLK32_OUT,
+-- ADC_A_IN => ADC_A_IN,
+-- ADC_B_IN => ADC_B_IN,
+-- ADC_NX_IN => ADC_NX_IN,
+-- ADC_D_IN => ADC_D_IN,
+-- --DEBUG_OUT => open,
+-- DEBUG_OUT => DEBUG_LINE_OUT
+-- );
-------------------------------------------------------------------------------
-- nXyter Signals
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd"
add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_clk3125.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd"
add_file -vhdl -lib "work" "cores/fifo_32to32_dc.vhd"
-add_file -vhdl -lib "work" "cores/fifo_dc_8to32_dyn.vhd"
-add_file -vhdl -lib "work" "source/fifo_dc_9to36_dyn.vhd"
+add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
+add_file -vhdl -lib "work" "cores/fifo_6to6_dc.vhd"
add_file -vhdl -lib "work" "trb3_periph.vhd"
# nXyter Files
-add_file -vhdl -lib "work" "./source/adcmv3_components.vhd"
-add_file -vhdl -lib "work" "./source/nxyter_components.vhd"
-
-add_file -vhdl -lib "work" "./source/nxyter.vhd"
-add_file -vhdl -lib "work" "./source/nxyter_data_handler.vhd"
-add_file -vhdl -lib "work" "./source/pll_nx_clk256.vhd"
-add_file -vhdl -lib "work" "./source/nxyter_registers.vhd"
-add_file -vhdl -lib "work" "./source/nx_timestamp_fifo_read.vhd"
-add_file -vhdl -lib "work" "./source/level_to_pulse.vhd"
-add_file -vhdl -lib "work" "./source/gray_decoder.vhd"
-add_file -vhdl -lib "work" "./source/gray_encoder.vhd"
-add_file -vhdl -lib "work" "./source/nx_data_buffer.vhd"
-add_file -vhdl -lib "work" "./source/fifo_32_data.vhd"
-add_file -vhdl -lib "work" "./source/nx_timer.vhd"
-
-add_file -vhdl -lib "work" "./source/nx_timestamp_decode.vhd"
-add_file -vhdl -lib "work" "./source/nx_timestamp_process.vhd"
-
-add_file -vhdl -lib "work" "./source/nx_i2c_master.vhd"
-add_file -vhdl -lib "work" "./source/nx_i2c_startstop.vhd"
-add_file -vhdl -lib "work" "./source/nx_i2c_sendbyte.vhd"
-add_file -vhdl -lib "work" "./source/nx_i2c_readbyte.vhd"
-
-add_file -vhdl -lib "work" "./source/adc_spi_master.vhd"
-add_file -vhdl -lib "work" "./source/adc_spi_sendbyte.vhd"
-add_file -vhdl -lib "work" "./source/adc_spi_readbyte.vhd"
-
-add_file -vhdl -lib "work" "./source/nx_fpga_timestamp.vhd"
-add_file -vhdl -lib "work" "./source/nx_trigger_generator.vhd"
-add_file -vhdl -lib "work" "./source/nx_trigger_handler.vhd"
-add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd"
+add_file -vhdl -lib "work" "source/nxyter_components.vhd"
+
+add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd"
+add_file -vhdl -lib "work" "source/nxyter_data_handler.vhd"
+add_file -vhdl -lib "work" "source/nxyter_registers.vhd"
+add_file -vhdl -lib "work" "source/nx_timestamp_fifo_read.vhd"
+add_file -vhdl -lib "work" "source/level_to_pulse.vhd"
+add_file -vhdl -lib "work" "source/gray_decoder.vhd"
+add_file -vhdl -lib "work" "source/gray_encoder.vhd"
+add_file -vhdl -lib "work" "source/nx_data_buffer.vhd"
+add_file -vhdl -lib "work" "source/nx_timer.vhd"
+
+add_file -vhdl -lib "work" "source/nx_timestamp_decode.vhd"
+add_file -vhdl -lib "work" "source/nx_timestamp_process.vhd"
+
+add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_sendbyte.vhd"
+add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd"
+
+add_file -vhdl -lib "work" "source/adc_spi_master.vhd"
+add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd"
+add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd"
+
+add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd"
+add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd"
+add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd"
+add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd"
+
+add_file -vhdl -lib "work" "source/adc_ad9228.vhd"
+add_file -vhdl -lib "work" "source/adc_receiver.vhd"
# Needed by ADC9222 Entity
add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd"
--Clocks
CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
NX1_ADC_NX_IN : in std_logic;
NX1_ADC_D_IN : in std_logic;
+ NX1B_ADC_FCLK_IN : in std_logic;
+ NX1B_ADC_DCLK_IN : in std_logic;
+ NX1B_ADC_A_IN : in std_logic;
+ NX1B_ADC_B_IN : in std_logic;
+ NX1B_ADC_NX_IN : in std_logic;
+ NX1B_ADC_D_IN : in std_logic;
+
--Connections to NXYTER-FEB 2
NX2_RESET_OUT : out std_logic;
--attribute syn_useioff of INP : signal is false;
attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
--attribute syn_useioff of DAC_SDO : signal is true;
--attribute syn_useioff of DAC_SDI : signal is true;
--attribute syn_useioff of DAC_SCK : signal is true;
attribute syn_preserve : boolean;
-- For 250MHz PLL nxyter clock, THE_256M_ODDR_1
- attribute ODDRAPPS : string;
- attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED";
+ -- attribute ODDRAPPS : string;
+ -- attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED";
--Clock / Reset
signal time_counter : unsigned(31 downto 0);
+ -- NXYTER Clock
+ signal pll_lock_clk256 : std_logic;
+
-- nXyter 1 Regio Bus
signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
signal nx1_regio_data_in : std_logic_vector (31 downto 0);
signal nx2_clk256_o : std_logic;
+
+ signal pll_192MHz : std_logic;
+
begin
---------------------------------------------------------------------------
-- Reset Generation
-- AddOn
---------------------------------------------------------------------------
+ pll_adc_clk192_1: pll_adc_clk192
+ port map (
+ CLK => CLK_PCLK_LEFT,
+ CLKOP => pll_192MHz,
+ LOCK => open
+ );
+
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
port map (
CLK_IN => clk_100_i,
RESET_IN => reset_i,
+ CLK_ADC_IN => CLK_PCLK_LEFT,
I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
NX_RESET_OUT => NX1_RESET_OUT,
NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
- ADC_FCLK_IN => NX1_ADC_FCLK_IN,
- ADC_DCLK_IN => NX1_ADC_DCLK_IN,
- ADC_SC_CLK32_OUT => NX1_ADC_SC_CLK32_OUT,
- ADC_A_IN => NX1_ADC_A_IN,
- ADC_B_IN => NX1_ADC_B_IN,
- ADC_NX_IN => NX1_ADC_NX_IN,
- ADC_D_IN => NX1_ADC_D_IN,
+ ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
+ ADC_SC_CLK32_OUT => NX1_ADC_SC_CLK32_OUT,
+ ADC_A_IN(0) => NX1_ADC_A_IN,
+ ADC_A_IN(1) => NX1B_ADC_A_IN,
+ ADC_B_IN(0) => NX1_ADC_B_IN,
+ ADC_B_IN(1) => NX1B_ADC_B_IN,
+ ADC_NX_IN(0) => NX1_ADC_NX_IN,
+ ADC_NX_IN(1) => NX1B_ADC_NX_IN,
+ ADC_D_IN(0) => NX1_ADC_D_IN,
+ ADC_D_IN(1) => NX1B_ADC_D_IN,
REGIO_ADDR_IN => nx1_regio_addr_in,
REGIO_DATA_IN => nx1_regio_data_in,
-- DEBUG_LINE_OUT => open
);
-
- pll_nx_clk256_1: pll_nx_clk256
+ pll_nx_clk256_1: entity work.pll_nx_clk256
port map (
CLK => clk_100_i,
CLKOP => NX1_CLK256A_OUT,
- LOCK => open
+ LOCK => pll_lock_clk256
);
-- -- 250MHz Clock to nXyters
--- pll_nx_clk250_1: pll_nx_clk250
+-- pll_nx_clk250_1: entity work.pll_nx_clk250
-- port map (
-- CLK => CLK_GPLL_LEFT,
-- CLKOP => NX1_CLK256A_OUT, -- nx1_clk256_o,
-- LOCK => open
-- );
- THE_256M_ODDR_1: ODDRXD1
- port map(
- SCLK => nx1_clk256_o,
- DA => '1',
- DB => '0',
- Q => open --NX1_CLK256A_OUT
- );
+-- THE_256M_ODDR_1: ODDRXD1
+-- port map(
+-- SCLK => nx1_clk256_o,
+-- DA => '1',
+-- DB => '0',
+-- Q => open --NX1_CLK256A_OUT
+-- );
-------------------------------------------------------------------------------
FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
- FREQUENCY PORT NX1_CLK256A_OUT 250 MHz;
+ FREQUENCY PORT NX1_CLK256A_OUT 256 MHz;
#Put the names of your nxyter inputs here:
- FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz;
- FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;
FREQUENCY PORT NX1_CLK128_IN 128 MHz;
FREQUENCY PORT NX2_CLK128_IN 128 MHz;
-
+ FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz;
+ FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;
+
#Change the next two lines to the clk_fast signal of the ADC
-# USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast";
-# USE PRIMARY NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast";
+ USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_receiver_1/pll_192MHz";
+ USE PRIMARY NET "nXyter_FEE_board_1/adc_receiver_1/pll_192MHz";
USE PRIMARY NET "CLK_PCLK_LEFT";
USE PRIMARY NET "CLK_PCLK_LEFT_c";
+
+ # USE PRIMARY NET "CLK_GPLL_RIGHT";
+ # USE PRIMARY NET "CLK_GPLL_RIGHT_c";
+
+ USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT";
+ USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT_c";
+
+
#################################################################
# Reset Nets
INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ;
MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c_c" 50 ns;
+
+
+
+
+
+
+
+#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c";
+#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";
+
package version is
- constant VERSION_NUMBER_TIME : integer := 1365511005;
+ constant VERSION_NUMBER_TIME : integer := 1366059697;
end package version;
+Zum Kompilieren:
+das in workdir aufrufen falls die links weg sind:
+/home/rich/TRB/nXyter/trb3/base/linkdesignfiles.sh
+
+
+
Zum debuggen: see workdir/*
.srr
.mrp
jspc29 / trb3.git / commitdiff