new timeout, added timeout to flush_channel function

diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c
index 4f339d4ae70fc711547ca8145b99a0ce1a07b314..552ffe0429594ba6754035aee27dacedf38a86f2 100644 (file)
--- a/libtrbnet/trbnet.c
+++ b/libtrbnet/trbnet.c
@@ -1,4 +1,4 @@
-const char trbnet_version[] = "$Revision: 2.70 $";
+const char trbnet_version[] = "$Revision: 2.71 $";
 
 #include <stdlib.h>
 #include <signal.h>
@@ -128,7 +128,7 @@ const char trbnet_version[] = "$Revision: 2.70 $";
 #define SHORT_TRANSFER                   0x0100
 
 /* Other  */
-#define MAX_TIME_OUT                     1500000
+#define MAX_TIMEOUT                      5000000
 #define DATA_BUFFER_SIZE                 8192
 
 /* ---------------------------------------------------------------------- */
@@ -389,7 +389,10 @@ static void fifo_flush(uint8_t channel)
   
   fifoAddress = CHANNEL_N_RECEIVER_DATA | ((channel * 2 + 1) << 4);
   do {
-    read32_from_FPGA(fifoAddress, &tmp);
+    unsigned int timeout = 0;
+    do {
+      read32_from_FPGA(fifoAddress, &tmp);
+    } while (((tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
     /* DEBUG INFO */
     if ((trb_debug > 1) && ((tmp & MASK_FIFO_VALID) != 0)) {
       fprintf(stderr, "FLUSH_FIFO_%03d:  0x%08x\n", counter, tmp);
@@ -408,7 +411,7 @@ static int trb_wait_tx_not_busy(uint8_t channel)
     return -1;
   }
 
-  while (timeout < MAX_TIME_OUT) {
+  while (timeout < MAX_TIMEOUT) {
     read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
     if ((tmp & MASK_TX_RUNNING) == 0) {
       return 0;
@@ -440,7 +443,7 @@ static int trb_init_transfer(uint8_t channel)
                    &tmp);
   if ((tmp & MASK_FIFO_EMPTY) == 0) {
     trb_errno = TRB_FIFO_NOT_EMPTY;
-    /* clear fifo ???*/
+    fifo_flush(channel);
     return -1;
   }
 
@@ -494,15 +497,15 @@ static int trb_fifo_read(uint8_t channel,
     do {
       dma_size =
         read32_from_FPGA_dma(fifoBuffer, tmp, DATA_BUFFER_SIZE);
-    } while ((dma_size == 0) && (++timeout < MAX_TIME_OUT));
+    } while ((dma_size == 0) && (++timeout < MAX_TIMEOUT));
   } else {
     /* Standard */
     do {
       read32_from_FPGA(fifoBuffer, tmp);
-    } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT));
+    } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
   }
 
-  if (timeout >= MAX_TIME_OUT) {
+  if (timeout >= MAX_TIMEOUT) {
     fifo_flush(channel);
     trb_errno = TRB_FIFO_TIMEOUT;
     return -1;
@@ -877,9 +880,9 @@ static int trb_fifo_read(uint8_t channel,
       timeout = 0;
       do {
        read32_from_FPGA(fifoBuffer, tmp);
-      } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT));
+      } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIMEOUT));
 
-      if (timeout >= MAX_TIME_OUT) {
+      if (timeout >= MAX_TIMEOUT) {
        fifo_flush(channel);
        trb_errno = TRB_FIFO_INCOMPLETE;
        return -1;