updated signal description for deepsea branch signals

diff --git a/trb3/DS_SignalDescription.tex b/trb3/DS_SignalDescription.tex
index aa0b883e396119a9fa5cbe0865e5647e95730c0b..cfb8c4b634b06b2d13b617f6e75017f88569af6d 100644 (file)
--- a/trb3/DS_SignalDescription.tex
+++ b/trb3/DS_SignalDescription.tex
@@ -7,14 +7,49 @@ The signals used in the SerDes TX and RX state machines are taken from the Latti
 example code available on the web. These state machines behave the same, but have been extended 
 to include TX channel serializer synchronization and RX channel WordAlignment.
 
+\subsubsection{\texttt{med\_ecp3\_sfp\_sync\_all\_RS}}
+
 \begin{itemize*}
-  \item \texttt{LINK\_TX\_READY} is set when the TX PLLs inside \textbf{all used} QUADs are locked, 
-  the serializers are synced and kommas can be transmitted.
-  \item \texttt{LINK\_RX\_READY} is set when the RX CDR of \textbf{one specific} SerDes is locked, 
-  correct word alignment is found and kommas can be received.
-  \item \texttt{LINK\_HALF\_DONE} is set when a SerDes has received a sequence of at least 16 toggling
-  idles.
-  \item \texttt{LINK\_FULL\_DONE} is set when a SerDes has received a sequence of at least 16 steady
-  idles after having set the \texttt{LINK\_HALF\_DONE} signal.
-  \item \texttt{xxx}
+  \item \texttt{RX\_DLM\_OUT} -- DLM komma received, per channel.\newline
+        Signal is set for one clock cycle of \texttt{RXI\_CLK}. 
+  \item \texttt{RX\_DLM\_WORD\_OUT} -- DLM data byte received, per channel. 
+  \item \texttt{TX\_DLM\_IN} -- send one DLM komma.\newline
+        Data byte must be valid when this signal is set for one clock cycle
+        of \texttt{TXI\_CLK}.
+  \item \texttt{TX\_DLM\_WORD\_IN} -- DLM data byte to be sent.\newline
+        A SP needs to connect these ports directly together to implement \texttt{DLM} komma
+        ping functionality, used for link delay measurements.
+  \item \texttt{RX\_RST\_OUT} -- RST komma received, per channel (only for SP).
+  \item \texttt{RX\_RST\_WORD\_OUT} -- RST data byte received (only for SP).\newline
+        Can be used directly as reset lines.
+  \item \texttt{TX\_RST\_IN} -- send one RST komma, is only forwarded to MPs.\newline
+        RST kommas can not be sent on SPs.\newline
+        In configurations with one SP and at least one MP, these \texttt{RX\_RST} ports
+        of SP must be connected to \texttt{TX\_RST} ports of all Quads with MPs.
+  \item \texttt{TX\_RST\_WORD\_IN} -- RST data byte to be sent.
+  \item \texttt{WORD\_SYNC\_IN} -- byte/word alignment input for MPs.\newline
+        On root MP, this input must be static high, on hub MPs it connects to
+        SP \texttt{WORD\_SYNC\_OUT} to keep links word aligned.
+  \item \texttt{WORD\_SYNC\_OUT} -- only valid if a SP is in the MI. Connects to 
+        \texttt{WORD\_SYNC\_IN} of all Quads containing MPs.
+  \item \texttt{MASTER\_CLK\_IN} -- clock used on TX PLL inside Quad.
+  \item \texttt{MASTER\_CLK\_OUT} -- recovered RX clock, if SP is available in the Quad.
+  \item \texttt{GLOBAL\_RESET\_IN} -- used for initial Quad reset (\texttt{RST\_QD\_C}) and keeping
+        SerDes related function blocks in reset. Usually connects to \texttt{GLOBAL\_RESET\_OUT} of 
+        the SP.
+  \item \texttt{GLOBAL\_RESET\_OUT} -- only valid on SP, signal is derived from \texttt{SFP\_LOS} signal
+        on uplink. Used to keep FPGA logic in hard reset. 
+  \item \texttt{TX\_PLL\_LOL\_IN} -- wired or of all \texttt{TX\_PLL\_LOL} signals of all Quads used in
+        the FPGA. Usually originates from \texttt{main\_tx\_reset\_RS} component.
+  \item \texttt{TX\_PLL\_LOL\_OUT} -- TX PLL lock signal from SerDes inside the MI. Usually connected to
+        the corresponding input of \texttt{main\_tx\_reset\_RS} component.
+  \item \texttt{TX\_CLK\_AVAIL\_OUT} -- only valid on SP. Signals valid recovered RX clock is available.
+        Usually connected to \texttt{main\_tx\_reset\_RS} component.
+  \item \texttt{TX\_PCS\_RST\_IN} -- reset for TX PCS blocks inside the Quad. Usually connected to 
+        \texttt{main\_tx\_reset\_RS} component.
+  \item \texttt{SYNC\_TX\_PLL\_IN} -- TX Serializer sync signal. Usually connected to \texttt{main\_tx\_reset\_RS} 
+        component. 
+  \item \texttt{DESTROY\_LINK\_IN} -- one bit signal per channel, only used for MPs. If set, the 
+        \texttt{SFP\_TX\_DISABLE} line to SFP is set and all connected boards will be forced into
+        hard reset. 
 \end{itemize*}