SDA_OUT : out std_logic;
SCL_IN : in std_logic;
SCL_OUT : out std_logic;
- STAT : out std_logic_vector(31 downto 0));
+ STAT : out std_logic_vector(31 downto 0)
+ );
end component i2c_master;
-
component I2C_GSTART
port (
CLK_IN : in std_logic;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
DOBYTE_IN : in std_logic;
- I2C_SPEED_IN : in std_logic_vector(7 downto 0);
+ I2C_SPEED_IN : in std_logic_vector(8 downto 0);
I2C_BYTE_IN : in std_logic_vector(8 downto 0);
I2C_BACK_OUT : out std_logic_vector(8 downto 0);
SDA_IN : in std_logic;
RESET_IN : in std_logic;
I2C_GO_IN : in std_logic;
ACTION_IN : in std_logic;
- I2C_SPEED_IN : in std_logic_vector(5 downto 0);
+ I2C_SPEED_IN : in std_logic_vector(8 downto 0);
I2C_ADR_IN : in std_logic_vector(7 downto 0);
I2C_CMD_IN : in std_logic_vector(7 downto 0);
I2C_DW_IN : in std_logic_vector(7 downto 0);
begin -- Gray_Decoder
PROC_DECODER: process (CLK_IN)
+ variable b : std_logic_vector(WIDTH -1 downto 0) := (others => '0');
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- binary_o <= (others => '0');
+ b := (others => '0');
else
- binary_o(WIDTH - 1) <= GRAY_IN(WIDTH - 1);
+ b(WIDTH - 1) := GRAY_IN(WIDTH - 1);
- for I in (WIDTH - 2) to 0 loop
- binary_o(I) <= binary_o(I + 1) xor GRAY_IN(I);
+ for I in (WIDTH - 2) downto 0 loop
+ b(I) := b(I + 1) xor GRAY_IN(I);
end loop;
end if;
end if;
-
+ binary_o <= b;
end process PROC_DECODER;
- -- Output
+-- Output
BINARY_OUT <= binary_o;
end Gray_Decoder;
gray_o <= (others => '0');
else
gray_o(WIDTH - 1) <= BINARY_IN(WIDTH -1);
- for I in (WIDTH - 2) to 0 loop
+ for I in (WIDTH - 2) downto 0 loop
gray_o(I) <= BINARY_IN(I + 1) xor BINARY_IN(I);
end loop;
end if;
end if;
- GRAY_O <= gray_o;
end process PROC_ENCODER;
-- Output
RESET_IN : in std_logic;\r
START_IN : in std_logic;\r
DOSTART_IN : in std_logic;\r
- I2C_SPEED_IN : in std_logic_vector(7 downto 0);\r
+ I2C_SPEED_IN : in std_logic_vector(8 downto 0);\r
SDONE_OUT : out std_logic;\r
SOK_OUT : out std_logic;\r
SDA_IN : in std_logic;\r
signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
signal bsm : std_logic_vector(3 downto 0);\r
- signal cctr : std_logic_vector(7 downto 0); -- counter for bit length\r
+ signal cctr : unsigned(8 downto 0); -- counter for bit length\r
\r
signal cycdone_x : std_logic;\r
signal cycdone : std_logic; -- one counter period done\r
end process THE_CYC_CTR_PROC;\r
\r
-- end of cycle recognition\r
- cycdone_x <= '1' when (cctr = x"00") else '0';\r
+ cycdone_x <= '1' when (cctr = 0) else '0';\r
\r
-- The main state machine\r
-- State memory process\r
signal status_data : std_logic_vector(31 downto 0);\r
signal i2c_debug : std_logic_vector(31 downto 0);\r
\r
+ signal i2c_speed_static : std_logic_vector(8 downto 0);\r
+ \r
begin\r
\r
---------------------------------------------------------\r
-- I2C command / setup\r
I2C_GO_IN => reg_slv_data_in(31),\r
ACTION_IN => reg_slv_data_in(30),\r
- I2C_SPEED_IN => reg_slv_data_in(29 downto 24),\r
+ I2C_SPEED_IN => i2c_speed_static,\r
I2C_ADR_IN => reg_slv_data_in(23 downto 16),\r
I2C_CMD_IN => reg_slv_data_in(15 downto 8),\r
I2C_DW_IN => reg_slv_data_in(7 downto 0),\r
status_data(23 downto 21) <= (others => '0');\r
status_data(20 downto 16) <= i2c_debug(4 downto 0);\r
status_data(15 downto 8) <= (others => '0');\r
-\r
+ i2c_speed_static <= (others => '1');\r
+ \r
-- Fake\r
stat <= i2c_debug;\r
\r
CLK_IN : in std_logic;\r
RESET_IN : in std_logic;\r
DOBYTE_IN : in std_logic;\r
- I2C_SPEED_IN : in std_logic_vector( 7 downto 0 );\r
+ I2C_SPEED_IN : in std_logic_vector( 8 downto 0 );\r
I2C_BYTE_IN : in std_logic_vector( 8 downto 0 );\r
I2C_BACK_OUT : out std_logic_vector( 8 downto 0 );\r
SDA_IN : in std_logic;\r
R_SDA_OUT : out std_logic;\r
S_SDA_OUT : out std_logic;\r
--- SCL_IN : in std_logic;\r
R_SCL_OUT : out std_logic;\r
S_SCL_OUT : out std_logic;\r
BDONE_OUT : out std_logic;\r
signal s_scl : std_logic; -- output for SCL\r
\r
signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9)\r
- signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length\r
+ signal cctr : unsigned(8 downto 0); -- counter for bit length\r
signal bok : std_logic;\r
signal cycdone : std_logic; -- one counter period done\r
signal bytedone : std_logic; -- all bits sents\r
end process THE_BIT_CTR_PROC;\r
\r
-- end of byte recognition\r
- bytedone <= '1' when (bctr = x"9") else '0';\r
+ bytedone <= '1' when (bctr = x"a") else '0';\r
\r
-- Countdown for one half of SCL (adjustable clock width)\r
THE_CYC_CTR_PROC: process( clk_in )\r
end process THE_CYC_CTR_PROC;\r
\r
-- end of cycle recognition\r
- cycdone <= '1' when (cctr = x"00") else '0';\r
+ cycdone <= '1' when (cctr = 0) else '0';\r
\r
-- Bit output\r
THE_BIT_OUT_PROC: process( clk_in )\r
library work;\r
use work.adcmv3_components.all;\r
\r
--- BUG: does alway set bit 0 of address byte to zero !!!!\r
--- REMARK: this is not a bug, but a feature....\r
-\r
entity i2c_slim is\r
- port(\r
+ port (\r
CLK_IN : in std_logic;\r
RESET_IN : in std_logic;\r
\r
-- I2C command / setup\r
I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions\r
ACTION_IN : in std_logic; -- '0' -> write, '1' -> read\r
- I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined)\r
+ I2C_SPEED_IN : in std_logic_vector( 8 downto 0 ); -- speed adjustment\r
I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored)\r
I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte)\r
I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command\r
\r
signal gs_debug : std_logic_vector(3 downto 0);\r
\r
- signal i2c_speed : std_logic_vector(7 downto 0);\r
+ signal i2c_speed : std_logic_vector(8 downto 0);\r
\r
begin\r
\r
- i2c_speed <= i2c_speed_in & "00";\r
+ i2c_speed <= I2C_SPEED_IN & "00";\r
\r
-- Read phase indicator\r
THE_PHASE_PROC: process( clk_in )\r
NEXT_STATE <= LOADC; -- I2C write\r
load_c_x <= '1';\r
elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then\r
- NEXT_STATE <= LOADC; -- I2C read, send register address\r
+ NEXT_STATE <= LOADC; -- I2C read, send register address\r
load_c_x <= '1';\r
elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then\r
- NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
+ NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte\r
load_d_x <= '1';\r
elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then\r
NEXT_STATE <= E_ADDR; -- first address phase failed\r
end process DECODE;\r
\r
-- We need to load different data sets\r
---LOAD_DATA_PROC: process( clk_in, reset_in, CURRENT_STATE, action_in, phase)\r
LOAD_DATA_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then\r
i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK\r
elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then\r
- i2c_byte <= i2c_cmd_in(7 downto 1) & '0' & '1'; -- send command byte (WRITE), receive ACK\r
+ i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK\r
elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then\r
- i2c_byte <= i2c_cmd_in(7 downto 1) & '1' & '1'; -- send command byte (READ), receive ACK\r
+ i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK\r
elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then\r
i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK\r
elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then\r
I2C_BACK_OUT => i2c_dr,\r
SDA_IN => sda_in,\r
R_SDA_OUT => r_sda_sb,\r
- S_SDA_OUT => s_sda_sb,\r
--- SCL_IN => scl_in,\r
+ S_SDA_OUT => s_sda_sb,\r
R_SCL_OUT => r_scl_sb,\r
S_SCL_OUT => s_scl_sb,\r
BDONE_OUT => bdone,\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_i2c_master is\r
+ generic (\r
+ i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- I2C connections\r
+ SDA_INOUT : inout std_logic;\r
+ SCL_INOUT : inout std_logic;\r
+\r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_master is\r
+\r
+ signal sda_i : std_logic;\r
+ signal sda_x : std_logic;\r
+ signal sda : std_logic;\r
+\r
+ signal scl_i : std_logic;\r
+ signal scl_x : std_logic;\r
+ signal scl : std_logic;\r
+\r
+ -- I2C Master \r
+ signal sda_o : std_logic;\r
+ signal scl_o : std_logic;\r
+ signal i2c_start : std_logic;\r
+ \r
+ signal startstop_select : std_logic;\r
+ signal startstop_seq_start : std_logic;\r
+ signal sendbyte_seq_start : std_logic;\r
+ signal sendbyte_byte : std_logic_vector(7 downto 0);\r
+\r
+ signal startstop_select_x : std_logic;\r
+ signal startstop_seq_start_x : std_logic;\r
+ signal wait_timer_init_x : std_logic_vector(11 downto 0);\r
+ signal sendbyte_seq_start_x : std_logic;\r
+ signal sendbyte_byte_x : std_logic_vector(7 downto 0);\r
+ signal i2c_ack_x : std_logic;\r
+ \r
+ signal sda_startstop : std_logic;\r
+ signal scl_startstop : std_logic;\r
+ signal sda_sendbyte : std_logic;\r
+ signal scl_sendbyte : std_logic;\r
+ signal startstop_done : std_logic;\r
+\r
+ signal sendbyte_done : std_logic;\r
+ signal sendbyte_ack : std_logic;\r
+ signal i2c_ack : std_logic;\r
+ signal i2c_notready : std_logic;\r
+ signal i2c_error : std_logic_vector(3 downto 0);\r
+\r
+ type STATES is (S_IDLE,\r
+ S_START,\r
+ S_START_WAIT,\r
+\r
+ S_SEND_CHIP_ID,\r
+ S_SEND_CHIP_ID_WAIT,\r
+ S_SEND_REGISTER,\r
+ S_SEND_REGISTER_WAIT,\r
+\r
+ S_STOP,\r
+ S_STOP_WAIT\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+\r
+ \r
+ -- I2C Timer\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
+ signal wait_timer_done : std_logic;\r
+ \r
+ -- TRBNet Slave Bus \r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ signal reg_data : std_logic_vector(31 downto 0);\r
+ signal i2c_chipid : std_logic_vector(6 downto 0);\r
+ signal i2c_rw_bit : std_logic;\r
+ signal i2c_registerid : std_logic_vector(7 downto 0);\r
+ signal i2c_register_data : std_logic_vector(7 downto 0);\r
+ signal i2c_register_value_read : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_i2c_timer_1: nx_i2c_timer\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+ -- Start / Stop Sequence\r
+ nx_i2c_startstop_1: nx_i2c_startstop\r
+ generic map (\r
+ i2c_speed => i2c_speed\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => startstop_seq_start,\r
+ SELECT_IN => startstop_select,\r
+ SEQUENCE_DONE_OUT => startstop_done,\r
+ SDA_OUT => sda_startstop,\r
+ SCL_OUT => scl_startstop,\r
+ NREADY_OUT => i2c_notready\r
+ );\r
+\r
+ nx_i2c_sendbyte_1: nx_i2c_sendbyte\r
+ generic map (\r
+ i2c_speed => i2c_speed\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => sendbyte_seq_start,\r
+ BYTE_IN => sendbyte_byte,\r
+ SEQUENCE_DONE_OUT => sendbyte_done,\r
+ SDA_OUT => sda_sendbyte,\r
+ SCL_OUT => scl_sendbyte,\r
+ SDA_IN => sda,\r
+ ACK_OUT => sendbyte_ack\r
+ );\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT(0) <= sda_o;\r
+ DEBUG_OUT(1) <= scl_o;\r
+ DEBUG_OUT(2) <= i2c_start;\r
+ DEBUG_OUT(3) <= startstop_done;\r
+ DEBUG_OUT(4) <= sda_startstop;\r
+ DEBUG_OUT(5) <= scl_startstop;\r
+ DEBUG_OUT(6) <= sda_sendbyte;\r
+ DEBUG_OUT(7) <= scl_sendbyte;\r
+ \r
+-- DEBUG_OUT(11 downto 8) <= i2c_error;\r
+\r
+ DEBUG_OUT(15 downto 8) <= (others => '0');\r
+\r
+ i2c_error(0) <= i2c_notready;\r
+ i2c_error(1) <= not sendbyte_ack;\r
+ i2c_error(3 downto 2) <= (others => '0');\r
+ \r
+ -- Sync I2C Lines\r
+ sda_i <= SDA_INOUT;\r
+ scl_i <= SCL_INOUT;\r
+\r
+ PROC_I2C_LINES_SYNC: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sda_x <= '1';\r
+ sda <= '1';\r
+\r
+ scl_x <= '1';\r
+ scl <= '1';\r
+ else\r
+ sda_x <= sda_i;\r
+ sda <= sda_x;\r
+\r
+ scl_x <= scl_i;\r
+ scl <= scl_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_LINES_SYNC;\r
+\r
+ PROC_I2C_MASTER_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ i2c_ack <= '0';\r
+ startstop_select <= '0';\r
+ startstop_seq_start <= '0';\r
+ sendbyte_seq_start <= '0';\r
+ sendbyte_byte <= (others => '0');\r
+ wait_timer_init <= (others => '0');\r
+ STATE <= S_IDLE;\r
+ else\r
+ i2c_ack <= i2c_ack_x;\r
+ startstop_select <= startstop_select_x;\r
+ startstop_seq_start <= startstop_seq_start_x;\r
+ sendbyte_seq_start <= sendbyte_seq_start_x;\r
+ sendbyte_byte <= sendbyte_byte_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_MASTER_TRANSFER;\r
+ \r
+ \r
+ PROC_I2C_MASTER: process(STATE)\r
+ begin\r
+ -- Defaults\r
+ sda_o <= '1';\r
+ scl_o <= '1';\r
+ i2c_ack_x <= '0';\r
+ startstop_select_x <= '0';\r
+ startstop_seq_start_x <= '0';\r
+ sendbyte_seq_start_x <= '0';\r
+ sendbyte_byte_x <= (others => '0');\r
+ wait_timer_init_x <= (others => '0');\r
+ \r
+ case STATE is\r
+\r
+ when S_IDLE =>\r
+ if (i2c_start = '1') then\r
+ NEXT_STATE <= S_START;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ -- I2C START Sequence \r
+ when S_START =>\r
+ startstop_select_x <= '1';\r
+ startstop_seq_start_x <= '1';\r
+ NEXT_STATE <= S_START_WAIT;\r
+ \r
+ when S_START_WAIT =>\r
+ if (startstop_done = '0') then\r
+ NEXT_STATE <= S_START_WAIT;\r
+ else\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ NEXT_STATE <= S_SEND_CHIP_ID;\r
+ end if;\r
+ \r
+ -- I2C SEND ChipId Sequence\r
+ when S_SEND_CHIP_ID =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ sendbyte_byte_x(7 downto 1) <= i2c_chipid;\r
+ sendbyte_byte_x(0) <= i2c_rw_bit;\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
+ \r
+ when S_SEND_CHIP_ID_WAIT =>\r
+ if (sendbyte_done = '0') then\r
+ NEXT_STATE <= S_SEND_CHIP_ID_WAIT;\r
+ else\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ NEXT_STATE <= S_SEND_REGISTER;\r
+ end if;\r
+\r
+ -- I2C SEND RegisterId Sequence\r
+\r
+ when S_SEND_REGISTER =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ sendbyte_byte_x <= i2c_registerid;\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
+ \r
+ when S_SEND_REGISTER_WAIT =>\r
+ if (sendbyte_done = '0') then\r
+ NEXT_STATE <= S_SEND_REGISTER_WAIT;\r
+ else\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ NEXT_STATE <= S_STOP;\r
+ end if;\r
+ \r
+ -- I2C STOP Sequence \r
+ when S_STOP =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ startstop_select_x <= '0';\r
+ startstop_seq_start_x <= '1';\r
+ NEXT_STATE <= S_STOP_WAIT;\r
+ \r
+ when S_STOP_WAIT =>\r
+ if (startstop_done = '0') then\r
+ NEXT_STATE <= S_STOP_WAIT;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ end case;\r
+ end process PROC_I2C_MASTER;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- TRBNet Slave Bus\r
+ -----------------------------------------------------------------------------\r
+\r
+ PROC_SLAVE_BUS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ reg_data <= x"affeaffe";\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ i2c_start <= '0';\r
+\r
+ i2c_chipid <= (others => '0'); \r
+ i2c_rw_bit <= '0'; \r
+ i2c_registerid <= (others => '0'); \r
+ i2c_register_data <= (others => '0'); \r
+ i2c_register_value_read <= (others => '0');\r
+ \r
+ else\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ slv_data_out_o <= (others => '0');\r
+ i2c_start <= '0';\r
+ \r
+ if (SLV_WRITE_IN = '1') then\r
+ i2c_chipid <= SLV_DATA_IN(30 downto 24);\r
+ i2c_registerid <= SLV_DATA_IN(23 downto 16);\r
+ i2c_rw_bit <= SLV_DATA_IN(8);\r
+ i2c_register_data <= SLV_DATA_IN(7 downto 0); \r
+ i2c_start <= '1';\r
+ elsif (SLV_READ_IN = '1') then\r
+ slv_data_out_o <= reg_data;\r
+ \r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if; \r
+ end process PROC_SLAVE_BUS;\r
+\r
+\r
+\r
+-- Write bit definition OLD boehmer\r
+-- ====================\r
+-- \r
+-- \r
+-- D[31] I2C_GO 0 => don't do anything on I2C, 1 => start I2C access\r
+-- D[30] I2C_ACTION 0 => write byte, 1 => read byte\r
+-- D[29:24] I2C_SPEED set to all '1'\r
+-- D[23:16] I2C_ADDRESS address of I2C chip\r
+-- D[15:8] I2C_CMD command byte for access\r
+-- D[7:0] I2C_DATA data to be written\r
+--\r
+--\r
+ \r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ -- I2c Outputs\r
+ SDA_INOUT <= '0' when (sda_o = '0' or\r
+ sda_startstop = '0' or\r
+ sda_sendbyte = '0')\r
+ else 'Z';\r
+ \r
+ SCL_INOUT <= '0' when (scl_o = '0' or\r
+ scl_startstop = '0' or\r
+ scl_sendbyte = '0')\r
+ else 'Z';\r
+\r
+ -- Slave Bus\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_i2c_master is\r
+ generic (\r
+ i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- I2C connections\r
+ SDA_INOUT : inout std_logic;\r
+ SCL_INOUT : inout std_logic;\r
+\r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_master is\r
+\r
+ signal sda_i : std_logic;\r
+ signal sda_x : std_logic;\r
+ signal sda : std_logic;\r
+\r
+ signal scl_i : std_logic;\r
+ signal scl_x : std_logic;\r
+ signal scl : std_logic;\r
+\r
+ -- I2C Master \r
+ signal sda_o : std_logic;\r
+ signal scl_o : std_logic;\r
+ signal i2c_start : std_logic;\r
+\r
+ signal sda_startstop : std_logic;\r
+ signal scl_startstop : std_logic;\r
+ signal startstop_select : std_logic;\r
+ signal startstop_seq_start : std_logic;\r
+ signal startstop_done : std_logic;\r
+\r
+ signal sda_sendbyte : std_logic;\r
+ signal scl_sendbyte : std_logic;\r
+ signal sendbyte_seq_start : std_logic;\r
+ signal sendbyte_byte : std_logic_vector(7 downto 0);\r
+ signal sendbyte_done : std_logic;\r
+ signal sendbyte_ack : std_logic;\r
+\r
+ signal i2c_byte : unsigned(7 downto 0);\r
+ signal bit_ctr : unsigned(3 downto 0);\r
+ signal i2c_ack : std_logic;\r
+ signal i2c_error : std_logic_vector(3 downto 0);\r
+\r
+ type STATES is (S_IDLE,\r
+ S_START,\r
+ S_START_WAIT,\r
+ \r
+ S_SEND_BYTE,\r
+ S_SET_SDA,\r
+ S_SET_SCL,\r
+ S_UNSET_SCL,\r
+ S_NEXT_BIT,\r
+\r
+ S_GET_ACK,\r
+ S_ACK_SET_SCL,\r
+ S_STORE_ACK,\r
+ S_ACK_UNSET_SCL,\r
+ S_VERIFY_ACK,\r
+ S_ACK_ERROR,\r
+ \r
+ S_STOP,\r
+ S_STOP_WAIT\r
+ );\r
+ signal STATE : STATES;\r
+\r
+ \r
+ -- I2C Timer\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
+ signal wait_timer_done : std_logic;\r
+ \r
+ -- TRBNet Slave Bus\r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ signal reg_data : std_logic_vector(31 downto 0);\r
+ signal i2c_chipid : std_logic_vector(6 downto 0);\r
+ signal i2c_rw_bit : std_logic;\r
+\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_i2c_timer_1: nx_i2c_timer\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+ -- Start / Stop Sequence\r
+ nx_i2c_startstop_1: nx_i2c_startstop\r
+ generic map (\r
+ i2c_speed => i2c_speed\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => startstop_seq_start,\r
+ SELECT_IN => startstop_select,\r
+ SEQUENCE_DONE_OUT => startstop_done,\r
+ SDA_OUT => sda_startstop,\r
+ SCL_OUT => scl_startstop\r
+ );\r
+\r
+ nx_i2c_sendbyte_1: nx_i2c_sendbyte\r
+ generic map (\r
+ i2c_speed => i2c_speed\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => sendbyte_seq_start,\r
+ BYTE_IN => sendbyte_byte,\r
+ SEQUENCE_DONE_OUT => sendbyte_done,\r
+ SDA_OUT => sda_sendbyte,\r
+ SCL_OUT => scl_sendbyte,\r
+ SDA_IN => sda,\r
+ ACK_OUT => sendbyte_ack\r
+ );\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT(0) <= sda_o;\r
+ DEBUG_OUT(1) <= scl_o;\r
+ DEBUG_OUT(2) <= i2c_start;\r
+ DEBUG_OUT(3) <= wait_timer_done;\r
+ DEBUG_OUT(7 downto 4) <= i2c_error;\r
+\r
+ DEBUG_OUT(15 downto 8) <= (others => '0');\r
+ \r
+ -- Sync I2C Lines\r
+ sda_i <= SDA_INOUT;\r
+ scl_i <= SCL_INOUT;\r
+\r
+ PROC_I2C_LINES_SYNC: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sda_x <= '1';\r
+ sda <= '1';\r
+\r
+ scl_x <= '1';\r
+ scl <= '1';\r
+ else\r
+ sda_x <= sda_i;\r
+ sda <= sda_x;\r
+\r
+ scl_x <= scl_i;\r
+ scl <= scl_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_LINES_SYNC;\r
+\r
+ PROC_I2C_MASTER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sda_o <= '1';\r
+ scl_o <= '1';\r
+ wait_timer_init <= (others => '0');\r
+ bit_ctr <= (others => '0');\r
+ i2c_ack <= '0';\r
+ i2c_error <= (others => '0');\r
+ startstop_select <= '0';\r
+ startstop_seq_start <= '0';\r
+ STATE <= S_IDLE;\r
+ else\r
+ sda_o <= '1';\r
+ scl_o <= '1';\r
+ wait_timer_init <= (others => '0');\r
+ startstop_select <= '0';\r
+ startstop_seq_start <= '0';\r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (i2c_start = '1') then\r
+ STATE <= S_START;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ -- I2C START Sequence \r
+ when S_START =>\r
+ i2c_ack <= '0';\r
+ startstop_select <= '1';\r
+ startstop_seq_start <= '1';\r
+ STATE <= S_START_WAIT;\r
+\r
+ when S_START_WAIT =>\r
+ if (startstop_done = '0') then\r
+ STATE <= S_START_WAIT;\r
+ else\r
+ STATE <= S_SEND_BYTE;\r
+ end if;\r
+ \r
+ -- I2C Send byte\r
+ when S_SEND_BYTE =>\r
+ bit_ctr <= x"7";\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ i2c_byte(7 downto 1) <= i2c_chipid;\r
+ i2c_byte(0) <= i2c_rw_bit;\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_SET_SDA;\r
+\r
+ when S_SET_SDA =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_SET_SDA;\r
+ else\r
+ wait_timer_init <= i2c_speed srl 1;\r
+ STATE <= S_SET_SCL;\r
+ end if;\r
+\r
+ when S_SET_SCL =>\r
+ sda_o <= i2c_byte(7);\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_SET_SCL;\r
+ else\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_UNSET_SCL;\r
+ end if;\r
+\r
+ when S_UNSET_SCL =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_UNSET_SCL;\r
+ else\r
+ STATE <= S_NEXT_BIT;\r
+ end if;\r
+ \r
+ when S_NEXT_BIT =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (bit_ctr > 0) then\r
+ bit_ctr <= bit_ctr - 1;\r
+ i2c_byte <= i2c_byte sll 1;\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_SET_SDA;\r
+ else\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_GET_ACK;\r
+ end if;\r
+\r
+ -- I2C Check ACK Sequence\r
+ when S_GET_ACK =>\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_GET_ACK;\r
+ else\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_ACK_SET_SCL;\r
+ end if;\r
+\r
+ when S_ACK_SET_SCL =>\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_ACK_SET_SCL;\r
+ else\r
+ STATE <= S_STORE_ACK;\r
+ end if; \r
+\r
+ when S_STORE_ACK =>\r
+ i2c_ack <= sda;\r
+ wait_timer_init <= i2c_speed srl 2;\r
+ STATE <= S_ACK_UNSET_SCL;\r
+ \r
+ when S_ACK_UNSET_SCL =>\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_ACK_UNSET_SCL;\r
+ else\r
+ STATE <= S_VERIFY_ACK;\r
+ end if;\r
+\r
+ when S_VERIFY_ACK =>\r
+ scl_o <= '0';\r
+ if (i2c_ack = '0') then\r
+ STATE <= S_STOP;\r
+ else\r
+ STATE <= S_ACK_ERROR;\r
+ end if;\r
+\r
+ when S_ACK_ERROR =>\r
+ scl_o <= '0';\r
+ i2c_error(1) <= '1';\r
+ STATE <= S_STOP;\r
+\r
+ -- I2C STOP Sequence \r
+ when S_STOP =>\r
+ startstop_select <= '0';\r
+ startstop_seq_start <= '1';\r
+ STATE <= S_STOP_WAIT;\r
+\r
+ when S_STOP_WAIT =>\r
+ if (startstop_done = '0') then\r
+ STATE <= S_STOP_WAIT;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ end case;\r
+\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_MASTER;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- TRBNet Slave Bus\r
+ -----------------------------------------------------------------------------\r
+\r
+ PROC_SLAVE_BUS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ reg_data <= x"affeaffe";\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ i2c_start <= '0';\r
+ else\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ slv_data_out_o <= (others => '0');\r
+ i2c_start <= '0';\r
+ \r
+ if (SLV_WRITE_IN = '1') then\r
+ i2c_chipid <= SLV_DATA_IN(6 downto 0);\r
+ i2c_rw_bit <= SLV_DATA_IN(7);\r
+ i2c_start <= '1';\r
+ elsif (SLV_READ_IN = '1') then\r
+ slv_data_out_o <= reg_data;\r
+ \r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if; \r
+ end process PROC_SLAVE_BUS;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ -- I2c Outputs\r
+ SDA_INOUT <= '0' when (sda_o = '0' or sda_startstop = '0') else 'Z';\r
+ SCL_INOUT <= '0' when (scl_o = '0' or scl_startstop = '0') else 'Z';\r
+\r
+ -- Slave Bus\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity nx_i2c_sendbyte is\r
+ generic (\r
+ i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ START_IN : in std_logic;\r
+ BYTE_IN : in std_logic_vector(7 downto 0);\r
+ SEQUENCE_DONE_OUT : out std_logic;\r
+\r
+ -- I2C connections\r
+ SDA_OUT : out std_logic;\r
+ SCL_OUT : out std_logic;\r
+ SDA_IN : in std_logic;\r
+ ACK_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_sendbyte is\r
+\r
+ -- Send Byte \r
+ signal sda_o : std_logic;\r
+ signal scl_o : std_logic;\r
+ signal i2c_start : std_logic;\r
+\r
+ signal sequence_done_o : std_logic;\r
+ signal i2c_byte : unsigned(7 downto 0);\r
+ signal bit_ctr : unsigned(3 downto 0);\r
+ signal i2c_ack_o : std_logic;\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
+\r
+ signal sequence_done_o_x : std_logic;\r
+ signal i2c_byte_x : unsigned(7 downto 0);\r
+ signal bit_ctr_x : unsigned(3 downto 0);\r
+ signal i2c_ack_o_x : std_logic;\r
+ signal wait_timer_init_x : unsigned(11 downto 0);\r
+ \r
+ type STATES is (S_IDLE,\r
+ S_INIT,\r
+ S_INIT_WAIT,\r
+\r
+ S_SEND_BYTE,\r
+ S_SET_SDA,\r
+ S_SET_SCL,\r
+ S_UNSET_SCL,\r
+ S_NEXT_BIT,\r
+\r
+ S_GET_ACK,\r
+ S_ACK_SET_SCL,\r
+ S_STORE_ACK,\r
+ S_ACK_UNSET_SCL\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+ \r
+ -- Wait Timer\r
+ signal wait_timer_done : std_logic;\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_i2c_timer_1: nx_i2c_timer\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+\r
+ PROC_SEND_BYTE_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sequence_done_o <= '0';\r
+ bit_ctr <= (others => '0');\r
+ i2c_ack_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ STATE <= S_IDLE;\r
+ else\r
+ sequence_done_o <= sequence_done_o_x;\r
+ i2c_byte <= i2c_byte_x;\r
+ bit_ctr <= bit_ctr_x;\r
+ i2c_ack_o <= i2c_ack_o_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_SEND_BYTE_TRANSFER; \r
+ \r
+ PROC_SEND_BYTE: process(STATE)\r
+ begin \r
+ sda_o <= '1';\r
+ scl_o <= '1';\r
+ sequence_done_o_x <= '0';\r
+ i2c_byte_x <= i2c_byte;\r
+ bit_ctr_x <= bit_ctr; \r
+ i2c_ack_o_x <= i2c_ack_o;\r
+ wait_timer_init_x <= (others => '0');\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (START_IN = '1') then\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ i2c_byte_x <= BYTE_IN;\r
+ NEXT_STATE <= S_INIT;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ -- INIT\r
+ when S_INIT =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_INIT_WAIT;\r
+\r
+ when S_INIT_WAIT =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_INIT_WAIT;\r
+ else\r
+ NEXT_STATE <= S_SEND_BYTE;\r
+ end if;\r
+ \r
+ -- I2C Send byte\r
+ when S_SEND_BYTE =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ bit_ctr_x <= x"7";\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_SET_SDA;\r
+\r
+ when S_SET_SDA =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_SET_SDA;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_SET_SCL;\r
+ end if;\r
+\r
+ when S_SET_SCL =>\r
+ sda_o <= i2c_byte(7);\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_SET_SCL;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_UNSET_SCL;\r
+ end if;\r
+\r
+ when S_UNSET_SCL =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_UNSET_SCL;\r
+ else\r
+ NEXT_STATE <= S_NEXT_BIT;\r
+ end if;\r
+ \r
+ when S_NEXT_BIT =>\r
+ sda_o <= i2c_byte(7);\r
+ scl_o <= '0';\r
+ if (bit_ctr > 0) then\r
+ bit_ctr_x <= bit_ctr - 1;\r
+ i2c_byte_x <= i2c_byte sll 1;\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_SET_SDA;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_GET_ACK;\r
+ end if;\r
+\r
+ -- I2C Check ACK Sequence\r
+ when S_GET_ACK =>\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_GET_ACK;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_ACK_SET_SCL;\r
+ end if;\r
+\r
+ when S_ACK_SET_SCL =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_ACK_SET_SCL;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_STORE_ACK;\r
+ end if; \r
+ \r
+ when S_STORE_ACK =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_STORE_ACK;\r
+ else\r
+ i2c_ack_o_x <= not SDA_IN;\r
+ wait_timer_init_x <= i2c_speed srl 2;\r
+ NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ end if;\r
+ \r
+ when S_ACK_UNSET_SCL =>\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_ACK_UNSET_SCL;\r
+ else\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ end case;\r
+ end process PROC_SEND_BYTE;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ SEQUENCE_DONE_OUT <= sequence_done_o;\r
+ ACK_OUT <= i2c_ack_o;\r
+ \r
+ -- I2c Outputs\r
+ SDA_OUT <= sda_o;\r
+ SCL_OUT <= scl_o;\r
+ \r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_i2c_startstop is\r
+ generic (\r
+ i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ START_IN : in std_logic; -- Start Sequence\r
+ SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop\r
+ SEQUENCE_DONE_OUT : out std_logic;\r
+ \r
+ -- I2C connections\r
+ SDA_OUT : out std_logic;\r
+ SCL_OUT : out std_logic;\r
+ NREADY_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_startstop is\r
+\r
+ -- I2C Bus \r
+ signal sda_o : std_logic;\r
+ signal scl_o : std_logic;\r
+ signal sequence_done_o : std_logic;\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
+\r
+ signal sequence_done_o_x : std_logic;\r
+ signal wait_timer_init_x : unsigned(11 downto 0);\r
+ \r
+ type STATES is (S_IDLE,\r
+ S_START,\r
+ S_WAIT_START_1,\r
+ S_WAIT_START_2,\r
+ S_WAIT_START_3,\r
+ \r
+ S_STOP,\r
+ S_WAIT_STOP_1,\r
+ S_WAIT_STOP_2,\r
+ S_WAIT_STOP_3\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+\r
+ -- I2C Timer\r
+ signal wait_timer_done : std_logic;\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_i2c_timer_1: nx_i2c_timer\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+ PROC_START_STOP_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sequence_done_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ STATE <= S_IDLE;\r
+ else\r
+ sequence_done_o <= sequence_done_o_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_START_STOP_TRANSFER;\r
+ \r
+ PROC_START_STOP: process(STATE)\r
+ begin\r
+\r
+ sda_o <= '1';\r
+ scl_o <= '1';\r
+ wait_timer_init_x <= (others => '0');\r
+ sequence_done_o_x <= '0';\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (START_IN = '1') then\r
+ if (SELECT_IN = '1') then\r
+ NEXT_STATE <= S_START;\r
+ else\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ NEXT_STATE <= S_STOP;\r
+ end if;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ -- I2C START Sequence \r
+ when S_START =>\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_START_1;\r
+\r
+ when S_WAIT_START_1 =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_START_1;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_START_2;\r
+ end if;\r
+\r
+ when S_WAIT_START_2 =>\r
+ sda_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_START_2;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_START_3;\r
+ end if;\r
+\r
+ when S_WAIT_START_3 =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_START_3;\r
+ else\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ -- I2C STOP Sequence \r
+ when S_STOP =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_STOP_1;\r
+\r
+ when S_WAIT_STOP_1 =>\r
+ sda_o <= '0';\r
+ scl_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_STOP_1;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_STOP_2;\r
+ end if;\r
+\r
+ when S_WAIT_STOP_2 =>\r
+ sda_o <= '0';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_STOP_2;\r
+ else\r
+ wait_timer_init_x <= i2c_speed srl 1;\r
+ NEXT_STATE <= S_WAIT_STOP_3;\r
+ end if;\r
+\r
+ when S_WAIT_STOP_3 =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_WAIT_STOP_3;\r
+ else\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ end case;\r
+ end process PROC_START_STOP;\r
+\r
+\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ SEQUENCE_DONE_OUT <= sequence_done_o;\r
+ SDA_OUT <= sda_o;\r
+ SCL_OUT <= scl_o;\r
+ NREADY_OUT <= '0';\r
+ \r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+entity nx_i2c_timer is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ TIMER_START_IN : in unsigned(11 downto 0);\r
+ TIMER_DONE_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_i2c_timer is\r
+\r
+ -- Timer\r
+ signal timer_ctr : unsigned(11 downto 0);\r
+ signal timer_done_o : std_logic;\r
+\r
+ signal timer_ctr_x : unsigned(11 downto 0);\r
+ signal timer_done_o_x : std_logic;\r
+\r
+ type STATES is (S_IDLE,\r
+ S_COUNT,\r
+ S_DONE\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+\r
+begin\r
+\r
+ PROC_TIMER_TRANSFER: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ timer_ctr <= (others => '0');\r
+ timer_done_o <= '0';\r
+ STATE <= S_IDLE;\r
+ else\r
+ timer_ctr <= timer_ctr_x;\r
+ timer_done_o <= timer_done_o_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_TIMER_TRANSFER;\r
+ \r
+ PROC_TIMER: process(STATE)\r
+ begin \r
+\r
+ timer_done_o_x <= '0';\r
+\r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (TIMER_START_IN = 0) then\r
+ NEXT_STATE <= S_IDLE;\r
+ else\r
+ timer_ctr_x <= TIMER_START_IN;\r
+ NEXT_STATE <= S_COUNT;\r
+ end if;\r
+ \r
+ when S_COUNT =>\r
+ if (timer_ctr > 0) then\r
+ timer_ctr_x <= timer_ctr - 1;\r
+ NEXT_STATE <= S_COUNT;\r
+ else\r
+ NEXT_STATE <= S_DONE;\r
+ end if;\r
+ \r
+ when S_DONE =>\r
+ timer_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+ \r
+ end case;\r
+ end process PROC_TIMER;\r
+ \r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ TIMER_DONE_OUT <= timer_done_o;\r
+\r
+end Behavioral;\r
use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
\r
library work;\r
-use work.adcmv3_components.all;\r
use work.nxyter_components.all;\r
\r
entity nx_timestamp_fifo_read is\r
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);\r
NX_FRAME_CLOCK_OUT : out std_logic;\r
NX_FRAME_SYNC_OUT : out std_logic;\r
+ NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);\r
\r
-- Slave bus \r
SLV_READ_IN : in std_logic;\r
SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
SLV_ACK_OUT : out std_logic;\r
SLV_NO_MORE_DATA_OUT : out std_logic;\r
- SLV_UNKNOWN_ADDR_OUT : out std_logic\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+\r
+ DEBUG_OUT : out std_logic_vector(7 downto 0)\r
);\r
end entity;\r
\r
\r
\r
-- FIFO Input Handler\r
+ signal nx_timestamp_n : std_logic_vector(7 downto 0);\r
signal fifo_skip_write_x : std_logic;\r
signal fifo_skip_write_l : std_logic;\r
signal fifo_skip_write : std_logic;\r
signal fifo_skip_write_s : std_logic;\r
\r
-- SYNC NX Frame Process\r
- signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
+ \r
+ -- RS Sync FlipFlop\r
signal nx_frame_synced_o : std_logic;\r
+ signal rs_sync_set : std_logic;\r
+ signal rs_sync_reset : std_logic;\r
+ \r
+ -- Sync Process\r
+ signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
signal frame_sync_wait_ctr : unsigned (7 downto 0);\r
\r
-- Slave Bus\r
\r
begin\r
\r
+ DEBUG_OUT(0) <= fifo_write_enable_o;\r
+ DEBUG_OUT(1) <= fifo_full;\r
+ DEBUG_OUT(2) <= fifo_read_enable_o;\r
+ DEBUG_OUT(3) <= fifo_empty;\r
+\r
+ DEBUG_OUT(4) <= nx_frame_synced_o;\r
+ DEBUG_OUT(5) <= fifo_skip_write_o;\r
+ DEBUG_OUT(6) <= nx_frame_clock_o;\r
+ DEBUG_OUT(7) <= CLK_IN;\r
+ \r
-----------------------------------------------------------------------------\r
-- Dual Clock FIFO 8bit to 32bit\r
-----------------------------------------------------------------------------\r
\r
+ -- First Decode\r
+ -- Gray_Decoder_1: Gray_Decoder\r
+ -- generic map (\r
+ -- WIDTH => 8)\r
+ -- port map (\r
+ -- CLK_IN => NX_TIMESTAMP_CLK_IN,\r
+ -- RESET_IN => RESET_IN,\r
+ -- GRAY_IN => NX_TIMESTAMP_IN,\r
+ -- BINARY_OUT => nx_timestamp_n\r
+ -- );\r
+ nx_timestamp_n <= NX_TIMESTAMP_IN;\r
+ \r
+ \r
+ -- Second send data to FIFO\r
fifo_dc_8to32_1: fifo_dc_8to32\r
port map (\r
- Data => NX_TIMESTAMP_IN,\r
+ Data => nx_timestamp_n,\r
WrClock => NX_TIMESTAMP_CLK_IN,\r
RdClock => CLK_IN,\r
WrEn => fifo_write_enable_o,\r
Full => fifo_full_i\r
);\r
\r
+ \r
-----------------------------------------------------------------------------\r
-- FIFO Input Handler\r
-----------------------------------------------------------------------------\r
-\r
+ \r
-- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal\r
-- fifo_skip_write\r
PROC_FIFO_IN_HANDLER_SYNC: process(NX_TIMESTAMP_CLK_IN)\r
end process PROC_FIFO_IN_HANDLER_SYNC;\r
\r
-- Signal fifo_skip_write might 2 clocks long --> I need 1\r
- level_to_pulse_1: level_to_pulse\r
- port map (\r
- CLK_IN => NX_TIMESTAMP_CLK_IN,\r
- RESET_IN => RESET_IN,\r
- LEVEL_IN => fifo_skip_write_l,\r
- PULSE_OUT => fifo_skip_write\r
- );\r
+ level_to_pulse_1: level_to_pulse\r
+ port map (\r
+ CLK_IN => NX_TIMESTAMP_CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ LEVEL_IN => fifo_skip_write_l,\r
+ PULSE_OUT => fifo_skip_write\r
+ );\r
\r
-- Write only in case FIFO is not full, skip one write cycle in case\r
-- fifo_skip_write is true (needed by the synchronization process\r
\r
NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
\r
-\r
-----------------------------------------------------------------------------\r
-- FIFO Output Handler and Sync FIFO\r
-----------------------------------------------------------------------------\r
end if;\r
end if;\r
end process PROC_FIFO_READ;\r
+ \r
\r
+ -- RS FlipFlop to hold Sync Status\r
+ PROC_RS_FRAME_SYNCED: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if (RESET_IN = '1' or rs_sync_reset = '1') then\r
+ nx_frame_synced_o <= '0';\r
+ elsif (rs_sync_set = '1') then\r
+ nx_frame_synced_o <= '1';\r
+ end if;\r
+ end if;\r
+ end process PROC_RS_FRAME_SYNCED;\r
\r
- -- Sync to NX NO_DATA FRAME\r
+ -- Sync to NX NO_DATA FRAME \r
PROC_SYNC_TO_NO_DATA: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- nx_frame_synced_o <= '0';\r
+ rs_sync_set <= '0';\r
+ rs_sync_reset <= '1';\r
nx_frame_resync_ctr <= (others => '0');\r
frame_sync_wait_ctr <= (others => '0');\r
- fifo_skip_write_s <= '0';\r
- STATE_SYNC <= SYNC_CHECK;\r
+ fifo_skip_write_s <= '0';\r
+ STATE_SYNC <= SYNC_CHECK;\r
else\r
+ rs_sync_set <= '0';\r
+ rs_sync_reset <= '0';\r
fifo_skip_write_s <= '0';\r
-\r
+ \r
case STATE_SYNC is\r
\r
when SYNC_CHECK =>\r
case fifo_out is\r
when x"7f7f7f06" =>\r
- nx_frame_synced_o <= '1';\r
- STATE_SYNC <= SYNC_CHECK;\r
+ rs_sync_set <= '1';\r
+ STATE_SYNC <= SYNC_CHECK;\r
\r
when x"067f7f7f" =>\r
- nx_frame_synced_o <= '0';\r
STATE_SYNC <= SYNC_RESYNC;\r
\r
when x"7f067f7f" =>\r
- nx_frame_synced_o <= '0';\r
STATE_SYNC <= SYNC_RESYNC;\r
\r
when x"7f7f067f" =>\r
- nx_frame_synced_o <= '0';\r
STATE_SYNC <= SYNC_RESYNC;\r
\r
when others =>\r
- nx_frame_synced_o <= nx_frame_synced_o;\r
STATE_SYNC <= SYNC_CHECK;\r
- \r
+ \r
end case;\r
\r
when SYNC_RESYNC =>\r
+ rs_sync_reset <= '1';\r
fifo_skip_write_s <= '1';\r
nx_frame_resync_ctr <= nx_frame_resync_ctr + 1;\r
frame_sync_wait_ctr <= x"ff";\r
end process PROC_SYNC_TO_NO_DATA;\r
\r
NX_FRAME_SYNC_OUT <= nx_frame_synced_o;\r
- \r
+ NX_TIMESTAMP_OUT <= register_fifo_data;\r
+\r
-------------------------------------------------------------------------------\r
-- TRBNet Slave Bus\r
-------------------------------------------------------------------------------\r
end if; \r
end process PROC_NX_TIMESTAMP;\r
\r
- \r
-\r
--- Gray_Encoder_1: Gray_Encoder\r
--- generic map (\r
--- WIDTH => 8\r
--- )\r
--- port map (\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- BINARY_IN => timestamp_n,\r
--- GRAY_OUT => timestamp_g \r
--- );\r
+-- Gray_Encoder_1: Gray_Encoder\r
+-- generic map (\r
+-- WIDTH => 8\r
+-- )\r
+-- port map (\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- BINARY_IN => timestamp_n,\r
+-- GRAY_OUT => timestamp_g \r
+-- );\r
-- \r
-\r
+ timestamp_g <= timestamp_n;\r
+ \r
+ \r
-- Output Signals\r
- TIMESTAMP_OUT <= timestamp_n;\r
+ TIMESTAMP_OUT <= timestamp_g;\r
CLK128_OUT <= CLK_IN;\r
\r
end Behavioral;\r
-----------------------------------------------------------------------------
--
---One nXyter FEB
+-- One nXyter FEB
--
-----------------------------------------------------------------------------
library ieee;
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.adcmv3_components.all;
use work.nxyter_components.all;
+-- ADCM use work.adcmv3_components.all;
entity nXyter_FEE_board is
-- I2C Ports
I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
- I2C_SCL_OUT : out std_logic; -- nXyter I2C Clock line
+ I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C StateMachine
I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers to default
-- ADC SPI
SPI_SCLK_OUT : out std_logic;
- SPI_SDIO_INOUT : in std_logic;
+ SPI_SDIO_INOUT : inout std_logic;
SPI_CSB_OUT : out std_logic;
-- nXyter Timestamp Ports
REGIO_DATAREADY_OUT : out std_logic;
REGIO_WRITE_ACK_OUT : out std_logic;
REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+
+ -- Debug Signals
+ CLK_128_IN : in std_logic;
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
);
end nXyter_FEE_board;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
+ -- Clock 256
+ signal clk_256_o : std_logic;
-- Bus Handler
signal slv_read : std_logic_vector(8-1 downto 0);
signal slv_write : std_logic_vector(8-1 downto 0);
- signal slv_busy : std_logic_vector(8-1 downto 0);
+ signal slv_no_more_data : std_logic_vector(8-1 downto 0);
signal slv_ack : std_logic_vector(8-1 downto 0);
signal slv_addr : std_logic_vector(8*16-1 downto 0);
signal slv_data_rd : std_logic_vector(8*32-1 downto 0);
signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
-- I2C Master
- signal i2c_sda_o : std_logic; -- I2C SDA
- signal i2c_sda_i : std_logic;
- signal i2c_scl_o : std_logic; -- I2C SCL
- signal i2c_scl_i : std_logic;
-
+-- ADCM signal i2c_sda_o : std_logic;
+-- ADCM signal i2c_sda_i : std_logic;
+-- ADCM signal i2c_scl_o : std_logic;
+-- ADCM signal i2c_scl_i : std_logic;
+ signal i2c_sm_reset_o : std_logic;
+ signal i2c_reg_reset_o : std_logic;
+
-- SPI Interface ADC
signal spi_sdi : std_logic;
signal spi_sdo : std_logic;
+ -- FIFO Read
+ signal nx_frame_clock_o : std_logic;
+ signal nx_frame_sync_o : std_logic;
+
+
+ -- Timestamp Handlers
+ signal nx_timestamp_o : std_logic_vector(31 downto 0);
+
+
begin
+-------------------------------------------------------------------------------
+-- DEBUG
+-------------------------------------------------------------------------------
+-- DEBUG_LINE_OUT(0) <= CLK_IN;
+-- DEBUG_LINE_OUT(1) <= clk_256_o;
+-- DEBUG_LINE_OUT(2) <= NX_CLK128_IN;
+-- DEBUG_LINE_OUT(3) <= nx_frame_clock_o;
+-- DEBUG_LINE_OUT(4) <= nx_frame_sync_o;
+-- DEBUG_LINE_OUT(7 downto 5) <= (others => '0');
+-- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
+-- DEBUG_LINE_OUT(8) <= i2c_sda_o;
+-- DEBUG_LINE_OUT(9) <= i2c_sda_i;
+-- DEBUG_LINE_OUT(10) <= i2c_scl_o;
+-- DEBUG_LINE_OUT(11) <= i2c_scl_i;
+-- DEBUG_LINE_OUT(15 downto 12) <= (others => '0');
+
+ DEBUG_LINE_OUT(0) <= CLK_IN;
+ DEBUG_LINE_OUT(1) <= I2C_SDA_INOUT;
+ DEBUG_LINE_OUT(2) <= I2C_SCL_INOUT;
+
+ DEBUG_LINE_OUT(7 downto 3) <= (others => '0');
+
-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------
+
+
+ -- pll_nx_clk256_1: pll_nx_clk256
+ -- port map (
+ -- CLK => CLK_IN,
+ -- CLKOP => clk_256_o,
+ -- LOCK => open
+ -- );
+
+ -- pll_25_1: pll_25
+ -- port map (
+ -- CLK => CLK_IN,
+ -- CLKOP => clk_256_o,
+ -- LOCK => open
+ -- );
+ clk_256_o <= CLK_128_IN;
+
+ NX_RESET_OUT <= '0';
+ NX_CLK256A_OUT <= clk_256_o;
+ NX_TESTPULSE_OUT <= '0';
+
-- TRBNet Bus Handler
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
- 1 => x"0040", -- I2C master
- 2 => x"0100", -- Timestamp Fifo
- -- 3 => x"d100", -- SPI data memory
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
+ 1 => x"0040", -- I2C master
+ 2 => x"0100", -- Timestamp Fifo
+ 3 => x"0200", -- Data Buffer
+ -- 3 => x"d100", -- SPI data memory
others => x"0000"),
- PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
- 1 => 0, -- I2C master
- 2 => 1, -- Timestamp Fifo
- -- 3 => 6, -- SPI data memory
+ PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
+ 1 => 0, -- I2C master
+ 2 => 1, -- Timestamp Fifo
+ 3 => 1, -- Data Buffer
+ -- 3 => 6, -- SPI data memory
others => 0)
)
port map(
BUS_TIMEOUT_OUT(0) => open,
BUS_DATAREADY_IN(0) => slv_ack(0),
BUS_WRITE_ACK_IN(0) => slv_ack(0),
- BUS_NO_MORE_DATA_IN(0) => slv_busy(0),
+ BUS_NO_MORE_DATA_IN(0) => slv_no_more_data(0),
BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0),
-- I2C master
BUS_TIMEOUT_OUT(1) => open,
BUS_DATAREADY_IN(1) => slv_ack(1),
BUS_WRITE_ACK_IN(1) => slv_ack(1),
- BUS_NO_MORE_DATA_IN(1) => slv_busy(1),
- BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(1) => slv_no_more_data(1),
+ BUS_UNKNOWN_ADDR_IN(1) => slv_unknown_addr(1),
-- Timestamp Fifo
BUS_READ_ENABLE_OUT(2) => slv_read(2),
BUS_TIMEOUT_OUT(2) => open,
BUS_DATAREADY_IN(2) => slv_ack(2),
BUS_WRITE_ACK_IN(2) => slv_ack(2),
- BUS_NO_MORE_DATA_IN(2) => slv_busy(2),
+ BUS_NO_MORE_DATA_IN(2) => slv_no_more_data(2),
BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2),
+ -- DataBuffer
+ BUS_READ_ENABLE_OUT(3) => slv_read(3),
+ BUS_WRITE_ENABLE_OUT(3) => slv_write(3),
+ BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),
+ BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),
+-- BUS_ADDR_OUT(3*16+0 downto 2*16) => slv_addr(3*16+0 downto 0*16),
+ BUS_ADDR_OUT(3*16+0) => slv_addr(3*16+0),
+ BUS_ADDR_OUT(3*16+15 downto 3*16+1) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATAREADY_IN(3) => slv_ack(3),
+ BUS_WRITE_ACK_IN(3) => slv_ack(3),
+ BUS_NO_MORE_DATA_IN(3) => slv_no_more_data(3),
+ BUS_UNKNOWN_ADDR_IN(3) => slv_unknown_addr(3),
+
---- SPI control registers
--BUS_READ_ENABLE_OUT(4) => slv_read(4),
--BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
--BUS_TIMEOUT_OUT(4) => open,
--BUS_DATAREADY_IN(4) => slv_ack(4),
--BUS_WRITE_ACK_IN(4) => slv_ack(4),
- --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),
+ --BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4),
--BUS_UNKNOWN_ADDR_IN(4) => '0',
---- SPI data memory
--BUS_TIMEOUT_OUT(5) => open,
--BUS_DATAREADY_IN(5) => slv_ack(5),
--BUS_WRITE_ACK_IN(5) => slv_ack(5),
- --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),
+ --BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5),
--BUS_UNKNOWN_ADDR_IN(5) => '0',
---- debug
- --STAT_DEBUG => stat
STAT_DEBUG => open
);
SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16),
SLV_ACK_OUT => slv_ack(0),
- SLV_NO_MORE_DATA_OUT => slv_busy(0),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0)
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(0),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0),
+
+ DEBUG_OUT => open
);
-------------------------------------------------------------------------------
-- I2C master block for accessing the nXyter
-------------------------------------------------------------------------------
- THE_I2C_MASTER: i2c_master
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- -- Slave bus
- SLV_READ_IN => slv_read(1),
- SLV_WRITE_IN => slv_write(1),
- SLV_BUSY_OUT => slv_busy(1),
- SLV_ACK_OUT => slv_ack(1),
- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
-
- -- I2C connections
- SDA_IN => open,
- SDA_OUT => open,
- SCL_IN => open,
- SCL_OUT => open,
-
- -- Status lines
- STAT => open
+ nx_i2c_master_1: nx_i2c_master
+ generic map (
+ i2c_speed => x"3e8"
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SDA_INOUT => I2C_SDA_INOUT,
+ SCL_INOUT => I2C_SCL_INOUT,
+ SLV_READ_IN => slv_read(1),
+ SLV_WRITE_IN => slv_write(1),
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ SLV_ACK_OUT => slv_ack(1),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8)
);
+
+-- ADCM i2c_master_1: i2c_master
+-- ADCM port map (
+-- ADCM CLK_IN => CLK_IN,
+-- ADCM RESET_IN => RESET_IN,
+-- ADCM SLV_READ_IN => slv_read(1),
+-- ADCM SLV_WRITE_IN => slv_write(1),
+-- ADCM SLV_BUSY_OUT => open,
+-- ADCM SLV_ACK_OUT => slv_ack(1),
+-- ADCM SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+-- ADCM SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+-- ADCM SDA_IN => i2c_sda_i,
+-- ADCM SDA_OUT => i2c_sda_o,
+-- ADCM SCL_IN => i2c_scl_i,
+-- ADCM SCL_OUT => i2c_scl_o,
+-- ADCM STAT => open
+-- ADCM );
+-- ADCM
+-- ADCM -- I2c Outputs
+-- ADCM I2C_SDA_INOUT <= '0' when (i2c_sda_o = '0') else 'Z';
+-- ADCM i2c_sda_i <= I2C_SDA_INOUT;
+-- ADCM I2C_SCL_INOUT <= '0' when (i2c_scl_o = '0') else 'Z';
+-- ADCM i2c_scl_i <= I2C_SCL_INOUT;
+
+ i2c_sm_reset_o <= not '0';
+ i2c_reg_reset_o <= not '0';
+
-------------------------------------------------------------------------------
-- nXyter TimeStamp Read
-------------------------------------------------------------------------------
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+
NX_TIMESTAMP_CLK_IN => NX_CLK128_IN,
NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
- NX_FRAME_CLOCK_OUT => open,
-
+ NX_FRAME_CLOCK_OUT => nx_frame_clock_o,
+ NX_FRAME_SYNC_OUT => nx_frame_sync_o,
+ NX_TIMESTAMP_OUT => nx_timestamp_o,
+
SLV_READ_IN => slv_read(2),
SLV_WRITE_IN => slv_write(2),
SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
SLV_ACK_OUT => slv_ack(2),
- SLV_NO_MORE_DATA_OUT => slv_busy(2),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2)
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
+
+-- DEBUG_OUT => DEBUG_LINE_OUT(7 downto 0)
+ DEBUG_OUT => open
);
- -----------------------------------------------------------------------------
- -- nXyter Signals
- -----------------------------------------------------------------------------
-
- -----------------------------------------------------------------------------
- -- I2C Signals
- -----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Data Buffer FIFO
+-------------------------------------------------------------------------------
+ nx_data_buffer_1: nx_data_buffer
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
- -- SDA line output
- I2C_SDA_INOUT <= '0' when (i2c_sda_o = '0') else 'Z';
+ FIFO_DATA_IN => nx_timestamp_o,
+ FIFO_WRITE_ENABLE_IN => '1',
+ FIFO_READ_ENABLE_IN => '1',
+
+ SLV_READ_IN => slv_read(3),
+ SLV_WRITE_IN => slv_write(3),
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
+ SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
+ SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
+ SLV_ACK_OUT => slv_ack(3),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3)
+ );
- -- SDA line input (wired OR negative logic)
- -- i2c_sda_i <= i2c_sda;
- -- SCL line output
- I2C_SCL_OUT <= '0' when (i2c_scl_o = '0') else 'Z';
+-------------------------------------------------------------------------------
+-- nXyter Signals
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- I2C Signals
+-------------------------------------------------------------------------------
- -- SCL line input (wired OR negative logic)
- -- i2c_scl_i <= i2c_scl;
+ I2C_SM_RESET_OUT <= i2c_sm_reset_o;
+ I2C_REG_RESET_OUT <= i2c_reg_reset_o;
-------------------------------------------------------------------------------
-- END
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
package nxyter_components is
-------------------------------------------------------------------------------
RESET_IN : in std_logic;
I2C_SDA_INOUT : inout std_logic;
- I2C_SCL_OUT : out std_logic;
+ I2C_SCL_INOUT : inout std_logic;
I2C_SM_RESET_OUT : out std_logic;
I2C_REG_RESET_OUT : out std_logic;
SPI_SCLK_OUT : out std_logic;
- SPI_SDIO_INOUT : in std_logic;
+ SPI_SDIO_INOUT : inout std_logic;
SPI_CSB_OUT : out std_logic;
NX_CLK128_IN : in std_logic;
REGIO_DATAREADY_OUT : out std_logic;
REGIO_WRITE_ACK_OUT : out std_logic;
REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+
+ CLK_128_IN : in std_logic;
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
);
end component;
+-------------------------------------------------------------------------------
+-- nXyter I2C Interface
+-------------------------------------------------------------------------------
+
+
+component nx_i2c_master
+ generic (
+ i2c_speed : unsigned(11 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SDA_INOUT : inout std_logic;
+ SCL_INOUT : inout std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+component nx_i2c_timer
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMER_START_IN : in unsigned(11 downto 0);
+ TIMER_DONE_OUT : out std_logic
+ );
+end component;
+
+component nx_i2c_startstop
+ generic (
+ i2c_speed : unsigned(11 downto 0));
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ START_IN : in std_logic; -- Start Sequence
+ SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop
+ SEQUENCE_DONE_OUT : out std_logic;
+ SDA_OUT : out std_logic;
+ SCL_OUT : out std_logic;
+ NREADY_OUT : out std_logic
+ );
+end component;
+
+component nx_i2c_sendbyte
+ generic (
+ i2c_speed : unsigned(11 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ START_IN : in std_logic;
+ BYTE_IN : in std_logic_vector(7 downto 0);
+ SEQUENCE_DONE_OUT : out std_logic;
+ SDA_OUT : out std_logic;
+ SCL_OUT : out std_logic;
+ SDA_IN : in std_logic;
+ ACK_OUT : out std_logic
+ );
+end component;
+
+-------------------------------------------------------------------------------
+-- TRBNet Registers
+-------------------------------------------------------------------------------
+
+
component nxyter_registers
port (
CLK_IN : in std_logic;
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- NX_TIMESTAMP_CLK_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX_FRAME_CLOCK_OUT : out std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
+
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_FRAME_CLOCK_OUT : out std_logic;
+ NX_FRAME_SYNC_OUT : out std_logic;
+ NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
+
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(7 downto 0)
);
end component;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0);
- BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0));
+ BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
+ );
end component;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0);
- GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0));
+ GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
+ );
+end component;
+
+component fifo_32_data
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+ );
+end component;
+
+component nx_data_buffer
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ FIFO_DATA_IN : std_logic_vector(31 downto 0);
+ FIFO_WRITE_ENABLE_IN : std_logic;
+ FIFO_READ_ENABLE_IN : std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+end component;
+
+
+component pll_nx_clk256
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
+end component;
+
+component pll_25
+ port (
+ CLK : in std_logic;
+ CLKOP : out std_logic;
+ LOCK : out std_logic);
end component;
-------------------------------------------------------------------------------
SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
SLV_ACK_OUT : out std_logic;\r
SLV_NO_MORE_DATA_OUT : out std_logic;\r
- SLV_UNKNOWN_ADDR_OUT : out std_logic\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
);\r
end entity;\r
\r
\r
begin\r
\r
+ DEBUG_OUT <= reg_data(0)(15 downto 0);\r
+ \r
PROC_NX_REGISTERS: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.adcmv3_components.all;
-use work.nxyter_components.all;
-
-entity slave_bus is
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- RegIO signals
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
- REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
- REGIO_READ_ENABLE_IN : in std_logic; -- read pulse
- REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse
- REGIO_TIMEOUT_IN : in std_logic; -- access timed out
- REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested
- REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted
- REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
- REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
-
- -- I2C connections
- SDA_IN : in std_logic;
- SDA_OUT : out std_logic;
- SCL_IN : in std_logic;
- SCL_OUT : out std_logic;
-
- -- SPI connections
- SPI_CS_OUT : out std_logic;
- SPI_SCK_OUT : out std_logic;
- SPI_SDI_IN : in std_logic;
- SPI_SDO_OUT : out std_logic;
-
- -- Timestamp Read
- NX_CLK128_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector(7 downto 0)
- );
-end entity;
-
-architecture Behavioral of slave_bus is
-
--- Signals
- signal slv_read : std_logic_vector(8-1 downto 0);
- signal slv_write : std_logic_vector(8-1 downto 0);
- signal slv_busy : std_logic_vector(8-1 downto 0);
- signal slv_ack : std_logic_vector(8-1 downto 0);
- signal slv_addr : std_logic_vector(8*16-1 downto 0);
- signal slv_data_rd : std_logic_vector(8*32-1 downto 0);
- signal slv_data_wr : std_logic_vector(8*32-1 downto 0);
- signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
-
--- SPI controller BRAM lines
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
- signal spi_cs : std_logic;
- signal spi_sck : std_logic;
- signal spi_sdi : std_logic;
- signal spi_sdo : std_logic;
- signal spi_debug : std_logic_vector(31 downto 0);
-
- signal ctrl_lvl : std_logic_vector(31 downto 0);
- signal ctrl_trg : std_logic_vector(31 downto 0);
- signal ctrl_pll : std_logic_vector(15 downto 0);
-
- signal debug : std_logic_vector(63 downto 0);
-
- -- Register Stuff
- -- type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);
-
- signal reg_data : std_logic_vector(31 downto 0);
-
-
-begin
-
--- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus
- THE_BUS_HANDLER: trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
- 1 => x"0040", -- I2C master
- 2 => x"0100", -- Timestamp Fifo
- -- 3 => x"d100", -- SPI data memory
- others => x"0000"),
- PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
- 1 => 0, -- I2C master
- 2 => 2, -- Timestamp Fifo
- -- 3 => 6, -- SPI data memory
- others => 0)
- )
- port map(
- CLK => CLK_IN,
- RESET => RESET_IN,
- DAT_ADDR_IN => REGIO_ADDR_IN,
- DAT_DATA_IN => REGIO_DATA_IN,
- DAT_DATA_OUT => REGIO_DATA_OUT,
- DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,
- DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,
- DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,
- DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,
- DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,
- DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
- DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
-
- -- Control Registers
- BUS_READ_ENABLE_OUT(0) => slv_read(0),
- BUS_WRITE_ENABLE_OUT(0) => slv_write(0),
- BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),
- BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),
- BUS_ADDR_OUT(0*16+2 downto 0*16) => slv_addr(0*16+2 downto 0*16),
- BUS_ADDR_OUT(0*16+15 downto 0*16+3) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATAREADY_IN(0) => slv_ack(0),
- BUS_WRITE_ACK_IN(0) => slv_ack(0),
- BUS_NO_MORE_DATA_IN(0) => slv_busy(0),
- BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0),
-
- -- I2C master
- BUS_READ_ENABLE_OUT(1) => slv_read(1),
- BUS_WRITE_ENABLE_OUT(1) => slv_write(1),
- BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),
- BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),
- BUS_ADDR_OUT(1*16+15 downto 1*16) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATAREADY_IN(1) => slv_ack(1),
- BUS_WRITE_ACK_IN(1) => slv_ack(1),
- BUS_NO_MORE_DATA_IN(1) => slv_busy(1),
- BUS_UNKNOWN_ADDR_IN(1) => '0',
-
- -- Timestamp Fifo
- BUS_READ_ENABLE_OUT(2) => slv_read(2),
- BUS_WRITE_ENABLE_OUT(2) => slv_write(2),
- BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),
- BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),
- BUS_ADDR_OUT(2*16+1 downto 2*16) => slv_addr(2*16+1 downto 2*16),
- BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATAREADY_IN(2) => slv_ack(2),
- BUS_WRITE_ACK_IN(2) => slv_ack(2),
- BUS_NO_MORE_DATA_IN(2) => slv_busy(2),
- BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2),
-
- ---- SPI control registers
- --BUS_READ_ENABLE_OUT(4) => slv_read(4),
- --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
- --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),
- --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),
- --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),
- --BUS_TIMEOUT_OUT(4) => open,
- --BUS_DATAREADY_IN(4) => slv_ack(4),
- --BUS_WRITE_ACK_IN(4) => slv_ack(4),
- --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),
- --BUS_UNKNOWN_ADDR_IN(4) => '0',
- ---- SPI data memory
- --BUS_READ_ENABLE_OUT(5) => slv_read(5),
- --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
- --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
- --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
- --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),
- --BUS_TIMEOUT_OUT(5) => open,
- --BUS_DATAREADY_IN(5) => slv_ack(5),
- --BUS_WRITE_ACK_IN(5) => slv_ack(5),
- --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),
- --BUS_UNKNOWN_ADDR_IN(5) => '0',
-
- ---- debug
- --STAT_DEBUG => stat
- STAT_DEBUG => open
- );
-
--------------------------------------------------------------------------------
--- Registers
--------------------------------------------------------------------------------
- nxyter_registers_1: nxyter_registers
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
-
- SLV_READ_IN => slv_read(0),
- SLV_WRITE_IN => slv_write(0),
- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
- SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16),
- SLV_ACK_OUT => slv_ack(0),
- SLV_NO_MORE_DATA_OUT => slv_busy(0),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0)
- );
-
--------------------------------------------------------------------------------
--- I2C master block for accessing APVs
--------------------------------------------------------------------------------
- THE_I2C_MASTER: i2c_master
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- -- Slave bus
- SLV_READ_IN => slv_read(1),
- SLV_WRITE_IN => slv_write(1),
- SLV_BUSY_OUT => slv_busy(1),
- SLV_ACK_OUT => slv_ack(1),
- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
- -- I2C connections
- SDA_IN => SDA_IN,
- SDA_OUT => SDA_OUT,
- SCL_IN => SCL_IN,
- SCL_OUT => SCL_OUT,
- -- Status lines
- STAT => open
- );
--------------------------------------------------------------------------------
--- TimeStamp Read
--------------------------------------------------------------------------------
- nx_timestamp_read_1: nx_timestamp_read
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- NX_CLK128_IN => NX_CLK128_IN,
- NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
-
- SLV_READ_IN => slv_read(2),
- SLV_WRITE_IN => slv_write(2),
- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
- SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
- SLV_ACK_OUT => slv_ack(2),
- SLV_NO_MORE_DATA_OUT => slv_busy(2),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2)
- );
-
------------------------------------------------------------------------------
--- Test Register
------------------------------------------------------------------------------
--- slv_register_1: slv_register
--- generic map (
--- RESET_VALUE => x"dead_beef"
--- )
--- port map (
--- CLK_IN => CLK_IN,
--- RESET_IN => RESET_IN,
--- BUSY_IN => '0',
---
--- SLV_READ_IN => slv_read(0),
--- SLV_WRITE_IN => slv_write(0),
--- SLV_BUSY_OUT => slv_busy(0),
--- SLV_ACK_OUT => slv_ack(0),
--- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
--- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
---
--- REG_DATA_IN => reg_data_in,
--- REG_DATA_OUT => reg_data_out,
--- STAT => open
--- );
--- slv_busy(0) <= '0';
-
--- ------------------------------------------------------------------------------------
--- -- SPI master
--- ------------------------------------------------------------------------------------
--- THE_SPI_MASTER: spi_master
--- port map(
--- CLK_IN => CLK_IN,
--- RESET_IN => RESET_IN,
--- -- Slave bus
--- BUS_READ_IN => slv_read(4),
--- BUS_WRITE_IN => slv_write(4),
--- BUS_BUSY_OUT => slv_busy(4),
--- BUS_ACK_OUT => slv_ack(4),
--- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),
--- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
--- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
--- -- SPI connections
--- SPI_CS_OUT => spi_cs,
--- SPI_SDI_IN => spi_sdi,
--- SPI_SDO_OUT => spi_sdo,
--- SPI_SCK_OUT => spi_sck,
--- -- BRAM for read/write data
--- BRAM_A_OUT => spi_bram_addr,
--- BRAM_WR_D_IN => spi_bram_wr_d,
--- BRAM_RD_D_OUT => spi_bram_rd_d,
--- BRAM_WE_OUT => spi_bram_we,
--- -- Status lines
--- STAT => spi_debug --open
--- );
---
--- ------------------------------------------------------------------------------------
--- -- data memory for SPI accesses
--- ------------------------------------------------------------------------------------
--- THE_SPI_MEMORY: spi_databus_memory
--- port map(
--- CLK_IN => CLK_IN,
--- RESET_IN => RESET_IN,
--- -- Slave bus
--- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),
--- BUS_READ_IN => slv_read(5),
--- BUS_WRITE_IN => slv_write(5),
--- BUS_ACK_OUT => slv_ack(5),
--- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
--- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
--- -- state machine connections
--- BRAM_ADDR_IN => spi_bram_addr,
--- BRAM_WR_D_OUT => spi_bram_wr_d,
--- BRAM_RD_D_IN => spi_bram_rd_d,
--- BRAM_WE_IN => spi_bram_we,
--- -- Status lines
--- STAT => open
--- );
--- slv_busy(5) <= '0';
---
-
--- unusable pins
- debug(63 downto 43) <= (others => '0');
--- connected pins
- debug(42 downto 0) <= (others => '0');
-
--- input signals
- spi_sdi <= SPI_SDI_IN;
-
--- Output signals
- SPI_CS_OUT <= spi_cs;
- SPI_SCK_OUT <= spi_sck;
- SPI_SDO_OUT <= spi_sdo;
-
-end Behavioral;
+++ /dev/null
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.adcmv3_components.all;\r
-\r
-entity slv_ped_thr_mem is\r
- port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
-\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(10 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
-\r
- -- I/O to the backend\r
- MEM_CLK_IN : in std_logic;\r
- MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
- MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
-\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of slv_ped_thr_mem is\r
-\r
--- Signals\r
- type STATES is (SLEEP,\r
- RD_RDY,\r
- RD_DEL0,\r
- RD_DEL1,\r
- WR_DEL0,\r
- WR_DEL1,\r
- WR_RDY,\r
- RD_ACK,\r
- WR_ACK,\r
- DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
--- statemachine signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal block_addr : std_logic_vector(3 downto 0);\r
-\r
- signal ped_data : std_logic_vector(17 downto 0);\r
- signal mem_data : std_logic_vector(17 downto 0);\r
-\r
- signal mem_wr_x : std_logic;\r
- signal mem_wr : std_logic;\r
- signal mem_sel : std_logic;\r
-\r
- signal rdback_data : std_logic_vector(17 downto 0);\r
-\r
-begin\r
-\r
----------------------------------------------------------\r
--- Mapping of backplanes --\r
----------------------------------------------------------\r
--- THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
--- port map (\r
--- ADDRESS(6 downto 4) => backplane_in,\r
--- ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
--- Q => block_addr\r
--- );\r
---\r
- THE_MEM_SEL_PROC: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- mem_sel <= '1';\r
- rdback_data <= mem_data;\r
- end if;\r
- end process THE_MEM_SEL_PROC;\r
-\r
----------------------------------------------------------\r
--- Statemachine --\r
----------------------------------------------------------\r
--- State memory process\r
- STATE_MEM: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- slv_ack <= slv_ack_x;\r
- store_wr <= store_wr_x;\r
- store_rd <= store_rd_x;\r
- end if;\r
- end if;\r
- end process STATE_MEM;\r
-\r
--- Transition matrix\r
- TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in )\r
- begin\r
- NEXT_STATE <= SLEEP;\r
- slv_ack_x <= '0';\r
- store_wr_x <= '0';\r
- store_rd_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP => if ( slv_read_in = '1' ) then\r
- NEXT_STATE <= RD_DEL0;\r
- store_rd_x <= '1';\r
- elsif( slv_write_in = '1' ) then\r
- NEXT_STATE <= WR_DEL0;\r
- store_wr_x <= '1';\r
- else\r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RD_DEL0 => NEXT_STATE <= RD_DEL1;\r
- when RD_DEL1 => NEXT_STATE <= RD_RDY;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- slv_ack_x <= '1';\r
- else\r
- NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when WR_DEL0 => NEXT_STATE <= WR_DEL1;\r
- when WR_DEL1 => NEXT_STATE <= WR_RDY;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- slv_ack_x <= '1';\r
- else\r
- NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
-\r
- when others => NEXT_STATE <= SLEEP;\r
- end case;\r
- end process TRANSFORM;\r
-\r
----------------------------------------------------------\r
--- block memories --\r
----------------------------------------------------------\r
- -- Port A: SLV_BUS\r
- -- Port B: state machine\r
- THE_PED_MEM: ped_thr_true\r
- port map(\r
- DATAINA => slv_data_in(17 downto 0),\r
- DATAINB => b"00_0000_0000_0000_0000",\r
- ADDRESSA => slv_addr_in(6 downto 0),\r
- ADDRESSB => mem_addr_in,\r
- CLOCKA => clk_in,\r
- CLOCKB => mem_clk_in,\r
- CLOCKENA => '1',\r
- CLOCKENB => '1',\r
- WRA => mem_wr, -- BUGBUGBUG\r
- WRB => '0', -- state machine never writes!\r
- RESETA => reset_in,\r
- RESETB => reset_in,\r
- QA => mem_data,\r
- QB => ped_data\r
- );\r
--- Write signals\r
- mem_wr_x <= '1' when ( (mem_sel = '1') and (store_wr = '1') ) else '0';\r
-\r
-\r
--- Synchronize\r
- THE_SYNC_PROC: process(clk_in)\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- mem_wr <= mem_wr_x;\r
- end if;\r
- end process THE_SYNC_PROC;\r
-\r
----------------------------------------------------------\r
--- output signals --\r
----------------------------------------------------------\r
- slv_ack_out <= slv_ack;\r
- slv_data_out <= b"0000_0000_0000_00" & rdback_data;\r
-\r
- mem_0_d_out <= ped_data;\r
-\r
- stat(31 downto 20) <= (others => '0');\r
- stat(19 downto 16) <= block_addr;\r
- stat(15 downto 1) <= (others => '0');\r
- stat(0) <= mem_sel;\r
-\r
-end Behavioral;\r
jspc29 / trb3.git / commitdiff