--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module Version: 4.2
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 16 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+
+-- Fri Feb 8 13:39:45 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_scm_fifo_18x16 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end lattice_scm_fifo_18x16;
+
+architecture Structure of lattice_scm_fifo_18x16 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal wptr_4: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal rptr_4: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2: std_logic;
+ signal wcount_4: std_logic;
+ signal co1: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_1: std_logic;
+ signal rcount_4: std_logic;
+ signal co1_1: std_logic;
+ signal rden_i: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal rcount_w0: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+ signal rdataout17: std_logic;
+ signal rdataout16: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wren_i: std_logic;
+ signal scuba_vhi: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+
+ -- local component declarations
+ component DPR16X2
+ -- synopsys translate_off
+ generic (INITVAL : in String; GSR : in String);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic;
+ WAD3: in std_logic; WAD2: in std_logic;
+ WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic;
+ WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic;
+ RAD2: in std_logic; RAD1: in std_logic;
+ RAD0: in std_logic; WDO0: out std_logic;
+ WDO1: out std_logic; RDO0: out std_logic;
+ RDO1: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute initval : string;
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute GSR of fifo_pfu_0_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t10: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t9: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t8: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t4: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ FF_69: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_54: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC1=>scuba_vlo, PC0=>wcount_4, CO=>co2,
+ NC1=>open, NC0=>iwcount_4);
+
+ r_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC1=>scuba_vlo, PC0=>rcount_4, CO=>co2_1,
+ NC1=>open, NC0=>ircount_4);
+
+ empty_cmp_0: AGEB2
+ port map (A1=>rcount_1, A0=>rcount_0, B1=>w_g2b_xor_cluster_0,
+ B0=>wcount_r0, CI=>rden_i, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A1=>rcount_3, A0=>rcount_2, B1=>wcount_r3,
+ B0=>wcount_r2, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A1=>scuba_vlo, A0=>empty_cmp_set, B1=>scuba_vlo,
+ B0=>empty_cmp_clr, CI=>co1_2, GE=>empty_d_c);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>empty_d);
+
+ full_cmp_0: AGEB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>r_g2b_xor_cluster_0,
+ B0=>rcount_w0, CI=>wren_i, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rcount_w3,
+ B0=>rcount_w2, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A1=>scuba_vlo, A0=>full_cmp_set, B1=>scuba_vlo,
+ B0=>full_cmp_clr, CI=>co1_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>full_d);
+
+ fifo_pfu_0_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>rdataout16, RDO1=>rdataout17);
+
+ fifo_pfu_0_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>rdataout14, RDO1=>rdataout15);
+
+ fifo_pfu_0_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>rdataout12, RDO1=>rdataout13);
+
+ fifo_pfu_0_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>rdataout10, RDO1=>rdataout11);
+
+ fifo_pfu_0_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout8,
+ RDO1=>rdataout9);
+
+ fifo_pfu_0_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout6,
+ RDO1=>rdataout7);
+
+ fifo_pfu_0_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout4,
+ RDO1=>rdataout5);
+
+ fifo_pfu_0_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout2,
+ RDO1=>rdataout3);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ fifo_pfu_0_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>scuba_vhi, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>rdataout0,
+ RDO1=>rdataout1);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_scm_fifo_18x16 is
+ for Structure
+ for all:DPR16X2 use entity SCM.DPR16X2(V); end for;
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:OR2 use entity SCM.OR2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
-- Module Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_bram_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e
--- Wed Jan 16 16:32:24 2008
+-- Fri Feb 8 13:39:06 2008
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
---library SCM;
---use SCM.COMPONENTS.all;
+library SCM;
+use SCM.COMPONENTS.all;
-- synopsys translate_on
-entity lattice_scm_bram_fifo is
+entity lattice_scm_fifo_18x1k is
port (
Data: in std_logic_vector(17 downto 0);
WrClock: in std_logic;
Full: out std_logic;
AlmostEmpty: out std_logic;
AlmostFull: out std_logic);
-end lattice_scm_bram_fifo;
+end lattice_scm_fifo_18x1k;
-architecture Structure of lattice_scm_bram_fifo is
+architecture Structure of lattice_scm_fifo_18x1k is
-- internal signal declarations
signal scuba_vhi: std_logic;
attribute CSDECODE_W : string;
attribute DATA_WIDTH_R : string;
attribute DATA_WIDTH_W : string;
- attribute FULLPOINTER1 of trb_net16_bram_fifo_0_0 : label is "0b011111111100001";
- attribute FULLPOINTER of trb_net16_bram_fifo_0_0 : label is "0b011111111110001";
- attribute AFPOINTER1 of trb_net16_bram_fifo_0_0 : label is "0b001111110100001";
- attribute AFPOINTER of trb_net16_bram_fifo_0_0 : label is "0b001111110110001";
- attribute AEPOINTER1 of trb_net16_bram_fifo_0_0 : label is "0b000000010111111";
- attribute AEPOINTER of trb_net16_bram_fifo_0_0 : label is "0b000000010101111";
- attribute RESETMODE of trb_net16_bram_fifo_0_0 : label is "ASYNC";
- attribute REGMODE of trb_net16_bram_fifo_0_0 : label is "NOREG";
- attribute CSDECODE_R of trb_net16_bram_fifo_0_0 : label is "0b11";
- attribute CSDECODE_W of trb_net16_bram_fifo_0_0 : label is "0b11";
- attribute DATA_WIDTH_R of trb_net16_bram_fifo_0_0 : label is "18";
- attribute DATA_WIDTH_W of trb_net16_bram_fifo_0_0 : label is "18";
+ attribute FULLPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b011111111100001";
+ attribute FULLPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b011111111110001";
+ attribute AFPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b001111110100001";
+ attribute AFPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b001111110110001";
+ attribute AEPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b000000010111111";
+ attribute AEPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b000000010101111";
+ attribute RESETMODE of lattice_scm_fifo_18x1k_0_0 : label is "SYNC";
+ attribute REGMODE of lattice_scm_fifo_18x1k_0_0 : label is "NOREG";
+ attribute CSDECODE_R of lattice_scm_fifo_18x1k_0_0 : label is "0b11";
+ attribute CSDECODE_W of lattice_scm_fifo_18x1k_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of lattice_scm_fifo_18x1k_0_0 : label is "18";
+ attribute DATA_WIDTH_W of lattice_scm_fifo_18x1k_0_0 : label is "18";
attribute syn_keep : boolean;
begin
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
- trb_net16_bram_fifo_0_0: FIFO16KA
+ lattice_scm_fifo_18x1k_0_0: FIFO16KA
-- synopsys translate_off
generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001",
AFPOINTER1=> "001111110100001", AFPOINTER=> "001111110110001",
AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ RESETMODE=> "SYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18)
-- synopsys translate_on
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
end Structure;
-- synopsys translate_off
--- library SCM;
--- configuration Structure_CON of lattice_scm_bram_fifo is
--- for Structure
--- for all:VHI use entity SCM.VHI(V); end for;
--- for all:VLO use entity SCM.VLO(V); end for;
--- for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
--- end for;
--- end Structure_CON;
+library SCM;
+configuration Structure_CON of lattice_scm_fifo_18x1k is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module Version: 4.2
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 32 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+
+-- Fri Feb 8 13:40:11 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_scm_fifo_18x32 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end lattice_scm_fifo_18x32;
+
+architecture Structure of lattice_scm_fifo_18x32 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wptr_4_inv: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal rptr_5: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co2: std_logic;
+ signal wcount_5: std_logic;
+ signal co1: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co2_1: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_1: std_logic;
+ signal rdataout17: std_logic;
+ signal rdataout16: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_4: std_logic;
+ signal rden_i: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_4: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal rcount_w4: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_4: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+ signal mdL0_0_0: std_logic;
+ signal mdL0_0_1: std_logic;
+ signal mdL0_0_2: std_logic;
+ signal mdL0_0_3: std_logic;
+ signal mdL0_0_4: std_logic;
+ signal mdL0_0_5: std_logic;
+ signal mdL0_0_6: std_logic;
+ signal mdL0_0_7: std_logic;
+ signal mdL0_0_8: std_logic;
+ signal mdL0_0_9: std_logic;
+ signal mdL0_0_10: std_logic;
+ signal mdL0_0_11: std_logic;
+ signal mdL0_0_12: std_logic;
+ signal mdL0_0_13: std_logic;
+ signal mdL0_0_14: std_logic;
+ signal mdL0_0_15: std_logic;
+ signal mdL0_0_16: std_logic;
+ signal mdL0_0_17: std_logic;
+ signal dec_wre1: std_logic;
+ signal mdL0_1_0: std_logic;
+ signal mdL0_1_1: std_logic;
+ signal mdL0_1_2: std_logic;
+ signal mdL0_1_3: std_logic;
+ signal mdL0_1_4: std_logic;
+ signal mdL0_1_5: std_logic;
+ signal mdL0_1_6: std_logic;
+ signal mdL0_1_7: std_logic;
+ signal mdL0_1_8: std_logic;
+ signal mdL0_1_9: std_logic;
+ signal mdL0_1_10: std_logic;
+ signal mdL0_1_11: std_logic;
+ signal mdL0_1_12: std_logic;
+ signal mdL0_1_13: std_logic;
+ signal mdL0_1_14: std_logic;
+ signal mdL0_1_15: std_logic;
+ signal mdL0_1_16: std_logic;
+ signal mdL0_1_17: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wren_i: std_logic;
+ signal dec_wre3: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+
+ -- local component declarations
+ component DPR16X2
+ -- synopsys translate_off
+ generic (INITVAL : in String; GSR : in String);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic;
+ WAD3: in std_logic; WAD2: in std_logic;
+ WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic;
+ WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic;
+ RAD2: in std_logic; RAD1: in std_logic;
+ RAD0: in std_logic; WDO0: out std_logic;
+ WDO1: out std_logic; RDO0: out std_logic;
+ RDO1: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX21
+ port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
+ Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute initval : string;
+ attribute initval of LUT4_15 : label is "0x8000";
+ attribute initval of LUT4_14 : label is "0x8000";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute GSR of fifo_pfu_0_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_8 : label is "0x0000000000000000";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t12: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_2: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t11: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_1: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t10: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ INV_0: INV
+ port map (A=>wptr_4, Z=>wptr_4_inv);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wptr_4_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wre1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wptr_4, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wre3);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w4);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ FF_79: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_61: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC1=>wcount_5, PC0=>wcount_4, CO=>co2,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_1,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ mux_17: MUX21
+ port map (D0=>mdL0_0_0, D1=>mdL0_1_0, SD=>rptr_4, Z=>rdataout17);
+
+ mux_16: MUX21
+ port map (D0=>mdL0_0_1, D1=>mdL0_1_1, SD=>rptr_4, Z=>rdataout16);
+
+ mux_15: MUX21
+ port map (D0=>mdL0_0_2, D1=>mdL0_1_2, SD=>rptr_4, Z=>rdataout15);
+
+ mux_14: MUX21
+ port map (D0=>mdL0_0_3, D1=>mdL0_1_3, SD=>rptr_4, Z=>rdataout14);
+
+ mux_13: MUX21
+ port map (D0=>mdL0_0_4, D1=>mdL0_1_4, SD=>rptr_4, Z=>rdataout13);
+
+ mux_12: MUX21
+ port map (D0=>mdL0_0_5, D1=>mdL0_1_5, SD=>rptr_4, Z=>rdataout12);
+
+ mux_11: MUX21
+ port map (D0=>mdL0_0_6, D1=>mdL0_1_6, SD=>rptr_4, Z=>rdataout11);
+
+ mux_10: MUX21
+ port map (D0=>mdL0_0_7, D1=>mdL0_1_7, SD=>rptr_4, Z=>rdataout10);
+
+ mux_9: MUX21
+ port map (D0=>mdL0_0_8, D1=>mdL0_1_8, SD=>rptr_4, Z=>rdataout9);
+
+ mux_8: MUX21
+ port map (D0=>mdL0_0_9, D1=>mdL0_1_9, SD=>rptr_4, Z=>rdataout8);
+
+ mux_7: MUX21
+ port map (D0=>mdL0_0_10, D1=>mdL0_1_10, SD=>rptr_4, Z=>rdataout7);
+
+ mux_6: MUX21
+ port map (D0=>mdL0_0_11, D1=>mdL0_1_11, SD=>rptr_4, Z=>rdataout6);
+
+ mux_5: MUX21
+ port map (D0=>mdL0_0_12, D1=>mdL0_1_12, SD=>rptr_4, Z=>rdataout5);
+
+ mux_4: MUX21
+ port map (D0=>mdL0_0_13, D1=>mdL0_1_13, SD=>rptr_4, Z=>rdataout4);
+
+ mux_3: MUX21
+ port map (D0=>mdL0_0_14, D1=>mdL0_1_14, SD=>rptr_4, Z=>rdataout3);
+
+ mux_2: MUX21
+ port map (D0=>mdL0_0_15, D1=>mdL0_1_15, SD=>rptr_4, Z=>rdataout2);
+
+ mux_1: MUX21
+ port map (D0=>mdL0_0_16, D1=>mdL0_1_16, SD=>rptr_4, Z=>rdataout1);
+
+ mux_0: MUX21
+ port map (D0=>mdL0_0_17, D1=>mdL0_1_17, SD=>rptr_4, Z=>rdataout0);
+
+ empty_cmp_0: AGEB2
+ port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1,
+ B0=>wcount_r0, CI=>rden_i, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A1=>rcount_3, A0=>rcount_2, B1=>wcount_r3,
+ B0=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A1=>empty_cmp_set, A0=>rcount_4, B1=>empty_cmp_clr,
+ B0=>wcount_r4, CI=>co1_2, GE=>empty_d_c);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>empty_d);
+
+ full_cmp_0: AGEB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1,
+ B0=>rcount_w0, CI=>wren_i, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rcount_w3,
+ B0=>r_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A1=>full_cmp_set, A0=>wcount_4, B1=>full_cmp_clr,
+ B0=>rcount_w4, CI=>co1_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>full_d);
+
+ fifo_pfu_0_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_1, RDO1=>mdL0_0_0);
+
+ fifo_pfu_0_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_3, RDO1=>mdL0_0_2);
+
+ fifo_pfu_0_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_5, RDO1=>mdL0_0_4);
+
+ fifo_pfu_0_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_7, RDO1=>mdL0_0_6);
+
+ fifo_pfu_0_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_9,
+ RDO1=>mdL0_0_8);
+
+ fifo_pfu_0_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_11,
+ RDO1=>mdL0_0_10);
+
+ fifo_pfu_0_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_13,
+ RDO1=>mdL0_0_12);
+
+ fifo_pfu_0_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_15,
+ RDO1=>mdL0_0_14);
+
+ fifo_pfu_0_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_17,
+ RDO1=>mdL0_0_16);
+
+ fifo_pfu_1_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_1, RDO1=>mdL0_1_0);
+
+ fifo_pfu_1_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_3, RDO1=>mdL0_1_2);
+
+ fifo_pfu_1_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_5, RDO1=>mdL0_1_4);
+
+ fifo_pfu_1_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>wren_i, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_7, RDO1=>mdL0_1_6);
+
+ fifo_pfu_1_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_9,
+ RDO1=>mdL0_1_8);
+
+ fifo_pfu_1_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_11,
+ RDO1=>mdL0_1_10);
+
+ fifo_pfu_1_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_13,
+ RDO1=>mdL0_1_12);
+
+ fifo_pfu_1_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_15,
+ RDO1=>mdL0_1_14);
+
+ fifo_pfu_1_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>wren_i,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_17,
+ RDO1=>mdL0_1_16);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_scm_fifo_18x32 is
+ for Structure
+ for all:DPR16X2 use entity SCM.DPR16X2(V); end for;
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX21 use entity SCM.MUX21(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:OR2 use entity SCM.OR2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module Version: 4.2
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 64 -width 18 -rwidth 18 -pfu_fifo -no_enable -pe -1 -pf -1 -sync_reset -e
+
+-- Fri Feb 8 13:40:40 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity lattice_scm_fifo_18x64 is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end lattice_scm_fifo_18x64;
+
+architecture Structure of lattice_scm_fifo_18x64 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wptr_4_inv: std_logic;
+ signal wptr_5_inv: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal rptr_6: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal co3: std_logic;
+ signal wcount_6: std_logic;
+ signal co2: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal co3_1: std_logic;
+ signal rcount_6: std_logic;
+ signal co2_1: std_logic;
+ signal rdataout17: std_logic;
+ signal rdataout16: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rden_i: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+ signal mdL0_0_0: std_logic;
+ signal mdL0_0_1: std_logic;
+ signal mdL0_0_2: std_logic;
+ signal mdL0_0_3: std_logic;
+ signal mdL0_0_4: std_logic;
+ signal mdL0_0_5: std_logic;
+ signal mdL0_0_6: std_logic;
+ signal mdL0_0_7: std_logic;
+ signal mdL0_0_8: std_logic;
+ signal mdL0_0_9: std_logic;
+ signal mdL0_0_10: std_logic;
+ signal mdL0_0_11: std_logic;
+ signal mdL0_0_12: std_logic;
+ signal mdL0_0_13: std_logic;
+ signal mdL0_0_14: std_logic;
+ signal mdL0_0_15: std_logic;
+ signal mdL0_0_16: std_logic;
+ signal mdL0_0_17: std_logic;
+ signal mdL0_1_0: std_logic;
+ signal mdL0_1_1: std_logic;
+ signal mdL0_1_2: std_logic;
+ signal mdL0_1_3: std_logic;
+ signal mdL0_1_4: std_logic;
+ signal mdL0_1_5: std_logic;
+ signal mdL0_1_6: std_logic;
+ signal mdL0_1_7: std_logic;
+ signal mdL0_1_8: std_logic;
+ signal mdL0_1_9: std_logic;
+ signal mdL0_1_10: std_logic;
+ signal mdL0_1_11: std_logic;
+ signal mdL0_1_12: std_logic;
+ signal mdL0_1_13: std_logic;
+ signal mdL0_1_14: std_logic;
+ signal mdL0_1_15: std_logic;
+ signal mdL0_1_16: std_logic;
+ signal mdL0_1_17: std_logic;
+ signal dec_wpe1: std_logic;
+ signal mdL0_2_0: std_logic;
+ signal mdL0_2_1: std_logic;
+ signal mdL0_2_2: std_logic;
+ signal mdL0_2_3: std_logic;
+ signal mdL0_2_4: std_logic;
+ signal mdL0_2_5: std_logic;
+ signal mdL0_2_6: std_logic;
+ signal mdL0_2_7: std_logic;
+ signal mdL0_2_8: std_logic;
+ signal mdL0_2_9: std_logic;
+ signal mdL0_2_10: std_logic;
+ signal mdL0_2_11: std_logic;
+ signal mdL0_2_12: std_logic;
+ signal mdL0_2_13: std_logic;
+ signal mdL0_2_14: std_logic;
+ signal mdL0_2_15: std_logic;
+ signal mdL0_2_16: std_logic;
+ signal mdL0_2_17: std_logic;
+ signal dec_wre1: std_logic;
+ signal mdL0_3_0: std_logic;
+ signal mdL0_3_1: std_logic;
+ signal mdL0_3_2: std_logic;
+ signal mdL0_3_3: std_logic;
+ signal mdL0_3_4: std_logic;
+ signal mdL0_3_5: std_logic;
+ signal mdL0_3_6: std_logic;
+ signal mdL0_3_7: std_logic;
+ signal mdL0_3_8: std_logic;
+ signal mdL0_3_9: std_logic;
+ signal mdL0_3_10: std_logic;
+ signal mdL0_3_11: std_logic;
+ signal mdL0_3_12: std_logic;
+ signal mdL0_3_13: std_logic;
+ signal mdL0_3_14: std_logic;
+ signal mdL0_3_15: std_logic;
+ signal mdL0_3_16: std_logic;
+ signal mdL0_3_17: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal dec_wpe3: std_logic;
+ signal dec_wre3: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+
+ -- local component declarations
+ component DPR16X2
+ -- synopsys translate_off
+ generic (INITVAL : in String; GSR : in String);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic;
+ WAD3: in std_logic; WAD2: in std_logic;
+ WAD1: in std_logic; WAD0: in std_logic; WRE: in std_logic;
+ WPE: in std_logic; WCK: in std_logic; RAD3: in std_logic;
+ RAD2: in std_logic; RAD1: in std_logic;
+ RAD0: in std_logic; WDO0: out std_logic;
+ WDO1: out std_logic; RDO0: out std_logic;
+ RDO1: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX41
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ attribute GSR : string;
+ attribute initval : string;
+ attribute initval of LUT4_19 : label is "0x8000";
+ attribute initval of LUT4_18 : label is "0x8000";
+ attribute initval of LUT4_17 : label is "0x8000";
+ attribute initval of LUT4_16 : label is "0x8000";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute GSR of fifo_pfu_0_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_0_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_0_8 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_1_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_1_8 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_2_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_2_8 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_0 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_0 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_1 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_1 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_2 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_2 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_3 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_3 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_4 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_4 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_5 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_5 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_6 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_6 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_7 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_7 : label is "0x0000000000000000";
+ attribute GSR of fifo_pfu_3_8 : label is "ENABLED";
+ attribute initval of fifo_pfu_3_8 : label is "0x0000000000000000";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t14: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t13: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t12: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ INV_1: INV
+ port map (A=>wptr_4, Z=>wptr_4_inv);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wptr_4_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wre1);
+
+ INV_0: INV
+ port map (A=>wptr_5, Z=>wptr_5_inv);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wren_i, AD2=>wptr_5_inv, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wpe1);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vhi, AD2=>wptr_4, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wre3);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wren_i, AD2=>wptr_5, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec_wpe3);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_gcount_r26,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_gcount_w26,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w5);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ FF_89: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_68: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC1=>wcount_5, PC0=>wcount_4, CO=>co2,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC1=>scuba_vlo, PC0=>wcount_6, CO=>co3,
+ NC1=>open, NC0=>iwcount_6);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_1,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC1=>scuba_vlo, PC0=>rcount_6, CO=>co3_1,
+ NC1=>open, NC0=>ircount_6);
+
+ mux_17: MUX41
+ port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout17);
+
+ mux_16: MUX41
+ port map (D0=>mdL0_0_1, D1=>mdL0_1_1, D2=>mdL0_2_1, D3=>mdL0_3_1,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout16);
+
+ mux_15: MUX41
+ port map (D0=>mdL0_0_2, D1=>mdL0_1_2, D2=>mdL0_2_2, D3=>mdL0_3_2,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout15);
+
+ mux_14: MUX41
+ port map (D0=>mdL0_0_3, D1=>mdL0_1_3, D2=>mdL0_2_3, D3=>mdL0_3_3,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout14);
+
+ mux_13: MUX41
+ port map (D0=>mdL0_0_4, D1=>mdL0_1_4, D2=>mdL0_2_4, D3=>mdL0_3_4,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout13);
+
+ mux_12: MUX41
+ port map (D0=>mdL0_0_5, D1=>mdL0_1_5, D2=>mdL0_2_5, D3=>mdL0_3_5,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout12);
+
+ mux_11: MUX41
+ port map (D0=>mdL0_0_6, D1=>mdL0_1_6, D2=>mdL0_2_6, D3=>mdL0_3_6,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout11);
+
+ mux_10: MUX41
+ port map (D0=>mdL0_0_7, D1=>mdL0_1_7, D2=>mdL0_2_7, D3=>mdL0_3_7,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout10);
+
+ mux_9: MUX41
+ port map (D0=>mdL0_0_8, D1=>mdL0_1_8, D2=>mdL0_2_8, D3=>mdL0_3_8,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout9);
+
+ mux_8: MUX41
+ port map (D0=>mdL0_0_9, D1=>mdL0_1_9, D2=>mdL0_2_9, D3=>mdL0_3_9,
+ SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout8);
+
+ mux_7: MUX41
+ port map (D0=>mdL0_0_10, D1=>mdL0_1_10, D2=>mdL0_2_10,
+ D3=>mdL0_3_10, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout7);
+
+ mux_6: MUX41
+ port map (D0=>mdL0_0_11, D1=>mdL0_1_11, D2=>mdL0_2_11,
+ D3=>mdL0_3_11, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout6);
+
+ mux_5: MUX41
+ port map (D0=>mdL0_0_12, D1=>mdL0_1_12, D2=>mdL0_2_12,
+ D3=>mdL0_3_12, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout5);
+
+ mux_4: MUX41
+ port map (D0=>mdL0_0_13, D1=>mdL0_1_13, D2=>mdL0_2_13,
+ D3=>mdL0_3_13, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout4);
+
+ mux_3: MUX41
+ port map (D0=>mdL0_0_14, D1=>mdL0_1_14, D2=>mdL0_2_14,
+ D3=>mdL0_3_14, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout3);
+
+ mux_2: MUX41
+ port map (D0=>mdL0_0_15, D1=>mdL0_1_15, D2=>mdL0_2_15,
+ D3=>mdL0_3_15, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout2);
+
+ mux_1: MUX41
+ port map (D0=>mdL0_0_16, D1=>mdL0_1_16, D2=>mdL0_2_16,
+ D3=>mdL0_3_16, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout1);
+
+ mux_0: MUX41
+ port map (D0=>mdL0_0_17, D1=>mdL0_1_17, D2=>mdL0_2_17,
+ D3=>mdL0_3_17, SD1=>rptr_4, SD2=>rptr_5, Z=>rdataout0);
+
+ empty_cmp_0: AGEB2
+ port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1,
+ B0=>wcount_r0, CI=>rden_i, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A1=>rcount_3, A0=>rcount_2, B1=>w_g2b_xor_cluster_0,
+ B0=>wcount_r2, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A1=>rcount_5, A0=>rcount_4, B1=>wcount_r5,
+ B0=>wcount_r4, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
+ port map (A1=>scuba_vlo, A0=>empty_cmp_set, B1=>scuba_vlo,
+ B0=>empty_cmp_clr, CI=>co2_2, GE=>empty_d_c);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>empty_d);
+
+ full_cmp_0: AGEB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1,
+ B0=>rcount_w0, CI=>wren_i, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>r_g2b_xor_cluster_0,
+ B0=>rcount_w2, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rcount_w5,
+ B0=>rcount_w4, CI=>co1_3, GE=>co2_3);
+
+ full_cmp_3: AGEB2
+ port map (A1=>scuba_vlo, A0=>full_cmp_set, B1=>scuba_vlo,
+ B0=>full_cmp_clr, CI=>co2_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>full_d);
+
+ fifo_pfu_0_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_1, RDO1=>mdL0_0_0);
+
+ fifo_pfu_0_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_3, RDO1=>mdL0_0_2);
+
+ fifo_pfu_0_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_5, RDO1=>mdL0_0_4);
+
+ fifo_pfu_0_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_0_7, RDO1=>mdL0_0_6);
+
+ fifo_pfu_0_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_9,
+ RDO1=>mdL0_0_8);
+
+ fifo_pfu_0_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_11,
+ RDO1=>mdL0_0_10);
+
+ fifo_pfu_0_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_13,
+ RDO1=>mdL0_0_12);
+
+ fifo_pfu_0_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_15,
+ RDO1=>mdL0_0_14);
+
+ fifo_pfu_0_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_0_17,
+ RDO1=>mdL0_0_16);
+
+ fifo_pfu_1_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_1, RDO1=>mdL0_1_0);
+
+ fifo_pfu_1_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_3, RDO1=>mdL0_1_2);
+
+ fifo_pfu_1_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_5, RDO1=>mdL0_1_4);
+
+ fifo_pfu_1_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe1, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_1_7, RDO1=>mdL0_1_6);
+
+ fifo_pfu_1_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_9,
+ RDO1=>mdL0_1_8);
+
+ fifo_pfu_1_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_11,
+ RDO1=>mdL0_1_10);
+
+ fifo_pfu_1_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_13,
+ RDO1=>mdL0_1_12);
+
+ fifo_pfu_1_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_15,
+ RDO1=>mdL0_1_14);
+
+ fifo_pfu_1_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe1,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_1_17,
+ RDO1=>mdL0_1_16);
+
+ fifo_pfu_2_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_2_1, RDO1=>mdL0_2_0);
+
+ fifo_pfu_2_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_2_3, RDO1=>mdL0_2_2);
+
+ fifo_pfu_2_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_2_5, RDO1=>mdL0_2_4);
+
+ fifo_pfu_2_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_2_7, RDO1=>mdL0_2_6);
+
+ fifo_pfu_2_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_2_9,
+ RDO1=>mdL0_2_8);
+
+ fifo_pfu_2_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_2_11,
+ RDO1=>mdL0_2_10);
+
+ fifo_pfu_2_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_2_13,
+ RDO1=>mdL0_2_12);
+
+ fifo_pfu_2_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_2_15,
+ RDO1=>mdL0_2_14);
+
+ fifo_pfu_2_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre1, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_2_17,
+ RDO1=>mdL0_2_16);
+
+ fifo_pfu_3_0: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(16), DI1=>Data(17), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_3_1, RDO1=>mdL0_3_0);
+
+ fifo_pfu_3_1: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(14), DI1=>Data(15), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_3_3, RDO1=>mdL0_3_2);
+
+ fifo_pfu_3_2: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(12), DI1=>Data(13), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_3_5, RDO1=>mdL0_3_4);
+
+ fifo_pfu_3_3: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(10), DI1=>Data(11), WAD3=>wptr_3,
+ WAD2=>wptr_2, WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3,
+ WPE=>dec_wpe3, WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2,
+ RAD1=>rptr_1, RAD0=>rptr_0, WDO0=>open, WDO1=>open,
+ RDO0=>mdL0_3_7, RDO1=>mdL0_3_6);
+
+ fifo_pfu_3_4: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(8), DI1=>Data(9), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_3_9,
+ RDO1=>mdL0_3_8);
+
+ fifo_pfu_3_5: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(6), DI1=>Data(7), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_3_11,
+ RDO1=>mdL0_3_10);
+
+ fifo_pfu_3_6: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(4), DI1=>Data(5), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_3_13,
+ RDO1=>mdL0_3_12);
+
+ fifo_pfu_3_7: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(2), DI1=>Data(3), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_3_15,
+ RDO1=>mdL0_3_14);
+
+ fifo_pfu_3_8: DPR16X2
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED", initval=> "0x0000000000000000")
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), WAD3=>wptr_3, WAD2=>wptr_2,
+ WAD1=>wptr_1, WAD0=>wptr_0, WRE=>dec_wre3, WPE=>dec_wpe3,
+ WCK=>WrClock, RAD3=>rptr_3, RAD2=>rptr_2, RAD1=>rptr_1,
+ RAD0=>rptr_0, WDO0=>open, WDO1=>open, RDO0=>mdL0_3_17,
+ RDO1=>mdL0_3_16);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of lattice_scm_fifo_18x64 is
+ for Structure
+ for all:DPR16X2 use entity SCM.DPR16X2(V); end for;
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX41 use entity SCM.MUX41(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:OR2 use entity SCM.OR2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
---library SCM;
---use SCM.COMPONENTS.all;
--- synopsys translate_on
-
--- entity trb_net_fifo is
--- generic (
--- WIDTH : integer := 18; -- FIFO word width
--- DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1)
--- FORCE_LUT : integer range 0 to 1 := 0 --don't allow use of BlockRAM
--- );
--- port (
--- CLK : in std_logic;
--- RESET : in std_logic;
--- CLK_EN : in std_logic;
---
--- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
--- WRITE_ENABLE_IN : in std_logic;
--- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
--- --output data MUST BE 0 if no data is available
--- READ_ENABLE_IN : in std_logic;
--- FULL_OUT : out std_logic; -- Full Flag
--- EMPTY_OUT : out std_logic;
--- DEPTH_OUT : out std_logic_vector(7 downto 0)
--- );
---
--- end trb_net_fifo;
-
-architecture Structure of trb_net_fifo is
- component lattice_scm_bram_fifo is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(17 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic
- );
- end component lattice_scm_bram_fifo;
-
- signal fifo_write_enable, fifo_read_enable : std_logic;
- signal fifo_data_out : std_logic_vector(17 downto 0);
- signal fifo_empty, fifo_full : std_logic;
- signal buf_EMPTY_OUT, next_EMPTY_OUT : std_logic;
- type state_t is (EMPTY, BUFFER_FULL, BRAM_NOT_EMPTY);
- signal state, next_state : state_t;
- signal next_DATA_OUT, buf_DATA_OUT : std_logic_vector(WIDTH-1 downto 0);
- signal last_fifo_empty : std_logic;
-begin
-
- gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate
- bram_fifo:lattice_scm_bram_fifo
- port map (
- Data => DATA_IN,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => fifo_write_enable,
- RdEn => fifo_read_enable,
- Reset => RESET,
- RPReset => RESET,
- Q => fifo_data_out,
- Empty => fifo_empty,
- Full => fifo_full,
- AlmostEmpty => open,
- AlmostFull => open
- );
- end generate;
-
-
-
- FULL_OUT <= fifo_full;
-
- EMPTY_OUT <= buf_EMPTY_OUT;
- DATA_OUT <= buf_DATA_OUT;
-
- process(CLK)
- begin
- next_DATA_OUT <= buf_DATA_OUT;
- next_EMPTY_OUT <= buf_EMPTY_OUT;
- next_state <= state;
- fifo_write_enable <= '0';
- fifo_read_enable <= '0';
- case state is
- when EMPTY =>
- next_DATA_OUT <= DATA_IN;
- if WRITE_ENABLE_IN = '1' then
- next_state <= BUFFER_FULL;
- next_EMPTY_OUT <= '0';
- end if;
- when BUFFER_FULL =>
- if READ_ENABLE_IN = '1' and WRITE_ENABLE_IN = '0' then
- next_state <= EMPTY;
- next_EMPTY_OUT <= '1';
- elsif READ_ENABLE_IN = '1' and WRITE_ENABLE_IN = '1' then
- next_DATA_OUT <= DATA_IN;
- elsif READ_ENABLE_IN = '0' and WRITE_ENABLE_IN = '1' then
- fifo_write_enable <= '1';
- next_state <= BRAM_NOT_EMPTY;
- end if;
- when BRAM_NOT_EMPTY =>
- if WRITE_ENABLE_IN <= '1' then
- fifo_write_enable <= '1';
- end if;
- fifo_read_enable <= READ_ENABLE_IN;
- fifo_write_enable <= WRITE_ENABLE_IN;
- next_DATA_OUT <= fifo_data_out;
- if last_fifo_empty <= '0' and fifo_empty <= '1' then
- next_state <= BUFFER_FULL;
- end if;
- end case;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- buf_DATA_OUT <= (others => '0');
- state <= EMPTY;
- buf_EMPTY_OUT <= '1';
- else
- buf_DATA_OUT <= next_DATA_OUT;
- state <= next_state;
- buf_EMPTY_OUT <= next_EMPTY_OUT;
- end if;
- end if;
- end process;
-
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- last_fifo_empty <= '0';
- else
- last_fifo_empty <= fifo_empty;
- end if;
- end if;
- end process;
-
-
-
-end architecture;
\ No newline at end of file
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
+ APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO
);
port(
FULL_OUT => fifo_to_apl_full,
EMPTY_OUT => fifo_to_apl_empty
);
- end generate CHECK_BUFFER5;
+ end generate;
CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate
FIFO_TO_APL: trb_net16_dummy_fifo
end if;
when WRONG_ADDR =>
fifo_to_apl_read <= not fifo_to_apl_empty;
+ throw_away <= '1';
when MY_ADDR =>
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out);
+ if APL_WRITE_4_PACKETS = 0 then
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out));
+ throw_away <= not or_all(fifo_to_apl_packet_num_out);
+ else
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before;
+ end if;
fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away);
throw_away <= not or_all(fifo_to_apl_packet_num_out);
end case;
fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN;
fifo_to_apl_read <= sbuf_to_apl_free;
- next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out);
- throw_away <= not or_all(fifo_to_apl_packet_num_out);
+
+ process(fifo_to_apl_read_before, fifo_to_apl_packet_num_out)
+ begin
+ if APL_WRITE_4_PACKETS = 0 then
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out);
+ throw_away <= not or_all(fifo_to_apl_packet_num_out);
+ else
+ next_APL_DATAREADY_OUT <= fifo_to_apl_read_before;
+ throw_away <= '0';
+ end if;
+ end process;
CLK_REG: process(CLK)
begin
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