DEBUG should be in clk_rd aka ADC clock domain

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 26e41f6fad7730a2500bc9eb25201eba53e1049d..488f7eafd5ad02922d39e91d9b7e63415eb90b2c 100644 (file)
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -321,7 +321,7 @@ begin
 
     proc_debug : process
     begin
-      wait until rising_edge(CLK);
+      wait until rising_edge(clk_rd);
       state_q(i)                           <= state(i);
       counter_q(i)                         <= counter(i);
       DEBUG(i * 32 + 31 downto i * 32 + 4) <= std_logic_vector(counter_q(i));