DEFINE PORT GROUP "fpga_led0_group" "fpga_led_to_board0*";
IOBUF GROUP "fpga_led0_group" IO_TYPE=LVCMOS25;
-LOCATE COMP "fpga_aux_to_board0_0" SITE "T7";
-LOCATE COMP "fpga_aux_to_board0_1" SITE "R6";
-LOCATE COMP "fpga_aux_to_board0_2" SITE "K2";
-LOCATE COMP "fpga_aux_to_board0_3" SITE "T8";
-LOCATE COMP "fpga_aux_to_board0_4" SITE "K4";
-LOCATE COMP "fpga_aux_to_board0_5" SITE "K1";
-LOCATE COMP "fpga_aux_to_board0_6" SITE "E1";
-LOCATE COMP "fpga_aux_to_board0_7" SITE "K5";
-LOCATE COMP "fpga_aux_to_board0_8" SITE "B2";
-LOCATE COMP "fpga_aux_to_board0_9" SITE "B3";
+LOCATE COMP "fpga_aux_from_board0_0" SITE "T7";
+LOCATE COMP "fpga_aux_from_board0_1" SITE "R6";
+LOCATE COMP "fpga_aux_from_board0_2" SITE "K2";
+LOCATE COMP "fpga_aux_from_board0_3" SITE "T8";
+LOCATE COMP "fpga_aux_from_board0_4" SITE "K4";
+LOCATE COMP "fpga_aux_from_board0_5" SITE "K1";
+LOCATE COMP "fpga_aux_to_board0_0" SITE "E1";
+LOCATE COMP "fpga_aux_to_board0_1" SITE "K5";
+LOCATE COMP "fpga_aux_to_board0_2" SITE "B2";
+LOCATE COMP "fpga_aux_to_board0_3" SITE "B3";
DEFINE PORT GROUP "fpga_aux0_group" "fpga_aux_to_board0*";
IOBUF GROUP "fpga_aux0_group" IO_TYPE=LVCMOS25;
DEFINE PORT GROUP "fpga_led1_group" "fpga_led_to_board1*";
IOBUF GROUP "fpga_led1_group" IO_TYPE=LVCMOS25;
-LOCATE COMP "fpga_aux_to_board1_0" SITE "AE25";
-LOCATE COMP "fpga_aux_to_board1_1" SITE "AE24";
-LOCATE COMP "fpga_aux_to_board1_2" SITE "W23";
-LOCATE COMP "fpga_aux_to_board1_3" SITE "AF24";
-LOCATE COMP "fpga_aux_to_board1_4" SITE "AA25";
-LOCATE COMP "fpga_aux_to_board1_5" SITE "W22";
-LOCATE COMP "fpga_aux_to_board1_6" SITE "AA26";
-LOCATE COMP "fpga_aux_to_board1_7" SITE "Y24";
-LOCATE COMP "fpga_aux_to_board1_8" SITE "W21";
-LOCATE COMP "fpga_aux_to_board1_9" SITE "W20";
+LOCATE COMP "fpga_aux_from_board1_0" SITE "AE25";
+LOCATE COMP "fpga_aux_from_board1_1" SITE "AE24";
+LOCATE COMP "fpga_aux_from_board1_2" SITE "W23";
+LOCATE COMP "fpga_aux_from_board1_3" SITE "AF24";
+LOCATE COMP "fpga_aux_from_board1_4" SITE "AA25";
+LOCATE COMP "fpga_aux_from_board1_5" SITE "W22";
+LOCATE COMP "fpga_aux_to_board1_0" SITE "AA26";
+LOCATE COMP "fpga_aux_to_board1_1" SITE "Y24";
+LOCATE COMP "fpga_aux_to_board1_2" SITE "W21";
+LOCATE COMP "fpga_aux_to_board1_3" SITE "W20";
DEFINE PORT GROUP "fpga_aux1_group" "fpga_aux_to_board1*";
IOBUF GROUP "fpga_aux01_group" IO_TYPE=LVCMOS25;
port(
--Clock signal
clk : in std_logic;
+ fast_clk : in std_logic;
reset : in std_logic;
--signals to and from MuPix 3 chip/board DACS
timestamp_from_mupix : in std_logic_vector(7 downto 0);
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
- fpga_aux_from_board : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board : in std_logic_vector(5 downto 0);
ldpix_to_mupix : out std_logic;
ldcol_to_mupix : out std_logic;
timestamp_to_mupix : out std_logic_vector(7 downto 0);
spi_clk_to_board : out std_logic;
spi_ld_to_board : out std_logic;
fpga_led_to_board : out std_logic_vector(3 downto 0);
- fpga_aux_to_board : out std_logic_vector(9 downto 0);
+ fpga_aux_to_board : out std_logic_vector(3 downto 0);
--resets
timestampreset_in : in std_logic;
--signal declarations
-- Bus Handler
- constant NUM_PORTS : integer := 8;
+ constant NUM_PORTS : integer := 9;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal sout_c_from_mupix_sync : std_logic;
signal sout_d_from_mupix_sync : std_logic;
signal hbus_from_mupix_sync : std_logic;
- signal fpga_aux_from_board_sync : std_logic_vector(9 downto 0);
+ signal fpga_aux_from_board_sync : std_logic_vector(5 downto 0);
+ signal szintilator_sync : std_logic;
5 => x"0300", -- Event Buffer
6 => x"0100", -- Trigger Handler
7 => x"0200", -- Board Interface
+ 8 => x"0400", -- TimeWalk Measurement
others => x"0000"),
PORT_ADDR_MASK
4 => 8, -- HitBus Histograms
5 => 8, -- Event Buffer
6 => 8, -- Trigger Handler
- 7 => 8, -- Board Interface
+ 7 => 8, -- Board Interface
+ 8 => 8, -- TimeWalk Measurement
others => 0)
--PORT_MASK_ENABLE => 1
board_interface_1: entity work.board_interface
port map (
clk_in => clk,
+ fast_clk_in => fast_clk,
timestamp_from_mupix => timestamp_from_mupix,
rowaddr_from_mupix => rowaddr_from_mupix,
coladdr_from_mupix => coladdr_from_mupix,
sout_d_from_mupix_sync => sout_d_from_mupix_sync,
hbus_from_mupix_sync => hbus_from_mupix_sync,
fpga_aux_from_board_sync => fpga_aux_from_board_sync,
+ szintilator_sync => szintilator_sync,
SLV_READ_IN => slv_read(7),
SLV_WRITE_IN => slv_write(7),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6));
+ TimeWalkWithFiFo_1: entity work.TimeWalkWithFiFo
+ port map (
+ trb_slv_clock => clk,
+ fast_clk => fast_clk,
+ reset => reset,
+ hitbus => hbus_from_mupix_sync,
+ szintillator_trigger => szintilator_sync,
+ SLV_READ_IN => slv_read(8),
+ SLV_WRITE_IN => slv_write(8),
+ SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),
+ SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),
+ SLV_ADDR_IN => slv_addr(8*16+15 downto 8*16),
+ SLV_ACK_OUT => slv_ack(8),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8));
+
end Behavioral;
entity board_interface is
port(
clk_in : in std_logic;
+ fast_clk_in : in std_logic;
-- signals from mupix
timestamp_from_mupix : in std_logic_vector(7 downto 0);
rowaddr_from_mupix : in std_logic_vector(5 downto 0);
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
- fpga_aux_from_board : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board : in std_logic_vector(5 downto 0);
--synced (and inverted) signals
timestamp_from_mupix_sync : out std_logic_vector(7 downto 0);
rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0);
sout_c_from_mupix_sync : out std_logic;
sout_d_from_mupix_sync : out std_logic;
hbus_from_mupix_sync : out std_logic;
- fpga_aux_from_board_sync : out std_logic_vector(9 downto 0);
+ fpga_aux_from_board_sync : out std_logic_vector(5 downto 0);
+ szintilator_sync : out std_logic;
--Trb Slv-Bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
begin
+-- fast synchronize for hitbus and szintilator
+ fast_sync: process (fast_clk_in) is
+ begin -- process fast_sync
+ if rising_edge(fast_clk_in) then
+ szintilator_sync <= fpga_aux_from_board(0);
+ if invert_signals_int = '1' then
+ hbus_from_mupix_sync <= hbus_from_mupix;
+ else
+ hbus_from_mupix_sync <= not hbus_from_mupix;
+ end if;
+ end if;
+ end process fast_sync;
-- Synchronize input signals
process
begin
wait until rising_edge(clk_in);
+ fpga_aux_from_board_sync <= fpga_aux_from_board;
if invert_signals_int = '1' then
timestamp_from_mupix_sync <= not timestamp_from_mupix;
rowaddr_from_mupix_sync <= not rowaddr_from_mupix;
sout_c_from_mupix_sync <= not sout_c_from_mupix;
sout_d_from_mupix_sync <= not sout_d_from_mupix;
priout_from_mupix_sync <= priout_from_mupix; --is inverted on the chip
- hbus_from_mupix_sync <= hbus_from_mupix;
- fpga_aux_from_board_sync <= fpga_aux_from_board;
else
timestamp_from_mupix_sync <= timestamp_from_mupix;
rowaddr_from_mupix_sync <= rowaddr_from_mupix;
sout_c_from_mupix_sync <= sout_c_from_mupix;
sout_d_from_mupix_sync <= sout_d_from_mupix;
priout_from_mupix_sync <= not priout_from_mupix; --is inverted on the chip
- hbus_from_mupix_sync <= not hbus_from_mupix;
- fpga_aux_from_board_sync <= not fpga_aux_from_board;
end if;
end process;
component MuPix3_Board
port (
clk : in std_logic;
+ fast_clk : in std_logic;
reset : in std_logic;
timestamp_from_mupix : in std_logic_vector(7 downto 0);
rowaddr_from_mupix : in std_logic_vector(5 downto 0);
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
- fpga_aux_from_board : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board : in std_logic_vector(5 downto 0);
ldpix_to_mupix : out std_logic;
ldcol_to_mupix : out std_logic;
timestamp_to_mupix : out std_logic_vector(7 downto 0);
spi_clk_to_board : out std_logic;
spi_ld_to_board : out std_logic;
fpga_led_to_board : out std_logic_vector(3 downto 0);
- fpga_aux_to_board : out std_logic_vector(9 downto 0);
+ fpga_aux_to_board : out std_logic_vector(3 downto 0);
timestampreset_in : in std_logic;
eventcounterreset_in : in std_logic;
TIMING_TRG_IN : in std_logic;
component board_interface is
port (
clk_in : in std_logic;
+ fast_clk_in : in std_logic;
timestamp_from_mupix : in std_logic_vector(7 downto 0);
rowaddr_from_mupix : in std_logic_vector(5 downto 0);
coladdr_from_mupix : in std_logic_vector(5 downto 0);
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
- fpga_aux_from_board : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board : in std_logic_vector(5 downto 0);
timestamp_from_mupix_sync : out std_logic_vector(7 downto 0);
rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0);
coladdr_from_mupix_sync : out std_logic_vector(5 downto 0);
sout_c_from_mupix_sync : out std_logic;
sout_d_from_mupix_sync : out std_logic;
hbus_form_mupix_sync : out std_logic;
- fpga_aux_from_board_sync : out std_logic_vector(9 downto 0);
+ fpga_aux_from_board_sync : out std_logic_vector(5 downto 0);
+ szintilator_sync : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic);
end component resethandler;
+
+ component TimeWalkWithFiFo is
+ port (
+ trb_slv_clock : in std_logic;
+ fast_clk : in std_logic;
+ reset : in std_logic;
+ hitbus : in std_logic;
+ szintillator_trigger : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic);
+ end component TimeWalkWithFiFo;
+
+ component TimeWalk is
+ port (
+ clk : in std_logic;
+ reset : in std_logic;
+ hitbus : in std_logic;
+ hitbus_timeout : in std_logic_vector(31 downto 0);
+ szintillator_trigger : in std_logic;
+ readyToWrite : in std_logic;
+ measurementFinished : out std_logic;
+ measurementData : out std_logic_vector(31 downto 0));
+ end component TimeWalk;
end mupix_components;
add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd"
add_file -vhdl -lib "work" "sources/ResetHandler.vhd"
+add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd"
+add_file -vhdl -lib "work" "sources/TimeWalk.vhd"
+add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd"
\ No newline at end of file
sout_c_from_mupix0 : in std_logic;
sout_d_from_mupix0 : in std_logic;
hbus_from_mupix0 : in std_logic;
- fpga_aux_from_board0 : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board0 : in std_logic_vector(5 downto 0);
ldpix_to_mupix0 : out std_logic;
ldcol_to_mupix0 : out std_logic;
timestamp_to_mupix0 : out std_logic_vector(7 downto 0);
spi_clk_to_board0 : out std_logic;
spi_ld_to_board0 : out std_logic;
fpga_led_to_board0 : out std_logic_vector(3 downto 0);
- fpga_aux_to_board0 : out std_logic_vector(9 downto 0);
+ fpga_aux_to_board0 : out std_logic_vector(3 downto 0);
--Connections to Sensorboard 1
timestamp_from_mupix1 : in std_logic_vector(7 downto 0);
sout_c_from_mupix1 : in std_logic;
sout_d_from_mupix1 : in std_logic;
hbus_from_mupix1 : in std_logic;
- fpga_aux_from_board1 : in std_logic_vector(9 downto 0);
+ fpga_aux_from_board1 : in std_logic_vector(5 downto 0);
ldpix_to_mupix1 : out std_logic;
ldcol_to_mupix1 : out std_logic;
timestamp_to_mupix1 : out std_logic_vector(7 downto 0);
spi_clk_to_board1 : out std_logic;
spi_ld_to_board1 : out std_logic;
fpga_led_to_board1 : out std_logic_vector(3 downto 0);
- fpga_aux_to_board1 : out std_logic_vector(9 downto 0);
+ fpga_aux_to_board1 : out std_logic_vector(3 downto 0);
---------------------------------------------------------------------------
MuPix3_Board_0 : MuPix3_Board
port map (
clk => clk_100_i,
+ fast_clk => clk_200_i,
reset => reset_i,
timestamp_from_mupix => timestamp_from_mupix0,
rowaddr_from_mupix => rowaddr_from_mupix0,
MuPix3_Board_1 : MuPix3_Board
port map (
clk => clk_100_i,
+ fast_clk => clk_200_i,
reset => reset_i,
timestamp_from_mupix => timestamp_from_mupix1,
rowaddr_from_mupix => rowaddr_from_mupix1,
jspc29 / trb3.git / commitdiff