cleanup

diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd
index 7bd606db2a2c12bb281f97416c8cbaebdbb59c21..dab24a657fac644ee89bde9785e8c2d33316fbf9 100644 (file)
--- a/gbe_trb/base/gbe_wrapper_fifo.vhd
+++ b/gbe_trb/base/gbe_wrapper_fifo.vhd
@@ -137,9 +137,7 @@ begin
     FRAME_REQ_IN        => FRAME_REQ_IN,
     FRAME_ACK_OUT       => FRAME_ACK_OUT,
     FRAME_AVAIL_OUT     => FRAME_AVAIL_OUT,
-    FRAME_START_OUT     => FRAME_START_OUT,
-    --
-    DEBUG               => open
+    FRAME_START_OUT     => FRAME_START_OUT
   );
   -------------------------------------------------------------------------------------------------
 

diff --git a/gbe_trb/base/rx_rb.vhd b/gbe_trb/base/rx_rb.vhd
index 31f3f5e0c771dba0ceb15618809bf8c01145aef0..c6e1b762e8a8920e56ffd7acebd01bbbe8a8f359 100644 (file)
--- a/gbe_trb/base/rx_rb.vhd
+++ b/gbe_trb/base/rx_rb.vhd
@@ -21,12 +21,22 @@ entity rx_rb is
     FRAME_REQ_IN        : in  std_logic; -- one pulse starts readout of frame stored in ring buffer\r
     FRAME_ACK_OUT       : out std_logic; -- one pulse for "end of frame"\r
     FRAME_AVAIL_OUT     : out std_logic; -- number of frames stored in ring buffer\r
-    FRAME_START_OUT     : out std_logic; -- StartOfFrame signal\r
-    --\r
-    DEBUG               : out std_logic_vector(15 downto 0)\r
+    FRAME_START_OUT     : out std_logic  -- StartOfFrame signal\r
   );\r
 end entity rx_rb;\r
 \r
+-- This entity acts as receiv buffer for the new GbE media interface. It connects to the MAC RX ports,\r
+-- and is storing incoming Ethernet frames. \r
+-- Broken frames (indicated by MAC_RX_ERROR_IN) are dropped, and in addition, frames which can't be stored\r
+-- completely (due to potential ring buffer overflow) are also dropped.\r
+-- This entity can forward frames on request by doing "DMA":\r
+-- If a frame is requested by FRAME_REQ_IN, the entity decides if a full frame is available (as shown by\r
+-- FRAME_AVAIL_OUT), in case no data is present, a FRAME_ACK_OUT is generated to avoid deadlocks, but\r
+-- no data is transfered.\r
+-- If a frame can be transfered, FRAME_START_OUT is set for one cycle, and data is written out \r
+-- (handshaking with FIFO_FULL_IN) on FIFO_Q_OUT, with data validated by FIFO_WR_OUT.\r
+-- With the EOF signal (FIFO_Q_OUT(8)) set FRAME_ACK_OUT is also set and the transfer ends.\r
+\r
 architecture rx_rb_arch of rx_rb is\r
 \r
 -- Components\r
@@ -53,29 +63,30 @@ architecture rx_rb_arch of rx_rb is
   signal rd_ptr             : unsigned(11 downto 0);\r
   signal wr_ptr             : unsigned(11 downto 0);\r
   signal last_wr_ptr        : std_logic_vector(11 downto 0);\r
-  signal rb_used            : unsigned(11 downto 0);\r
-  signal rb_full            : std_logic;\r
-  signal rb_empty           : std_logic;\r
-  signal ce_wr_ptr          : std_logic;\r
-  signal ld_wr_ptr          : std_logic;\r
-  signal ce_rd_ptr          : std_logic;\r
-  signal wr_ram             : std_logic;\r
-  signal rd_ram             : std_logic;\r
+  signal rb_used_x          : unsigned(11 downto 0);\r
+  signal rb_full_x          : std_logic;\r
+  signal rb_empty_x         : std_logic;\r
+  signal ce_wr_ptr_x        : std_logic;\r
+  signal ld_wr_ptr_x        : std_logic;\r
+  signal ce_rd_ptr_x        : std_logic;\r
+  signal wr_ram_x           : std_logic;\r
+  signal rd_ram_x           : std_logic;\r
   signal ram_q              : std_logic_vector(8 downto 0);\r
-  signal frame_active       : std_logic;\r
   signal frame_requested    : std_logic;\r
   signal frame_acknowledged : std_logic;\r
   signal fifo_wr_int        : std_logic;\r
   signal empty_read_ack     : std_logic;\r
-  signal normal_read_ack    : std_logic;\r
+  signal normal_read_ack_x  : std_logic;\r
   signal sof_int            : std_logic;\r
   signal frames_avail       : unsigned(7 downto 0);\r
-\r
-\r
+  signal frame_active       : std_logic;\r
+  signal frame_error        : std_logic;\r
+  \r
 begin\r
 \r
   -- FrameActive: we must not change to "receive" in the middle of a frame\r
-  -- when "buffer full" condition is deasserted\r
+  -- when "buffer full" condition is deasserted.\r
+  -- Needs to be extra process, not inside the state machine!\r
   THE_FRAME_ACTIVE_PROC: process( CLK )\r
   begin\r
     if( rising_edge(CLK) ) then\r
@@ -89,56 +100,57 @@ begin
     end if;\r
   end process THE_FRAME_ACTIVE_PROC;\r
 \r
+  -- Read pointer for ring buffer\r
+  THE_RD_PTR_PROC: process( CLK )\r
+  begin\r
+    if( rising_edge(CLK) ) then\r
+      if   ( RESET = '1' ) then\r
+        rd_ptr <= (others => '0');\r
+      elsif( ce_rd_ptr_x = '1' ) then\r
+        rd_ptr <= rd_ptr + 1;\r
+      end if;\r
+    end if;\r
+  end process THE_RD_PTR_PROC;\r
+\r
   -- Write pointer for ring buffer\r
   THE_WR_PTR_PROC: process( CLK )\r
   begin\r
     if( rising_edge(CLK) ) then\r
       if   ( RESET = '1' ) then\r
         wr_ptr <= (others => '0');\r
-      elsif( ld_wr_ptr = '1' ) then\r
+      elsif( ld_wr_ptr_x = '1' ) then\r
         wr_ptr <= unsigned(last_wr_ptr);\r
-      elsif( ce_wr_ptr = '1' ) then\r
+      elsif( ce_wr_ptr_x = '1' ) then\r
         wr_ptr <= wr_ptr + 1;\r
       end if;\r
     end if;\r
   end process THE_WR_PTR_PROC;\r
 \r
-  -- Read pointer for ring buffer\r
-  THE_RD_PTR_PROC: process( CLK )\r
+  -- last write pointer: used to drop a broken frame, in case\r
+  THE_LAST_WR_PTR_PROC: process( CLK )\r
   begin\r
     if( rising_edge(CLK) ) then\r
       if   ( RESET = '1' ) then\r
-        rd_ptr <= (others => '0');\r
-      elsif( ce_rd_ptr = '1' ) then\r
-        rd_ptr <= rd_ptr + 1;\r
+        last_wr_ptr <= (others => '0');\r
+      elsif( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then\r
+        last_wr_ptr <= std_logic_vector(wr_ptr);\r
       end if;\r
     end if;\r
-  end process THE_RD_PTR_PROC;\r
+  end process THE_LAST_WR_PTR_PROC;\r
 \r
   -- ring buffer fill level\r
-  rb_used <= wr_ptr - rd_ptr;\r
+  rb_used_x <= wr_ptr - rd_ptr;\r
   \r
   -- ring buffer full \r
   -- TAKE CARE: the last byte of a frame is taken into account\r
   --            by "one less" for the full condition\r
-  rb_full  <= '1' when (rb_used(11 downto 1) = b"1111_1111_111") else '0';\r
+  rb_full_x  <= '1' when (rb_used_x(11 downto 1) = b"1111_1111_111") else '0';\r
 \r
-  rb_empty <= '1' when (rb_used(11 downto 0) = b"0000_0000_0000") else '0';\r
+  -- ring buffer empty\r
+  rb_empty_x <= '1' when (rb_used_x(11 downto 0) = b"0000_0000_0000") else '0';\r
 \r
-  MAC_RX_FIFOFULL_OUT <= rb_full;\r
+  MAC_RX_FIFOFULL_OUT <= rb_full_x;\r
   \r
-  -- last write pointer: used to drop a broken frame, in case\r
-  THE_LAST_WR_PTR_PROC: process( CLK )\r
-  begin\r
-    if( rising_edge(CLK) ) then\r
-      if   ( RESET = '1' ) then\r
-        last_wr_ptr <= (others => '0');\r
-      elsif( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then\r
-        last_wr_ptr <= std_logic_vector(wr_ptr);\r
-      end if;\r
-    end if;\r
-  end process THE_LAST_WR_PTR_PROC;\r
-\r
   -- DPRAM as ring buffer\r
   THE_DP_RAM: rb_4k_9\r
   port map(\r
@@ -146,7 +158,7 @@ begin
     RDADDRESS         => std_logic_vector(rd_ptr),\r
     DATA(8)           => MAC_RX_EOF_IN,\r
     DATA(7 downto 0)  => MAC_RX_DATA_IN,\r
-    WE                => wr_ram,\r
+    WE                => wr_ram_x,\r
     RDCLOCK           => CLK,\r
     RDCLOCKEN         => '1',\r
     RESET             => RESET,\r
@@ -155,14 +167,28 @@ begin
     Q                 => ram_q\r
   );\r
 \r
-  -- write signal\r
-  wr_ram    <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or\r
-                        ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0'))  \r
-                    else '0';\r
-  ce_wr_ptr <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full = '0')) or\r
-                        ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full = '0'))  \r
-                    else '0';\r
+  -- write signal \r
+  wr_ram_x    <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full_x = '0')) or -- first byte of frame\r
+                          ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full_x = '0'))    -- all other bytes of frame\r
+                     else '0';\r
+  ce_wr_ptr_x <= '1' when ((STATE = RX_READY) and (MAC_RX_WR_IN = '1') and (rb_full_x = '0')) or\r
+                          ((STATE = RX_FRAME) and (MAC_RX_WR_IN = '1') and (rb_full_x = '0'))  \r
+                     else '0';\r
 \r
+  -- FrameError: catches problem with FIFOFULL during a frame write.\r
+  THE_FRAME_ERROR_PROC: process( CLK )\r
+  begin\r
+    if( rising_edge(CLK) ) then\r
+      if   ( RESET = '1' ) then\r
+        frame_error <= '0';\r
+      elsif( (frame_active = '1') and (rb_full_x = '1') and (MAC_RX_WR_IN = '1') ) then\r
+        frame_error <= '1';\r
+      elsif( (frame_active = '0') ) then -- could be better!\r
+        frame_error <= '0';\r
+      end if;\r
+    end if;\r
+  end process THE_FRAME_ERROR_PROC;\r
+                     \r
   -- FrameReq signal, one pulse only\r
   THE_FRAME_REQ_PROC: process( CLK )\r
   begin\r
@@ -176,29 +202,24 @@ begin
       end if;\r
     end if;\r
   end process THE_FRAME_REQ_PROC;\r
-\r
-  -- EmptyReadAck signal, used to handle a request to RX_RB with no frame to send\r
-  empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK);\r
   \r
-  -- NormalReadAck signal\r
---  normal_read_ack <= ram_q(8) and fifo_wr_int when rising_edge(CLK); -- ADDED 2nd step\r
-  normal_read_ack <= ram_q(8) and fifo_wr_int;\r
+  -- NormalReadAck signal: ends a normal data transfer by EOF\r
+  normal_read_ack_x <= ram_q(8) and fifo_wr_int;\r
   \r
   -- read signal\r
-  rd_ram    <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0';\r
-  ce_rd_ptr <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty = '0')) else '0';\r
-  \r
-  sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK);\r
-  \r
-  FRAME_ACK_OUT <= normal_read_ack or empty_read_ack when rising_edge(CLK); -- ADDED\r
-  \r
-  FRAME_START_OUT <= sof_int when rising_edge(CLK); -- ADDED\r
-  \r
-  FIFO_Q_OUT <= ram_q when rising_edge(CLK); -- ADDED\r
-  \r
-  fifo_wr_int <= rd_ram when rising_edge(CLK);\r
-   \r
-  FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK); -- ADDED\r
+  rd_ram_x    <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0';\r
+  ce_rd_ptr_x <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0';\r
+\r
+--  THE_SYNC_PROC: process( CLK )\r
+--  begin\r
+    empty_read_ack  <= FRAME_REQ_IN and rb_empty_x when rising_edge(CLK);\r
+    sof_int         <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK);  \r
+    FRAME_START_OUT <= sof_int when rising_edge(CLK);\r
+    fifo_wr_int     <= rd_ram_x when rising_edge(CLK);\r
+    FIFO_WR_OUT     <= fifo_wr_int when rising_edge(CLK);\r
+    FRAME_ACK_OUT   <= normal_read_ack_x or empty_read_ack when rising_edge(CLK);  \r
+    FIFO_Q_OUT      <= ram_q when rising_edge(CLK);\r
+--  end process THE_SYNC_PROC;\r
   \r
   -- FramesAvailable counter\r
   THE_FRAMES_AVAIL_PROC: process( CLK )\r
@@ -206,10 +227,10 @@ begin
     if( rising_edge(CLK) ) then\r
       if   ( RESET = '1' ) then\r
         frames_avail <= (others => '0');\r
-      elsif( (STATE = FRAME_OK) and (normal_read_ack = '0') ) then\r
+      elsif( (STATE = FRAME_OK) and (normal_read_ack_x = '0') ) then\r
         -- one frame written successfully\r
         frames_avail <= frames_avail + 1;\r
-      elsif( (STATE /= FRAME_OK) and (normal_read_ack = '1') ) then\r
+      elsif( (STATE /= FRAME_OK) and (normal_read_ack_x = '1') ) then\r
         -- one frame read successfully\r
         frames_avail <= frames_avail - 1;\r
       end if;\r
@@ -232,14 +253,14 @@ begin
     end if;\r
   end process THE_FSM;\r
 \r
-  THE_STATE_TRANSITIONS: process( STATE, MAC_RX_WR_IN, MAC_RX_EOF_IN, MAC_RX_ERROR_IN, frame_active, rb_full )\r
+  THE_STATE_TRANSITIONS: process( STATE, MAC_RX_WR_IN, MAC_RX_EOF_IN, MAC_RX_ERROR_IN, frame_active, rb_full_x )\r
   begin\r
-    ld_wr_ptr <= '0';\r
+    ld_wr_ptr_x <= '0';\r
     \r
     case STATE is\r
 \r
       when RX_DENY =>\r
-        if( (frame_active = '0') and (rb_full = '0') ) then\r
+        if( (frame_active = '0') and (rb_full_x = '0') ) then\r
           NEXT_STATE <= RX_READY;\r
         else\r
           NEXT_STATE <= RX_DENY;\r
@@ -253,11 +274,11 @@ begin
         end if;\r
         \r
       when RX_FRAME =>\r
-        if   ( (MAC_RX_EOF_IN = '1') and (MAC_RX_ERROR_IN = '0') and (rb_full = '0') ) then\r
+        if   ( (MAC_RX_EOF_IN = '1') and (MAC_RX_ERROR_IN = '0') and (rb_full_x = '0') ) then\r
           NEXT_STATE <= FRAME_OK;\r
-        elsif( (MAC_RX_EOF_IN = '1') and ((MAC_RX_ERROR_IN = '1') or (rb_full = '1')) ) then\r
+        elsif( (MAC_RX_EOF_IN = '1') and ((MAC_RX_ERROR_IN = '1') or (rb_full_x = '1')) ) then\r
           NEXT_STATE <= FRAME_BAD;\r
-          ld_wr_ptr <= '1';\r
+          ld_wr_ptr_x <= '1';\r
         else\r
           NEXT_STATE <= RX_FRAME;\r
         end if;\r
@@ -266,7 +287,7 @@ begin
         NEXT_STATE <= FORWARD;\r
         \r
       when FORWARD =>\r
-        if( rb_full = '0' ) then\r
+        if( rb_full_x = '0' ) then\r
           NEXT_STATE <= RX_READY;\r
         else\r
           NEXT_STATE <= RX_DENY;\r
@@ -276,7 +297,7 @@ begin
         NEXT_STATE <= SKIP;\r
         \r
       when SKIP =>\r
-        if( rb_full = '0' ) then\r
+        if( rb_full_x = '0' ) then\r
           NEXT_STATE <= RX_READY;\r
         else\r
           NEXT_STATE <= RX_DENY;\r

diff --git a/gbe_trb/base/sgl_ctrl.vhd b/gbe_trb/base/sgl_ctrl.vhd
index ad79d4d76359b812b452eaf6b71a9e9effab6b59..e1249fa1b83a13aff57a14cfa682d81e0fa2e37f 100644 (file)
--- a/gbe_trb/base/sgl_ctrl.vhd
+++ b/gbe_trb/base/sgl_ctrl.vhd
@@ -29,9 +29,8 @@ entity sgl_ctrl is
     DL_TX_PORT_SEL_OUT    : out std_logic; -- '0' => LOCAL, '1' UL\r
     LOCAL_TX_PORT_SEL_OUT : out std_logic;\r
     UL_TX_PORT_SEL_OUT    : out std_logic;\r
-\r
     --\r
-    DEBUG               : out std_logic_vector(15 downto 0)\r
+    DEBUG                 : out std_logic_vector(15 downto 0)\r
   );\r
 end entity sgl_ctrl;\r
 \r
@@ -229,7 +228,6 @@ begin
     local_tx_port_sel_x <= '0';\r
     ul_tx_port_sel_x <= '0';\r
 \r
-\r
     case STATE is\r
       when IDLE =>\r
         bsm <= x"0";\r

diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd
index 9bd55d9f12802a6b6ba5567774b3fe169d7c89ba..940d72ad07a6d6f646b315874b9937ca8661d8c5 100644 (file)
--- a/gbe_trb/base/tx_fifo.vhd
+++ b/gbe_trb/base/tx_fifo.vhd
@@ -6,6 +6,7 @@ library work;
 \r
 -- BUG: if no frame is stored in FIFO, and filling the FIFO triggers FIFOFULL,\r
 --      the frame must be written completely but dropped.\r
+--      Otherwise we experience a deadlock in data transfer.\r
 \r
 -- BUG: use dynamic ALMOSTFULL to accommodate for pipelining inside the data\r
 --      multiplexer of hub.\r
@@ -32,9 +33,7 @@ entity tx_fifo is
     FIFO_D_IN         : in  std_logic_vector(8 downto 0);\r
     -- Link stuff\r
     FRAME_START_IN    : in  std_logic;\r
-    LINK_ACTIVE_IN    : in  std_logic;\r
-    --\r
-    DEBUG             : out std_logic_vector(15 downto 0)\r
+    LINK_ACTIVE_IN    : in  std_logic\r
   );\r
 end entity tx_fifo;\r
 \r
@@ -66,6 +65,7 @@ architecture tx_fifo_arch of tx_fifo is
   signal mac_tx_read       : std_logic;\r
   signal frame_active      : std_logic;\r
   signal fifo_wr           : std_logic;\r
+  signal no_frames_x       : std_logic;\r
 \r
 begin\r
 \r
@@ -99,7 +99,7 @@ begin
     FULL          => open,\r
     ALMOSTFULL    => FIFO_FULL_OUT\r
   );\r
-  \r
+\r
   MAC_FIFOEOF_OUT <= mac_fifoeof;\r
 \r
   mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK);\r
@@ -130,4 +130,8 @@ begin
 \r
   MAC_FIFOAVAIL_OUT <= '1' when (frames_avail /= x"00") else '0';\r
 \r
+  -- Bugfix: dropped partially stored frame, if it is the only frame and we run into FIFO full condition\r
+  no_frames_x <= '1' when (frames_avail = x"00") else '0';\r
+  \r
+  \r
 end architecture;\r

diff --git a/gbe_trb_ecp3/base/gbe_med_fifo.vhd b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
index 23afea00dee4e7687092593c5e6584555813573b..519224263a7e15693ffe5788f940e856ee8d5e32 100644 (file)
--- a/gbe_trb_ecp3/base/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
@@ -606,9 +606,7 @@ begin
         FRAME_REQ_IN        => FRAME_REQ_IN(i),
         FRAME_ACK_OUT       => FRAME_ACK_OUT(i),
         FRAME_AVAIL_OUT     => FRAME_AVAIL_OUT(i),
-        FRAME_START_OUT     => FRAME_START_OUT(i),
-        --
-        DEBUG               => open
+        FRAME_START_OUT     => FRAME_START_OUT(i)
       );
       
       -- TX FIFO
@@ -629,9 +627,7 @@ begin
         FIFO_D_IN         => FIFO_DATA_IN((i + 1) * 9 - 1 downto i * 9),
         -- Link stuff
         FRAME_START_IN    => FRAME_START_IN(i),
-        LINK_ACTIVE_IN    => link_active(i), --an_complete(i),
-        --
-        DEBUG             => open
+        LINK_ACTIVE_IN    => link_active(i)
       );
       
       PCS_AN_READY_OUT(i) <= an_complete(i); -- needed for internal SCTRL

diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd
index 3e1eac89f97aa16e9dca3e854a21164d0a690b49..564f456987d757cf57214d664d0994d2c6c07961 100644 (file)
--- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd
@@ -487,43 +487,6 @@ begin
     STATE_OUT         => rx_bsm --open
   );
 
-  -- "Good" debugging pins
-  debug(0)           <= pll_lol;
-  debug(1)           <= rx_cdr_lol;
-  debug(2)           <= rx_los_low;
-  debug(3)           <= sd_rx_cv_error(0);
-  debug(4)           <= lsm_status;
-  debug(5)           <= tx_pcs_rst;
-  debug(6)           <= rx_serdes_rst;
-  debug(7)           <= rx_pcs_rst;
-  debug(8)           <= link_rx_ready;
-  debug(9)           <= link_tx_ready;
-  debug(10)          <= rx_bsm(0); --'0';
-  debug(11)          <= rx_bsm(1); --'0';
-  debug(12)          <= rx_bsm(2); --'0';
-  debug(13)          <= rx_bsm(3); --'0';
-  debug(14)          <= '0';
-  debug(15)          <= '0';
-  debug(16)          <= '0';
-  debug(17)          <= '0';
-  debug(18)          <= '0';
-  debug(19)          <= '0';
-  -- "Bad" debugging pins
-  debug(20) <= RESET;
-  debug(21) <= CLEAR;
-  debug(22) <= '0';
-  debug(23) <= '0';
-  debug(24) <= '0';
-  debug(25) <= '0';
-  debug(26) <= '0';
-  debug(27) <= '0';
-  debug(28) <= '0';
-  debug(29) <= '0';
-  debug(30) <= '0';
-  debug(31) <= '0';
-  debug(32) <= '0';
-  debug(33) <= CLK_125;
-
   -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
   SYNC_RST_SIGS: entity work.signal_sync 
   generic map( WIDTH => 2 )
@@ -537,6 +500,29 @@ begin
     D_OUT(1) => rx_serdes_rst_q
   );
 
+--  -- "Good" debugging pins
+  debug(7 downto 0)  <= sd_tx_data;
+  debug(15 downto 8) <= sd_rx_data;
+  debug(16)          <= sd_tx_kcntl(0);
+  debug(17)          <= sd_rx_kcntl(0);
+  debug(18)          <= sd_tx_correct_disp(0);
+  debug(19)          <= sd_rx_disp_error(0);
+  -- "Bad" debugging pins
+  debug(20) <= pcs_tx_en;
+  debug(21) <= pcs_rx_en;
+  debug(22) <= '0';
+  debug(23) <= '0';
+  debug(24) <= '0';
+  debug(25) <= '0';
+  debug(26) <= '0';
+  debug(27) <= '0';
+  debug(28) <= '0';
+  debug(29) <= '0';
+  debug(30) <= '0';
+  debug(31) <= '0';
+  debug(32) <= sd_rx_clk;
+  debug(33) <= CLK_125;
+
   -- SGMII core
   SGMII_GBE_PCS : sgmii_gbe_core
   port map(
@@ -724,9 +710,7 @@ begin
     FRAME_REQ_IN        => FRAME_REQ_IN,
     FRAME_ACK_OUT       => FRAME_ACK_OUT,
     FRAME_AVAIL_OUT     => FRAME_AVAIL_OUT,
-    FRAME_START_OUT     => FRAME_START_OUT,
-    --
-    DEBUG               => open
+    FRAME_START_OUT     => FRAME_START_OUT
   );
   
   -- TX FIFO
@@ -747,9 +731,7 @@ begin
     FIFO_D_IN         => FIFO_DATA_IN,
     -- Link stuff
     FRAME_START_IN    => FRAME_START_IN,
-    LINK_ACTIVE_IN    => link_active,
-    --
-    DEBUG             => open
+    LINK_ACTIVE_IN    => link_active
   );
   
   FIFO_FULL_OUT    <= fifo_full_i;
@@ -814,6 +796,43 @@ begin
 --  debug(32) <= '0';
 --  debug(33) <= CLK_125;
 
+--  -- "Good" debugging pins
+--  debug(0)           <= pll_lol;
+--  debug(1)           <= rx_cdr_lol;
+--  debug(2)           <= rx_los_low;
+--  debug(3)           <= sd_rx_cv_error(0);
+--  debug(4)           <= lsm_status;
+--  debug(5)           <= tx_pcs_rst;
+--  debug(6)           <= rx_serdes_rst;
+--  debug(7)           <= rx_pcs_rst;
+--  debug(8)           <= link_rx_ready;
+--  debug(9)           <= link_tx_ready;
+--  debug(10)          <= rx_bsm(0); --'0';
+--  debug(11)          <= rx_bsm(1); --'0';
+--  debug(12)          <= rx_bsm(2); --'0';
+--  debug(13)          <= rx_bsm(3); --'0';
+--  debug(14)          <= '0';
+--  debug(15)          <= '0';
+--  debug(16)          <= '0';
+--  debug(17)          <= '0';
+--  debug(18)          <= '0';
+--  debug(19)          <= '0';
+--  -- "Bad" debugging pins
+--  debug(20) <= RESET;
+--  debug(21) <= CLEAR;
+--  debug(22) <= '0';
+--  debug(23) <= '0';
+--  debug(24) <= '0';
+--  debug(25) <= '0';
+--  debug(26) <= '0';
+--  debug(27) <= '0';
+--  debug(28) <= '0';
+--  debug(29) <= '0';
+--  debug(30) <= '0';
+--  debug(31) <= '0';
+--  debug(32) <= '0';
+--  debug(33) <= CLK_125;
+
 --  -- "Good" debugging pins
 --  debug(7 downto 0)  <= pcs_txd;
 --  debug(15 downto 8) <= pcs_rxd;