| ++> gbe_logic_wrapper ++> gbe_main_control ++> gbe_protocol_selector ++> gbe_response_constructor_ARP
| | ++> gbe_response_constructor_DHCP
| | ++> gbe_response_constructor_Ping
- | | ++> gbe_response_constructor_SCTRL
+ | | ++> gbe_response_constructor_SCTRL +-> fifo_2kx9x18_wcnt
| | ++> gbe_response_constructor_Forward
| +-> gbe_transmit_control
| +-> gbe_frame_constr
# locate the PCS blocks
-LOCATE COMP "THE_GBE_MED_PCSA/gbe_serdes/PCSD_INST" SITE "PCSA";
-LOCATE COMP "THE_GBE_MED_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB";
-LOCATE COMP "THE_GBE_MED_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC";
-LOCATE COMP "THE_GBE_MED_PCSD/gbe_serdes/PCSD_INST" SITE "PCSD";
+LOCATE COMP "THE_GBE_MED_PCSA/THE_GBE_SERDES/PCSD_INST" SITE "PCSA";
+LOCATE COMP "THE_GBE_MED_PCSB/THE_GBE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "THE_GBE_MED_PCSC/THE_GBE_SERDES/PCSD_INST" SITE "PCSC";
+LOCATE COMP "THE_GBE_MED_PCSD/THE_GBE_SERDES/PCSD_INST" SITE "PCSD";
# main frequencies
# read from SCI can be delayed due to long read strobe
-MULTICYCLE FROM ASIC THE_GBE_MED_PCSA/gbe_serdes/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE FROM ASIC THE_GBE_MED_PCSB/gbe_serdes/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE FROM ASIC THE_GBE_MED_PCSC/gbe_serdes/PCSD_INST PIN SCIRDATA* 15 ns;
-MULTICYCLE FROM ASIC THE_GBE_MED_PCSD/gbe_serdes/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC THE_GBE_MED_PCSA/THE_GBE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC THE_GBE_MED_PCSB/THE_GBE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC THE_GBE_MED_PCSC/THE_GBE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+MULTICYCLE FROM ASIC THE_GBE_MED_PCSD/THE_GBE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
##################################################################################################
signal oob_2_reg : std_logic_vector(31 downto 0);
signal oob_3_reg : std_logic_vector(31 downto 0);
+ signal debug_wrapper : std_logic_vector(31 downto 0);
+
begin
-- SerDes usage:
-- 8 : fifo_eof
-- 7..0: data
--- DBG(31 downto 0) <= debug_pcsd(31 downto 0);
+ DBG(31 downto 0) <= debug_wrapper(31 downto 0);
DBG(32) <= '0';
DBG(33) <= master_clk;
port map(
CLK_125_IN => master_clk,
RESET => reset_i,
- GSR_N => reset_n_i,
-- we connect to FIFO interface directly
-- FIFO interface TX (send frames)
FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
MAC_RX_EOF_IN => sniffer_eof,
MAC_RX_ERROR_IN => sniffer_error,
--
- PCS_AN_READY_IN => link_active, -- check here
- LINK_ACTIVE_IN => link_active, -- check here
+ LINK_ACTIVE_IN => link_active,
-- unique adresses
MC_UNIQUE_ID_IN => timer.uid,
MY_TRBNET_ADDRESS_IN => timer.network_address,
MAKE_RESET_OUT => reset_via_gbe,
-- debug
STATUS_OUT => status,
- DEBUG_OUT => DBG(31 downto 0) --open
+ DEBUG_OUT => debug_wrapper --open
);
-------------------------------------------------------------------------------