signal flash_miso_i : std_logic;
signal flash_mosi_i : std_logic;
- signal pcs_an_ready : std_logic;
signal link_active : std_logic;
-- the new FIFO interface
signal port_sel : std_logic_vector(0 downto 0);
- signal scatter_cycle_done : std_logic;
- signal gather_cycle_done : std_logic;
-
signal sniffer_data : std_logic_vector(7 downto 0);
signal sniffer_wr : std_logic;
signal sniffer_eof : std_logic;
signal sniffer_error : std_logic;
- signal tick_int : std_logic;
signal fwd_mac_int : std_logic_vector(47 downto 0);
signal fwd_ip_int : std_logic_vector(31 downto 0);
MAC_RX_EOF_OUT => sniffer_eof,
MAC_RX_ERROR_OUT => sniffer_error,
-- Status
- PCS_AN_READY_OUT => pcs_an_ready,
+ PCS_AN_READY_OUT => open,
LINK_ACTIVE_OUT => link_active,
TICK_MS_IN => tick_us_int,
-- Debug
FRAME_AVAIL_IN => ul_rx_frame_avail,
FRAME_REQ_OUT => ul_rx_frame_req,
FRAME_ACK_IN => ul_rx_frame_ack,
- CYCLE_DONE_OUT => scatter_cycle_done, --open,
+ CYCLE_DONE_OUT => open,
--
DEBUG => open
);
FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack(0 downto 0),
PORT_SELECT_OUT(0 downto 0) => port_sel,
PORT_MUX_OUT => open,
- CYCLE_DONE_OUT => gather_cycle_done, --open,
+ CYCLE_DONE_OUT => open,
--
DEBUG => open
);
debug(12) <= fwd_data_valid_int;
debug(13) <= fwd_busy_int;
debug(14) <= additional_reg(31);
- debug(15) <= tick_int;
+ debug(15) <= tick_us_int;
debug(16) <= debug(64);
debug(17) <= debug(65);
debug(18) <= debug(66);