saved_data_fpga <= INTERNAL_DATA_IN;
end if;
elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
- buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
+ if saved_address(15 downto 4) = x"001" then
+ buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
+ end if;
end if;
-- when others =>
-- saved_data_fpga <= x"deadface";
signal led_counter : std_logic_vector(16 downto 0);
signal rx_led, tx_led : std_logic_vector(3 downto 0);
attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
attribute syn_keep of led_counter : signal is true;
+ attribute syn_keep of reset_i : signal is true;
+ attribute syn_preserve of reset_i : signal is true;
signal reset_word_cnt : std_logic_vector(19 downto 0);
\r
architecture Behavioral of spi_databus_memory is\r
\r
--- Components\r
- component spi_dpram is\r
- port(\r
- DATAINA : in std_logic_vector(31 downto 0);\r
- DATAINB : in std_logic_vector(7 downto 0);\r
- ADDRESSA : in std_logic_vector(5 downto 0);\r
- ADDRESSB : in std_logic_vector(7 downto 0);\r
- CLOCKA : in std_logic;\r
- CLOCKB : in std_logic;\r
- CLOCKENA : in std_logic;\r
- CLOCKENB : in std_logic;\r
- WRA : in std_logic;\r
- WRB : in std_logic;\r
- RESETA : in std_logic;\r
- RESETB : in std_logic;\r
- QA : out std_logic_vector(31 downto 0);\r
- QB : out std_logic_vector(7 downto 0)\r
- );\r
- end component;\r
\r
-- Signals\r
type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
signal buf_MED_PACKET_NUM_OUT : std_logic_vector(MII_NUMBER*c_NUM_WIDTH-1 downto 0);
signal buf_MED_DATA_OUT : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ signal HUB_locked : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
+
+
signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
signal HC_DATAREADY_IN : std_logic;
REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16),
+ STAT_locked => HUB_locked(i),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32)
REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
MY_ADDRESS_IN => HUB_ADDRESS,
STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0),
+ STAT_locked => HUB_locked(i),
STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32),
STAT_FSM => stat_ipu_fsm,
gen_select_no_logic : if i = 2 generate
buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
+ HUB_locked(i) <= '0';
HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
end process;
--Control Registers
- HUB_CTRL_activepoints <= HC_CTRL_REGS(2**2*32-1 downto 0);
HUB_CTRL_media_interfaces_off <= HC_CTRL_REGS(2**2*32+31 downto 2**2*32);
-
+ PROC_active_points : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ for i in 0 to 2**(c_MUX_WIDTH-1)-1 loop
+ if HUB_locked(i) = '0' then
+ HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32);
+ end if;
+ end loop;
+ end if;
+ end process;
---------------------------------------------------------------------
MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
--Status ports
STAT_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0);
REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
STAT : out std_logic_vector (15 downto 0);
+ STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0)
MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
--Status ports
STAT_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
STAT_FSM : out std_logic_vector (15 downto 0);
STAT_FSM(12 downto 10)<= packet_counter;
STAT_FSM(15 downto 13)<= dhdr_addr;
+ STAT_locked <= locked;
+
end architecture;
REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0);
--Status ports (for debugging)
STAT : out std_logic_vector (15 downto 0);
+ STAT_locked : out std_logic;
STAT_POINTS_locked : out std_logic_vector (31 downto 0);
STAT_ERRORBITS : out std_logic_vector (31 downto 0);
CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1')
SYN_READ_IN => REPLY_POOL_READ
);
+STAT_locked <= locked;
+
----------------------------------
--Debugging
----------------------------------