integrated solutions using the peripheral FPGAs, for example to provide a
timing reference, transport the acquired data to the eventbuilder and
configuration of the attached ASIC via slow control. This was realised for the
-n-XYTER ASIC, which provides the digital timestamp and the analoge pulse height of
+n-XYTER ASIC, which provides the digital timestamp and the analogue pulse height of
self-triggered $128$ channels. In this case, the integration of the read-out
and slow control (e.\,g. trigger windows) on the peripheral FPGA was easily
achieved due to the well-documented VHDL interfaces of the TRB3 platform.
-The peripheral FPGA also reads out the ADC for the digitization of the pulse
+The peripheral FPGA also reads out the ADC for the digitisation of the pulse
height information.
\section{J\"{u}lich Test Beamtime 2012}\label{sec:juelich}