updated trb3_gbe config files

diff --git a/trb3_gbe/config_125.vhd b/trb3_gbe/config_125.vhd
index 2ce4e59749d33eae08bc64f6e76bf162fafda4a3..1f5a7e2d6603669d0459d1d8446fd045db5276f9 100644 (file)
--- a/trb3_gbe/config_125.vhd
+++ b/trb3_gbe/config_125.vhd
@@ -23,17 +23,23 @@ package config is
     constant USE_125_MHZ            : integer := c_YES;    
    
 --Only slow-control, no trigger or read-out
-    constant USE_SCTRL_ONLY         : integer := c_YES;    
+    constant USE_SCTRL_ONLY         : integer := c_NO;    
 
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;
-    
+
+--Run external 200 MHz clock source
+    constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO;        
    
 --Address settings   
     constant INIT_ENDPOINT_ID       : std_logic_vector := x"0005";
     constant INIT_ADDRESS           : std_logic_vector := x"F305";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"40";
-   
+
+
+--Statistics for generated trigger signals?
+    constant INCLUDE_STATISTICS     : integer := c_YES;
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -89,6 +95,9 @@ package config is
     constant CLOCK_FREQUENCY_ARR  : hub_mii_t := (100,125);
     constant MEDIA_FREQUENCY_ARR  : hub_mii_t := (200,125);
                           
+    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0) := (others => '0');       
+                          
+                          
   --declare constants, filled in body                          
     constant INTERNAL_NUM         : integer;
     constant INTERFACE_NUM        : integer;
@@ -119,4 +128,4 @@ package body config is
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
   
-end package body;
\ No newline at end of file
+end package body;

diff --git a/trb3_gbe/config_default.vhd b/trb3_gbe/config_default.vhd
index 1281487891e62ed2c689b5b85f66328ef1a1aa92..a0fe19d19f20e1184c2c8f44fc89c3a3003539d2 100644 (file)
--- a/trb3_gbe/config_default.vhd
+++ b/trb3_gbe/config_default.vhd
@@ -27,13 +27,19 @@ package config is
 
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;
-    
+
+--Run external 200 MHz clock source
+    constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO;        
    
 --Address settings   
     constant INIT_ENDPOINT_ID       : std_logic_vector := x"0005";
     constant INIT_ADDRESS           : std_logic_vector := x"F305";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"40";
-   
+
+
+--Statistics for generated trigger signals?
+    constant INCLUDE_STATISTICS     : integer := c_YES;
+    
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -89,6 +95,9 @@ package config is
     constant CLOCK_FREQUENCY_ARR  : hub_mii_t := (100,125);
     constant MEDIA_FREQUENCY_ARR  : hub_mii_t := (200,125);
                           
+    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0) := (others => '0');       
+                          
+                          
   --declare constants, filled in body                          
     constant INTERNAL_NUM         : integer;
     constant INTERFACE_NUM        : integer;