-- Signal declaration (Testbench)
signal powerup_reset : std_logic := '1';
- signal prompt_reset : std_logic := '1';
+ signal prompt_reset : std_logic := '1';
- signal general_reset_n : std_logic := '1';
- signal general_reset : std_logic := '0';
+ signal general_reset_n : std_logic := '1';
+ signal general_reset : std_logic := '0';
- signal sca_enable : std_logic_vector(0 downto 0) := "1";
+ signal sca_enable : std_logic_vector(0 downto 0) := "1";
signal start_transaction : std_logic := '0';
- signal start_reset : std_logic := '0';
+ signal start_reset : std_logic := '0';
signal start_connect : std_logic := '0';
- signal start_transaction_s0 : std_logic := '0';
- signal start_reset_s0 : std_logic := '0';
- signal start_connect_s0 : std_logic := '0';
+ signal start_transaction_s0 : std_logic := '0';
+ signal start_reset_s0 : std_logic := '0';
+ signal start_connect_s0 : std_logic := '0';
signal inject_crc_error : std_logic := '0';
- signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11";
+ signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11";
signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11";
- signal hdlc_to_sca : std_logic := '1';
+ signal hdlc_to_sca : std_logic := '1';
signal hdlc_from_sca : std_logic := '1';
- signal hdlc_clock : std_logic := '0';
+ signal hdlc_clock : std_logic := '0';
- signal tx_addr : std_logic_vector(7 downto 0) := x"00";
- signal tx_trid : std_logic_vector(7 downto 0) := x"01";
+ signal tx_addr : std_logic_vector(7 downto 0) := x"00";
+ signal tx_trid : std_logic_vector(7 downto 0) := x"01";
signal tx_ch : std_logic_vector(7 downto 0) := x"00";
- signal tx_cmd : std_logic_vector(7 downto 0) := x"02";
- signal tx_data : std_logic_vector(31 downto 0) := x"0000FF00";
-
- signal rx_received : std_logic := '0';
- signal rx_received_s0 : std_logic := '0';
- signal rx_addr : std_logic_vector(7 downto 0) := x"00";
- signal rx_ctrl : std_logic_vector(7 downto 0) := x"00";
- signal rx_trid : std_logic_vector(7 downto 0) := x"00";
+ signal tx_cmd : std_logic_vector(7 downto 0) := x"02";
+ signal tx_data : std_logic_vector(31 downto 0) := x"0000FF00";
+
+ signal rx_received : std_logic := '0';
+ signal rx_received_s0 : std_logic := '0';
+ signal rx_addr : std_logic_vector(7 downto 0) := x"00";
+ signal rx_ctrl : std_logic_vector(7 downto 0) := x"00";
+ signal rx_trid : std_logic_vector(7 downto 0) := x"00";
signal rx_ch : std_logic_vector(7 downto 0) := x"00";
- signal rx_len : std_logic_vector(7 downto 0) := x"00";
- signal rx_err : std_logic_vector(7 downto 0) := x"00";
- signal rx_data : std_logic_vector(31 downto 0) := x"00000000";
+ signal rx_len : std_logic_vector(7 downto 0) := x"00";
+ signal rx_err : std_logic_vector(7 downto 0) := x"00";
+ signal rx_data : std_logic_vector(31 downto 0) := x"00000000";
- signal GPIO_i : std_logic_vector(31 downto 0);
- signal GPIO_o : std_logic_vector(31 downto 0);
- signal GPIO_oe : std_logic_vector(31 downto 0);
+ signal GPIO_i : std_logic_vector(31 downto 0);
+ signal GPIO_o : std_logic_vector(31 downto 0);
+ signal GPIO_oe : std_logic_vector(31 downto 0);
signal SDA_out_inv_1 : std_logic_vector(15 downto 0);
-- Component declaration (SCA Model)
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
+ TESTOUT : out std_logic_vector(7 downto 0);
+
ELINK_RX : in std_logic;
ELINK_TX : out std_logic
);
architecture arch of gbt_core is
-- Clock & reset
- signal gbtsc_tx_clk_en : std_logic := '0'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled
- signal gbtsc_rx_clk_en : std_logic := '0'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled
+ signal gbtsc_tx_clk_en : std_logic := '0'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled
+ signal gbtsc_rx_clk_en : std_logic := '0'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled
-- SCA control
- signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs
- signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs
- signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs
- signal gbtsc_start_command_i : std_logic := '0'; --! Send the command set in input to the enabled SCAs
- signal gbtsc_start_reset_cmd_raw :std_logic := '0';
+ signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs
+ signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs
+ signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs
+ signal gbtsc_start_command_i : std_logic := '0'; --! Send the command set in input to the enabled SCAs
+ signal gbtsc_start_reset_cmd_raw :std_logic := '0';
signal gbtsc_start_connect_cmd_raw :std_logic := '0';
- signal gbtsc_start_command_raw :std_logic := '0';
- signal gbtsc_reset_go : std_logic := '0';
- signal gbtsc_connect_go : std_logic := '0';
- signal gbtsc_go : std_logic := '0';
+ signal gbtsc_start_command_raw :std_logic := '0';
+ signal gbtsc_reset_go : std_logic := '0';
+ signal gbtsc_connect_go : std_logic := '0';
+ signal gbtsc_go : std_logic := '0';
-- SCA command
- signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; --! Command: address field (According to the SCA manual)
- signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; --! Command: transaction ID field (According to the SCA manual)
- signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; --! Command: channel field (According to the SCA manual)
- signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; --! Command: command field (According to the SCA manual)
- signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; --! Command: data field (According to the SCA manual)
-
- signal gbtsc_rx_received_o : std_logic := '0'; --! Reply received flag (pulse)
- signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual)
- signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual)
- signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual)
- signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual)
- signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual)
- signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual)
- signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual)
- signal sync_reg : std_logic_vector(79 downto 0); -- register for syncing
+ signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; --! Command: address field (According to the SCA manual)
+ signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; --! Command: transaction ID field (According to the SCA manual)
+ signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; --! Command: channel field (According to the SCA manual)
+ signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; --! Command: command field (According to the SCA manual)
+ signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; --! Command: data field (According to the SCA manual)
+
+ signal gbtsc_rx_received_o : std_logic := '0'; --! Reply received flag (pulse)
+ signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual)
+ signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual)
+ signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual)
+ signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual)
+ signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual)
+ signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual)
+ signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual)
+ signal sync_reg : std_logic_vector(79 downto 0); -- register for syncing
-- EC line
- signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (TX) Array of bits to be mapped to the TX GBT-Frame
- signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (RX) Array of bits to be mapped to the RX GBT-Frame
+ signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (TX) Array of bits to be mapped to the TX GBT-Frame
+ signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (RX) Array of bits to be mapped to the RX GBT-Frame
+
+ signal test_out : std_logic_vector(7 downto 0) := (others => '0');
+ signal counter : unsigned(23 downto 0);
begin
);
- -- shift signals to the next high enable
- PROC_SHIFT_TX_EN : process
- variable reg_res : std_logic_vector(1 downto 0) := "00";
- variable reg_con : std_logic_vector(1 downto 0) := "00";
- variable reg_cmd : std_logic_vector(1 downto 0) := "00";
+ PROC_TOGGEL_TESTOUT_40 : process
begin
wait until rising_edge(CLK);
- reg_res := reg_res(0) & gbtsc_start_reset_cmd_raw;
- reg_con := reg_con(0) & gbtsc_start_connect_cmd_raw;
- reg_cmd := reg_cmd(0) & gbtsc_start_command_raw;
- gbtsc_start_reset_cmd_i <= (reg_res(0) and not gbtsc_tx_clk_en ) or (reg_res(1) and not gbtsc_tx_clk_en);
- gbtsc_start_connect_cmd_i <= (reg_con(0) and not gbtsc_tx_clk_en ) or (reg_con(1) and not gbtsc_tx_clk_en);
- gbtsc_start_command_i <= (reg_cmd(0) and not gbtsc_tx_clk_en ) or (reg_cmd(1) and not gbtsc_tx_clk_en);
+ if gbtsc_start_reset_cmd_i = '1' or gbtsc_start_reset_cmd_i = '0' then
+ counter(0) <= counter(0) xor gbtsc_start_reset_cmd_i;
+ counter(2) <= counter(2) xor gbtsc_start_connect_cmd_i;
+ counter(4) <= counter(4) xor gbtsc_start_command_i;
+ counter(7) <= counter(7) xor gbtsc_rx_received_o;
+ else
+ counter(0) <= '0';
+ counter(2) <= '0';
+ counter(4) <= '0';
+ counter(7) <= '0';
+ end if;
+ end process;
+
+ PROC_TOGGLE_TESTOUT_100 : process
+ begin
+ wait until rising_edge(CLK_SYS);
+ counter(1) <= counter(1) xor gbtsc_reset_go;
+ counter(3) <= counter(3) xor gbtsc_connect_go;
+ counter(5) <= counter(5) xor gbtsc_go;
end process;
+ -- 1 means off for LED
+ counter(6) <= '1';
+
+ TESTOUT <= std_logic_vector(counter(7 downto 0));
+
PROC_SYNC_REG : process
begin
end process;
- -- -- HDLC serializer
- -- hdlcser_proc: process(CLK_80)
- -- begin
- -- if rising_edge(CLK_80) then
- -- gbtsc_tx_clk_en <= gbtsc_tx_clk_en xor '1';
- -- if gbtsc_tx_clk_en = '1' then
- -- ELINK_TX <= hdlc_from_gbtsc(0);
- -- elsif gbtsc_tx_clk_en = '0' then
- -- ELINK_TX <= hdlc_from_gbtsc(1);
- -- end if;
- -- end if;
- -- end process;
-
-- HDLC serializer
hdlcser_proc: process(CLK_80)
begin
if rising_edge(CLK_80) then
+ -- if rising_edge(CLK) or CLK = '1' then
if CLK = '1' then
- ELINK_TX <= hdlc_from_gbtsc(0);
- elsif CLK = '0' then
ELINK_TX <= hdlc_from_gbtsc(1);
+ else
+ ELINK_TX <= hdlc_from_gbtsc(0);
end if;
end if;
end process;
- -- -- HDLC deserializer
- -- hdlcdes_proc: process(CLK)
- -- variable hdlc_des: std_logic_vector(1 downto 0);
- -- begin
- -- if rising_edge(CLK) then
- -- gbtsc_rx_clk_en <= gbtsc_rx_clk_en xor '1';
- -- hdlc_des := hdlc_des(0) & ELINK_RX;
- -- if gbtsc_rx_clk_en = '1' then
- -- hdlc_to_gbtsc <= hdlc_des;
- -- end if;
- -- end if;
- -- end process;
-
-- HDLC deserializer
hdlcdes_proc: process(CLK_80)
variable hdlc_des: std_logic_vector(1 downto 0);
PULSE_A_IN => gbtsc_go,
CLK_B_IN => CLK,
RESET_B_IN => RESET,
- PULSE_B_OUT => gbtsc_start_command_raw
+ PULSE_B_OUT => gbtsc_start_command_i
);
THE_RESET_SYNC : entity work.pulse_sync
PULSE_A_IN => gbtsc_reset_go,
CLK_B_IN => CLK,
RESET_B_IN => RESET,
- PULSE_B_OUT => gbtsc_start_reset_cmd_raw
+ PULSE_B_OUT => gbtsc_start_reset_cmd_i
);
THE_CONNECT_SYNC : entity work.pulse_sync
PULSE_A_IN => gbtsc_connect_go,
CLK_B_IN => CLK,
RESET_B_IN => RESET,
- PULSE_B_OUT => gbtsc_start_connect_cmd_raw
+ PULSE_B_OUT => gbtsc_start_connect_cmd_i
);
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 1 # Controlled by the compile.pl script.
-s 10
--t 51
+-t 49
-c 2
-e 2
-i 10
architecture arch of tb_gbt_core is
- signal clk : std_logic := '0';
+ signal clk_40 : std_logic := '1';
+ signal clk_80 : std_logic := '0';
signal clk_sys : std_logic := '0';
signal reset : std_logic := '0';
signal bus_rx : CTRLBUS_RX;
signal bus_tx : CTRLBUS_TX;
- -- COMPONENT TOP_core_sca_tri
- -- PORT (
- -- -- Elink HDLC
- -- link_clk_1 : in STD_LOGIC;
- -- link_clk_aux_1 : in STD_LOGIC;
- -- disable_aux_1 : in STD_LOGIC;
- -- tx_sd_1 : out STD_LOGIC;
- -- tx_sd_aux_1 : out STD_LOGIC;
- -- rx_sd_1 : in STD_LOGIC;
- -- rx_sd_aux_1 : in STD_LOGIC;
- -- tx_adr_1 : in STD_LOGIC_VECTOR(7 downto 0);
- -- CRE_1 : out STD_LOGIC_VECTOR(7 downto 0);
- -- active_aux_1 : out STD_LOGIC;
-
- -- -- JTAG
- -- JTAG_TCK_pad_o_1 : out STD_LOGIC;
- -- JTAG_TMS_pad_o_1 : out STD_LOGIC;
- -- JTAG_TDO_pad_o_1 : out STD_LOGIC;
- -- JTAG_TDI_pad_i_1 : in STD_LOGIC;
- -- JTAG_RST_pad_o_1 : out STD_LOGIC;
-
- -- -- SPI
- -- SPI_sclk_pad_o_1 : out STD_LOGIC;
- -- SPI_ss_pad_o_1 : out STD_LOGIC_VECTOR(7 downto 0);
- -- SPI_miso_pad_i_1 : in STD_LOGIC;
- -- SPI_mosi_pad_o_1 : out STD_LOGIC;
-
- -- -- GPIO
- -- GPIO_ext_pad_o_1 : out STD_LOGIC_VECTOR(31 downto 0);
- -- GPIO_ext_padOE_o_1 : out STD_LOGIC_VECTOR(31 downto 0);
- -- GPIO_clk_pad_i_1 : in STD_LOGIC;
- -- GPIO_ext_pad_i_1 : in STD_LOGIC_VECTOR(31 downto 0);
-
- -- -- I2C
- -- SCL_1 : out STD_LOGIC_VECTOR(15 downto 0);
- -- SCLEN_1 : out STD_LOGIC_VECTOR(15 downto 0);
- -- SDA_in_1 : in STD_LOGIC_VECTOR(15 downto 0);
- -- SDA_out_inv_1 : out STD_LOGIC_VECTOR(15 downto 0);
-
- -- -- ADC
- -- ADC_wb_RES_1 : out STD_LOGIC;
- -- ADC_wb_CLK_1 : out STD_LOGIC;
- -- ADC_wb_SEL_1 : out STD_LOGIC;
- -- ADC_wb_WE_1 : out STD_LOGIC;
- -- ADC_wb_STB_1 : out STD_LOGIC;
- -- ADC_wb_CYC_1 : out STD_LOGIC;
- -- ADC_wb_ADR_1 : out STD_LOGIC_VECTOR(3 downto 0);
- -- ADC_wb_DATi_1 : out STD_LOGIC_VECTOR(31 downto 0);
- -- ADC_wb_DATo_1 : in STD_LOGIC_VECTOR(31 downto 0);
- -- ADC_wb_ACK_1 : in STD_LOGIC;
- -- ADC_wb_INT_1 : in STD_LOGIC;
-
- -- -- DAC
- -- anaDAC_A_1 : out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_B_1 : out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_C_1 : out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_D_1 : out STD_LOGIC_VECTOR(7 downto 0);
-
- -- -- Reset Logic
- -- PowerUpReset_1 : in STD_LOGIC;
- -- PromtReset_1 : in STD_LOGIC;
- -- Reset_BG_1 : out STD_LOGIC;
-
- -- -- Auxiliary Port I2C
- -- auxPort_TestEn_1 : in STD_LOGIC;
- -- auxPort_SCL_1 : in STD_LOGIC;
- -- auxPort_SDA_in_1 : in STD_LOGIC;
- -- auxPort_SDA_out_1 : out STD_LOGIC;
- -- auxPort_SDA_oEn_1 : out STD_LOGIC
- -- );
- -- END COMPONENT;
-
- -- signal tdo_s : stD_logic;
-
-
- begin
-
- SCAModel: entity work.TOP_core_sca_tri
- port map (
- -- -- Elink HDLC
- -- link_clk_1 => hdlc_clock , --: in STD_LOGIC;
- -- link_clk_aux_1 => '0' , --: in STD_LOGIC;
- -- disable_aux_1 => '1' , --: in STD_LOGIC;
- -- tx_sd_1 => hdlc_from_sca , --: out STD_LOGIC;
- -- tx_sd_aux_1 => open , --: out STD_LOGIC;
- -- rx_sd_1 => hdlc_to_sca , --: in STD_LOGIC;
- -- rx_sd_aux_1 => '0' , --: in STD_LOGIC;
- -- tx_adr_1 => x"00" , --: in STD_LOGIC_VECTOR(7 downto 0);
- -- CRE_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
- -- active_aux_1 => open , --: out STD_LOGIC;
-
- -- -- JTAG
- -- JTAG_TCK_pad_o_1 => JTAG_TCK , --: out STD_LOGIC;
- -- JTAG_TMS_pad_o_1 => JTAG_TMS , --: out STD_LOGIC;
- -- JTAG_TDO_pad_o_1 => tdo_s , --: out STD_LOGIC;
- -- JTAG_TDI_pad_i_1 => tdo_s , --: in STD_LOGIC;
- -- JTAG_RST_pad_o_1 => open , --: out STD_LOGIC;
-
- -- -- SPI
- -- SPI_sclk_pad_o_1 => open , --: out STD_LOGIC;
- -- SPI_ss_pad_o_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
- -- SPI_miso_pad_i_1 => '0' , --: in STD_LOGIC;
- -- SPI_mosi_pad_o_1 => open , --: out STD_LOGIC;
-
- -- -- GPIO
- -- GPIO_ext_pad_o_1 => GPIO_o , --: out STD_LOGIC_VECTOR(31 downto 0);
- -- GPIO_ext_padOE_o_1 => GPIO_oe , --: out STD_LOGIC_VECTOR(31 downto 0);
- -- GPIO_clk_pad_i_1 => '0' , --: in STD_LOGIC;
- -- GPIO_ext_pad_i_1 => GPIO_i , --: in STD_LOGIC_VECTOR(31 downto 0);
-
- -- -- I2C
- -- SCL_1 => SCL_1 , --: out STD_LOGIC_VECTOR(15 downto 0);
- -- SCLEN_1 => SCLEN_1 , --: out STD_LOGIC_VECTOR(15 downto 0);
- -- SDA_in_1 => SDA_in_1 , --: in STD_LOGIC_VECTOR(15 downto 0);
- -- SDA_out_inv_1 => SDA_out_inv_1 , --: out STD_LOGIC_VECTOR(15 downto 0);
-
- -- -- ADC
- -- ADC_wb_RES_1 => open , --: out STD_LOGIC;
- -- ADC_wb_CLK_1 => open , --: out STD_LOGIC;
- -- ADC_wb_SEL_1 => open , --: out STD_LOGIC;
- -- ADC_wb_WE_1 => open , --: out STD_LOGIC;
- -- ADC_wb_STB_1 => open , --: out STD_LOGIC;
- -- ADC_wb_CYC_1 => open , --: out STD_LOGIC;
- -- ADC_wb_ADR_1 => open , --: out STD_LOGIC_VECTOR(3 downto 0);
- -- ADC_wb_DATi_1 => open , --: out STD_LOGIC_VECTOR(31 downto 0);
- -- ADC_wb_DATo_1 => (others => '0') , --: in STD_LOGIC_VECTOR(31 downto 0);
- -- ADC_wb_ACK_1 => '0' , --: in STD_LOGIC;
- -- ADC_wb_INT_1 => '0' , --: in STD_LOGIC;
-
- -- -- DAC
- -- anaDAC_A_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_B_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_C_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
- -- anaDAC_D_1 => open , --: out STD_LOGIC_VECTOR(7 downto 0);
-
- -- -- Reset Logic
- -- PowerUpReset_1 => powerup_reset , --: in STD_LOGIC;
- -- PromtReset_1 => prompt_reset , --: in STD_LOGIC;
- -- Reset_BG_1 => open , --: out STD_LOGIC;
-
- -- -- Auxiliary Port I2C
- -- auxPort_TestEn_1 => '0' , --: in STD_LOGIC;
- -- auxPort_SCL_1 => '0' , --: in STD_LOGIC;
- -- auxPort_SDA_in_1 => '0' , --: in STD_LOGIC;
- -- auxPort_SDA_out_1 => open , --: out STD_LOGIC;
- -- auxPort_SDA_oEn_1 => open --: out STD_LOGIC
+ COMPONENT TOP_core_sca_tri
+ PORT (
+ -- Elink HDLC
+ link_clk_1 : in STD_LOGIC;
+ link_clk_aux_1 : in STD_LOGIC;
+ disable_aux_1 : in STD_LOGIC;
+ tx_sd_1 : out STD_LOGIC;
+ tx_sd_aux_1 : out STD_LOGIC;
+ rx_sd_1 : in STD_LOGIC;
+ rx_sd_aux_1 : in STD_LOGIC;
+ tx_adr_1 : in STD_LOGIC_VECTOR(7 downto 0);
+ CRE_1 : out STD_LOGIC_VECTOR(7 downto 0);
+ active_aux_1 : out STD_LOGIC;
+
+ -- JTAG
+ JTAG_TCK_pad_o_1 : out STD_LOGIC;
+ JTAG_TMS_pad_o_1 : out STD_LOGIC;
+ JTAG_TDO_pad_o_1 : out STD_LOGIC;
+ JTAG_TDI_pad_i_1 : in STD_LOGIC;
+ JTAG_RST_pad_o_1 : out STD_LOGIC;
+
+ -- SPI
+ SPI_sclk_pad_o_1 : out STD_LOGIC;
+ SPI_ss_pad_o_1 : out STD_LOGIC_VECTOR(7 downto 0);
+ SPI_miso_pad_i_1 : in STD_LOGIC;
+ SPI_mosi_pad_o_1 : out STD_LOGIC;
+
+ -- GPIO
+ GPIO_ext_pad_o_1 : out STD_LOGIC_VECTOR(31 downto 0);
+ GPIO_ext_padOE_o_1 : out STD_LOGIC_VECTOR(31 downto 0);
+ GPIO_clk_pad_i_1 : in STD_LOGIC;
+ GPIO_ext_pad_i_1 : in STD_LOGIC_VECTOR(31 downto 0);
+
+ -- I2C
+ SCL_1 : out STD_LOGIC_VECTOR(15 downto 0);
+ SCLEN_1 : out STD_LOGIC_VECTOR(15 downto 0);
+ SDA_in_1 : in STD_LOGIC_VECTOR(15 downto 0);
+ SDA_out_inv_1 : out STD_LOGIC_VECTOR(15 downto 0);
+
+ -- ADC
+ ADC_wb_RES_1 : out STD_LOGIC;
+ ADC_wb_CLK_1 : out STD_LOGIC;
+ ADC_wb_SEL_1 : out STD_LOGIC;
+ ADC_wb_WE_1 : out STD_LOGIC;
+ ADC_wb_STB_1 : out STD_LOGIC;
+ ADC_wb_CYC_1 : out STD_LOGIC;
+ ADC_wb_ADR_1 : out STD_LOGIC_VECTOR(3 downto 0);
+ ADC_wb_DATi_1 : out STD_LOGIC_VECTOR(31 downto 0);
+ ADC_wb_DATo_1 : in STD_LOGIC_VECTOR(31 downto 0);
+ ADC_wb_ACK_1 : in STD_LOGIC;
+ ADC_wb_INT_1 : in STD_LOGIC;
+
+ -- DAC
+ anaDAC_A_1 : out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_B_1 : out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_C_1 : out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_D_1 : out STD_LOGIC_VECTOR(7 downto 0);
+
+ -- Reset Logic
+ PowerUpReset_1 : in STD_LOGIC;
+ PromtReset_1 : in STD_LOGIC;
+ Reset_BG_1 : out STD_LOGIC;
+
+ -- Auxiliary Port I2C
+ auxPort_TestEn_1 : in STD_LOGIC;
+ auxPort_SCL_1 : in STD_LOGIC;
+ auxPort_SDA_in_1 : in STD_LOGIC;
+ auxPort_SDA_out_1 : out STD_LOGIC;
+ auxPort_SDA_oEn_1 : out STD_LOGIC
+ );
+ END COMPONENT;
+
+ signal hdlc_to_sca : std_logic := '1';
+ signal hdlc_from_sca : std_logic := '1';
+
+begin
+
+ SCAModel: TOP_core_sca_tri
+ port map (
+ -- Elink HDLC
+ link_clk_1 => clk_40, --: in STD_LOGIC;
+ link_clk_aux_1 => '0', --: in STD_LOGIC;
+ disable_aux_1 => '1', --: in STD_LOGIC;
+ tx_sd_1 => hdlc_from_sca, --: out std_logic;
+ tx_sd_aux_1 => open, --: out STD_LOGIC;
+ rx_sd_1 => hdlc_to_sca, --: in STD_LOGIC;
+ rx_sd_aux_1 => '0', --: in STD_LOGIC;
+ tx_adr_1 => x"00", --: in STD_LOGIC_VECTOR(7 downto 0);
+ CRE_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+ active_aux_1 => open, --: out STD_LOGIC;
+
+ -- JTAG
+ JTAG_TCK_pad_o_1 => open, --: out STD_LOGIC;
+ JTAG_TMS_pad_o_1 => open, --: out STD_LOGIC;
+ JTAG_TDO_pad_o_1 => open, --: out STD_LOGIC;
+ JTAG_TDI_pad_i_1 => '0', --: in STD_LOGIC;
+ JTAG_RST_pad_o_1 => open, --: out STD_LOGIC;
+
+ -- SPI
+ SPI_sclk_pad_o_1 => open, --: out STD_LOGIC;
+ SPI_ss_pad_o_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+ SPI_miso_pad_i_1 => '0', --: in STD_LOGIC;
+ SPI_mosi_pad_o_1 => open, --: out STD_LOGIC;
+
+ -- GPIO
+ GPIO_ext_pad_o_1 => open, --: out STD_LOGIC_VECTOR(31 downto 0);
+ GPIO_ext_padOE_o_1 => open, --: out STD_LOGIC_VECTOR(31 downto 0);
+ GPIO_clk_pad_i_1 => '0', --: in STD_LOGIC;
+ GPIO_ext_pad_i_1 => (others => '0'), --: in STD_LOGIC_VECTOR(31 downto 0);
+
+ -- I2C
+ SCL_1 => open, --: out STD_LOGIC_VECTOR(15 downto 0);
+ SCLEN_1 => open, --: out STD_LOGIC_VECTOR(15 downto 0);
+ SDA_in_1 => (others => '0'), --: in STD_LOGIC_VECTOR(15 downto 0);
+ SDA_out_inv_1 => open, --: out STD_LOGIC_VECTOR(15 downto 0);
+
+ -- ADC
+ ADC_wb_RES_1 => open, --: out STD_LOGIC;
+ ADC_wb_CLK_1 => open, --: out STD_LOGIC;
+ ADC_wb_SEL_1 => open, --: out STD_LOGIC;
+ ADC_wb_WE_1 => open, --: out STD_LOGIC;
+ ADC_wb_STB_1 => open, --: out STD_LOGIC;
+ ADC_wb_CYC_1 => open, --: out STD_LOGIC;
+ ADC_wb_ADR_1 => open, --: out STD_LOGIC_VECTOR(3 downto 0);
+ ADC_wb_DATi_1 => open, --: out STD_LOGIC_VECTOR(31 downto 0);
+ ADC_wb_DATo_1 => (others => '0'), --: in STD_LOGIC_VECTOR(31 downto 0);
+ ADC_wb_ACK_1 => '0', --: in STD_LOGIC;
+ ADC_wb_INT_1 => '0', --: in STD_LOGIC;
+
+ -- DAC
+ anaDAC_A_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_B_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_C_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+ anaDAC_D_1 => open, --: out STD_LOGIC_VECTOR(7 downto 0);
+
+ -- Reset Logic
+ PowerUpReset_1 => reset, --: in STD_LOGIC;
+ PromtReset_1 => reset, --: in STD_LOGIC;
+ Reset_BG_1 => open, --: out STD_LOGIC;
+
+ -- Auxiliary Port I2C
+ auxPort_TestEn_1 => '0', --: in STD_LOGIC;
+ auxPort_SCL_1 => '0', --: in STD_LOGIC;
+ auxPort_SDA_in_1 => '0', --: in STD_LOGIC;
+ auxPort_SDA_out_1 => open, --: out STD_LOGIC;
+ auxPort_SDA_oEn_1 => open --: out STD_LOGIC
);
THE_GBT_CORE : entity work.gbt_core
port map(
CLK_SYS => clk_sys,
- CLK => clk,
+ CLK => clk_40,
+ CLK_80 => clk_80,
RESET => reset,
BUS_RX => bus_rx,
BUS_TX => bus_tx,
- ELINK_RX => '0',
- ELINK_TX => open
-);
+ ELINK_RX => hdlc_from_sca,
+ ELINK_TX => hdlc_to_sca
+ );
- clk <= not(clk) after 6.25 ns;
+ clk_40 <= not(clk_40) after 12.5 ns;
+ clk_80 <= not(clk_80) after 6.25 ns;
clk_sys <= not(clk_sys) after 5 ns;
end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity tb_gbt_core_slim is
+end entity;
+
+architecture arch of tb_gbt_core_slim is
+
+ signal clk_40 : std_logic := '0';
+ signal clk_80 : std_logic := '0';
+ signal clk_sys : std_logic := '0';
+ signal reset : std_logic := '0';
+ signal bus_rx : CTRLBUS_RX;
+ signal bus_tx : CTRLBUS_TX;
+
+ begin
+
+ THE_GBT_CORE : entity work.gbt_core
+ port map(
+ CLK_SYS => clk_sys,
+ CLK => clk_40,
+ CLK_80 => clk_80,
+ RESET => reset,
+
+ BUS_RX => bus_rx,
+ BUS_TX => bus_tx,
+
+ ELINK_RX => '0',
+ ELINK_TX => open
+);
+
+ clk_40 <= not(clk_40) after 12.5 ns;
+ clk_80 <= not(clk_80) after 6.25 ns;
+ clk_sys <= not(clk_sys) after 5 ns;
+
+end architecture;
../code/Testbench/SCA-model/SPI_channel.v
../code/Testbench/SCA-model/spi_defines.v
../code/Testbench/SCA-model/timescale.v
- ../code/Testbench/SCA-model/Table_Commande.v
../code/Testbench/SCA-model/TOP_core_sca_tri.v
../code/GBT-SC/SCA/sca_pkg.vhd
../code/GBT-SC/SCA/sca_tx.vhd
proc simulate {{restart "restart"}} {
if { $restart == "start" } {
- eval vsim work.tb_gbt_core -novopt
+ eval vsim work.tb_gbt_core -t 10ps -novopt
reset_waves 0
}
wave zoom full
send_reset
- # send_reset_go
- # send_connect_go
+ send_reset_bus
+ send_connect_bus
+ send_command_bus
}
proc reset_waves { verbosity } {
delete wave *
- add wave -noupdate -divider -height 20 "Reset, Clock, Enable"
- add wave -label "TB Clock 80" sim:/tb_gbt_core/clk
- add wave -label "TB Clock 100" sim:/tb_gbt_core/clk_sys
- add wave -label "TB Reset" sim:/tb_gbt_core/reset
-
- add wave -label "Core Clock TX EN" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_clk_en
- # add wave -label "Core Clock RX EN" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_clk_en
+ add wave -noupdate -divider -height 20 "Reset and Clock"
+ add wave -label "Clock 100" sim:/tb_gbt_core/clk_sys
+ add wave -label "Clock 80" sim:/tb_gbt_core/clk_80
+ add wave -label "Clock 40" sim:/tb_gbt_core/clk_40
+ add wave -label "Reset" sim:/tb_gbt_core/reset
+ add wave -label "Test" sim:/tb_gbt_core/THE_GBT_CORE/test_out
add wave -noupdate -divider -height 20 "HDLC"
- add wave -label "Core From SCA" sim:/tb_gbt_core/THE_GBT_CORE/ELINK_TX
- add wave -label "Core To SCA" sim:/tb_gbt_core/THE_GBT_CORE/ELINK_RX
-
- add wave -noupdate -divider -height 20 "Bus"
- add wave -label "TB BUS_RX" sim:/tb_gbt_core/bus_rx
- add wave -label "TB BUS_TX" sim:/tb_gbt_core/bus_tx
-
- add wave -noupdate -divider -height 20 "Control"
- # add wave -label "Core SCA Enable" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_sca_enable_i
- add wave -label "Core Start Reset CMD" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_reset_cmd_i
- # add wave -label "Core Start Reset GO" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go
- add wave -label "Core Start Connect CMD" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_connect_cmd_i
- # add wave -label "Core Start Connect GO" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go
- add wave -label "Core Start Command" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_command_i
- # add wave -label "Core Start Command GO" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_go
+ add wave -label "To SCA" sim:/tb_gbt_core/hdlc_to_sca
+ add wave -label "From SCA" sim:/tb_gbt_core/hdlc_from_sca
+
+ add wave -noupdate -divider -height 20 "BUS"
+ add wave -label "BUS RX" sim:/tb_gbt_core/bus_rx
+ add wave -label "BUS TX" sim:/tb_gbt_core/bus_tx
+
+ add wave -noupdate -divider -height 20 "Connect"
+ add wave -label "Start Transaction" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_command_i
+ add wave -label "Start Reset" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_reset_cmd_i
+ add wave -label "Start Connect" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_connect_cmd_i
add wave -noupdate -divider -height 20 "Command"
- add wave -label "Core Address" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_address_i
- add wave -label "Core Trans ID" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_transID_i
- add wave -label "Core Channel" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_channel_i
- add wave -label "Core Command" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_command_i
- add wave -label "Core Data" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_data_i
+ add wave -label "Address" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_address_i
+ add wave -label "Transaction Id" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_transID_i
+ add wave -label "Channel" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_channel_i
+ add wave -label "Command" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_command_i
+ add wave -label "Data" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_data_i
+
+ add wave -noupdate -divider -height 20 "Reply"
+ add wave -label "Received" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_received_o
+ add wave -label "Address" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_address_o
+ add wave -label "Transaction Id" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_transID_o
+ add wave -label "Channel" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_channel_o
+ add wave -label "Length" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_len_o
+ add wave -label "Error" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_error_o
+ add wave -label "Data" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_data_o
+ add wave -label "Control" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_control_o
}
}
-proc send_reset_go {} {
-
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 0 0
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 1 10 ns
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 0 20 ns
-
- run 2500ns
- wave zoom full
-}
-
proc send_reset_bus {} {
force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
set data 0x00000300
set addr 0x0000
- force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns
- force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 505 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 505 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 1 505 ns
set data 0x00000000
set addr 0x0000
- force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns
- force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 515 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 515 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 1 515 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 0 520 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 0 525 ns
- run 2500ns
+ run 1500ns
wave zoom full
}
-proc send_connect_go {} {
-
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 0 0
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 1 500 ns
- force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 0 1000 ns
-
- run 2500ns
- wave zoom full
-}
-
-
proc send_connect_bus {} {
force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
force -freeze sim:/tb_gbt_core/bus_rx.read 0 0
+ # set data 0x00000500
set data 0x00000500
set addr 0x0000
- force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns
- force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 505 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 505 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 1 505 ns
set data 0x00000000
set addr 0x0000
- force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns
- force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 515 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 515 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 1 515 ns
- force -freeze sim:/tb_gbt_core/bus_rx.write 0 520 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.write 0 525 ns
- run 2500ns
+ run 1500ns
wave zoom full
}
force -freeze sim:/tb_gbt_core/bus_rx.write 0 530 ns
# run -all
- run 2500ns
+ run 5000ns
+ wave zoom full
+}
+
+
+proc read_bus {} {
+
+ force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
+ force -freeze sim:/tb_gbt_core/bus_rx.read 0 0
+
+ set addr 0x0001
+ force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 300 ns
+ force -freeze sim:/tb_gbt_core/bus_rx.read 1 300 ns
+
+ force -freeze sim:/tb_gbt_core/bus_rx.read 0 330 ns
+
+ # run -all
+ run 2000ns
wave zoom full
}
RJ : inout std_logic_vector(3 downto 0);\r
H1 : inout std_logic_vector(4 downto 0);\r
H2 : inout std_logic_vector(4 downto 0);\r
+ H3_2 : in std_logic;\r
H3 : inout std_logic_vector(4 downto 0);\r
H4 : inout std_logic_vector(4 downto 0);\r
H5 : inout std_logic_vector(3 downto 0);\r
signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
- signal i2c_go_100, i2c_go : std_logic;\r
- signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
- signal counter : unsigned(23 downto 0);\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ signal counter : unsigned(23 downto 0);\r
\r
--signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
--signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
--signal fwd_length : std_logic_vector(15 downto 0);\r
--signal fwd_do_send : std_logic;\r
\r
+ signal h3_2_buf : std_logic;\r
begin\r
\r
trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
PORT_NUMBER => 6,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0),\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"d600", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 4, 6 => 8, 7 => 8, others => 0),\r
PORT_MASK_ENABLE => 1\r
)\r
port map(\r
LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
- LED <= x"FF";\r
+ -- LED <= x"FF";\r
LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
BUS_RX => busgbtcore_rx,\r
BUS_TX => busgbtcore_tx,\r
\r
- ELINK_RX => H3(2),\r
+ TESTOUT => LED,\r
+\r
+ ELINK_RX => H3_2,\r
ELINK_TX => H3(0)\r
);\r
\r
- H3(3) <= clk_80;\r
+ H3(3) <= clk_40;\r
\r
---------------------------------------------------------------------------\r
-- Input stage\r
jspc29 / trb5sc.git / commitdiff