remove some outdated information

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index a747bd808e21757ca562a5df89cc5ef2415aaa62..2c4c3526bab86f769ed0f2db4982b72c57f0ea1f 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -84,9 +84,8 @@ Typically only the first programming of a board is done with a JTAG cable, all l
 
 First, the name of the design has to contain a certain sub-string:
 \begin{description}
- \item[trb3\_central or trb3\_fpga5] if the design is targeted to the central FPGA
- \item[trb3\_periph or trb3\_fpga1234] if the design is targeted to either of the peripheral FPGA
- \item[trb3\_fpgaN] were N is a number between 1 and 4 if the design should be loaded to a special FPGA only
+ \item[trb3\_central] if the design is targeted to the central FPGA
+ \item[trb3\_periph] if the design is targeted to either of the peripheral FPGA
 \end{description}
 Second, the upper 16 Bit of the Hardware Version register as described below is checked.
 
@@ -105,12 +104,8 @@ The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (reg
 The upper 16 Bit are used by the software to identify the hardware before programming the Flash to prevent loading invalid designs and 
 have to contain one of the following values. The last digit should be used to denote the hardware revision.
 \begin{description*}
- \item[9000] design for the central FPGA
- \item[9100] design for either of the peripheral FPGAs
- \item[9110] design for FPGA 1 only
- \item[9120] design for FPGA 2 only
- \item[9130] design for FPGA 3 only
- \item[9140] design for FPGA 4 only
+ \item[9000] design for Trb3 central FPGA
+ \item[9100] design for Trb3 peripheral FPGAs
  \item[9200] design for CBM Rich
  \item[9300] design for CBM Tof
  \item[9500] design for Trb3sc
@@ -186,7 +181,7 @@ All network addresses are of the form ABBC, where:
 \item BB is a number identifying the TRB in the full system. BB is equal on all 5 FPGA of one board.
 \end{itemize*}
 
-The FPGA with the CTS has address C000. For data unpacking schemes see also \ref{Data_Unpacking}.
+The FPGA with the CTS has an address starting with 'C'. For data unpacking schemes see also \ref{Data_Unpacking}.
 
 
 All boards of a given type are accessible by a broadcast address at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint: