--- /dev/null
+{
+ "name": "Padiwa"
+, "files": [ { "git": 1 } ]
+}
--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME = "padiwa_pulser"; #Name of top-level entity
+my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="MACHXO2";
+my $DEVICENAME="LCMXO2-4000HC";
+my $PACKAGE="FTBGA256";
+my $SPEEDGRADE="6";
+
+
+#create full lpf file
+system("cp ../pinout/panda_dirc_wasa1.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
+ print "\n\n";
+ exit 129;
+ }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+execute($c);
+# IOR IO Timing Report
+# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+# execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+# execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -jedec $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 1
+-t 11
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=0:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
--- /dev/null
+
+#project files
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/2.2_x64/cae_library/synthesis/vhdl/machxo2.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../source/spi_slave.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../source/pwm.vhd"
+add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
+add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
+add_file -vhdl -lib work "../source/ffarray.vhd"
+
+
+add_file -vhdl -lib work "../cores/oddr16.vhd"
+add_file -vhdl -lib work "../cores/flash.vhd"
+add_file -vhdl -lib work "../cores/flashram.vhd"
+add_file -vhdl -lib work "../cores/pll.vhd"
+add_file -verilog -lib work "../cores/efb_define_def.v"
+add_file -verilog -lib work "../cores/UFM_WB.v"
+
+
+add_file -vhdl -lib work "padiwa_pulser.vhd"
+
+
+#implementation: "padiwa_pulser"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std sysv
+set_option -project_relative_includes 1
+
+#device options
+set_option -technology MACHXO2
+set_option -part LCMXO2_4000HC
+set_option -package FTG256C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr no
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -update_models_cp 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+set_option -top_module "padiwa_pulser"
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "workdir/padiwa_pulser.edf"
+impl -active "workdir"
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.version.all;
+
+library machxo2;
+use machxo2.all;
+
+
+entity padiwa_pulser is
+ port(
+ CON : out std_logic_vector(16 downto 1); --Output for pulser signals
+ SPARE_LINE : inout std_logic_vector(3 downto 0); --connection to PC
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ TEST_LINE : out std_logic_vector(15 downto 0) --connection for debugging
+ );
+end entity;
+
+architecture padiwa_pulser_arch of padiwa_pulser is
+
+component OSCH
+-- synthesis translate_off
+ generic (NOM_FREQ: string := "133.00");
+-- synthesis translate_on
+ port (
+ STDBY :IN std_logic;
+ OSC :OUT std_logic;
+ SEDSTDBY :OUT std_logic
+ );
+end component;
+
+attribute NOM_FREQ : string;
+attribute NOM_FREQ of clk_source : label is "133.00";
+signal clk_i : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock
+---------------------------------------------------------------------------
+clk_source: OSCH
+-- synthesis translate_off
+ generic map ( NOM_FREQ => "133.00" )
+-- synthesis translate_on
+ port map (
+ STDBY => '0',
+ OSC => clk_i,
+ SEDSTDBY => open
+ );
+
+
+
+SPARE_LINE(0) <= 'Z'; --TX from PC
+SPARE_LINE(1) <= 'Z'; --C1 spare
+SPARE_LINE(2) <= SPARE_LINE(0) when rising_edge(clk_i); --RX to PC
+SPARE_LINE(3) <= 'Z'; --C2 spare
+
+
+LED_GREEN <= '0';
+LED_ORANGE <= '1';
+LED_RED <= '0';
+LED_YELLOW <= '1';
+
+end architecture;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity uart_rec is
+-- generic(
+-- CLK_DIV : integer
+-- );
+ port(
+ CLK_DIV : in integer;
+ CLK : in std_logic;
+ RST : in std_logic;
+ RX : in std_logic;
+
+ DATA_OUT : out std_logic_vector(7 downto 0);
+ DATA_WAITING : out std_logic;
+ DEBUG : out std_logic_vector(3 downto 0)
+ );
+end entity;
+
+
+
+architecture uart_rec_arch of uart_rec is
+
+signal clk_div_counter: unsigned(15 downto 0) := x"0000";
+signal symbol_pulse : std_logic := '0';
+signal symbol_counter: unsigned(3 downto 0) := x"0";
+
+type state_type is (idle,receiving,update_parallel_output);
+signal state: state_type := idle;
+
+-- MSB is the stopbit, LSB is the start bit, both are never changed
+signal rx_shift_register: std_logic_vector(9 downto 0);
+signal symbol : std_logic := '1';
+signal data_waiting_sig: std_logic := '0';
+signal current_data_out: std_logic_vector(7 downto 0) := "00000000";
+signal symbol_start_pulse : std_logic := '0'; -- just debug
+signal rst_clk_div_counter : std_logic;
+
+
+begin
+----------------------------
+-- debug
+----------------------------
+
+DEBUG(0) <= symbol_start_pulse;
+DEBUG(1) <= symbol_pulse;
+DEBUG(2) <= data_waiting_sig;
+DEBUG(3) <= '0';
+
+----------------------------
+-- Inputs
+----------------------------
+ sync_input : process begin
+ wait until rising_edge(CLK);
+ symbol <= RX;
+ end process;
+
+----------------------------
+-- Outputs
+----------------------------
+ sync_output : process begin
+ wait until rising_edge(CLK);
+ DATA_WAITING <= data_waiting_sig;
+ DATA_OUT <= current_data_out;
+ end process;
+
+----------------------------
+-- Generate Serial Clock
+----------------------------
+ clock_division : process begin
+ wait until rising_edge(CLK);
+ -- scaling down the main clock to the desired baudrate
+ if clk_div_counter < CLK_DIV-1 then
+ clk_div_counter <= clk_div_counter + 1;
+ else
+ clk_div_counter <= x"0000";
+ end if;
+ -- generates symbol_pulse, a signal that has 1 clock cycle pulses, one symbol duration period apart
+ -- in contrast to the transceiver module, the symbol pulse is generated in the middle of the
+ -- symbol period
+ -- if clk_div_counter = '0' & CLK_DIV(15 downto 1) then -- CLK_DIV/2 by >> (right shifting)
+ if clk_div_counter = CLK_DIV/2 then
+ symbol_pulse <= '1';
+ else
+ symbol_pulse <= '0';
+ end if;
+
+ if clk_div_counter = x"0000" then
+ symbol_start_pulse <= '1';
+ else
+ symbol_start_pulse <= '0';
+ end if;
+ if (RST or rst_clk_div_counter) = '1' then
+ clk_div_counter <= x"0000";
+ end if;
+
+ end process;
+
+----------------------------
+-- State Machine of the Receiver
+----------------------------
+ state_machine : process begin
+ wait until rising_edge(CLK);
+ data_waiting_sig <= '0';
+ rst_clk_div_counter <= '0';
+
+ -- state machine rules:
+ case state is
+ when idle =>
+
+ if symbol = '0' then -- the start bit comes!
+ state <= receiving;
+ -- restart the divcounter
+ -- clk_div_counter <= x"0000";
+ rst_clk_div_counter<= '1';
+ symbol_counter <= x"0";
+
+ end if;
+
+ when receiving =>
+ if symbol_pulse = '1' then
+ if symbol_counter <= 9 then -- reception process
+ rx_shift_register(to_integer(symbol_counter)) <= symbol;
+ symbol_counter <= symbol_counter + 1;
+ end if;
+ if symbol_counter = 9 then
+ state <= update_parallel_output;
+ end if;
+
+
+ end if;
+ when update_parallel_output =>
+ state <= idle;
+ -- check start and stop bit consistency
+ -- (checking the start bit again seems a little obsolete)
+ -- only if bit was received correctly output the data!
+ if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then
+ current_data_out <= rx_shift_register(8 downto 1);
+ data_waiting_sig <= '1';
+ end if;
+
+ end case;
+
+ -- reset clock divider counters when reset signal is on
+ if RST = '1' then
+ symbol_counter <= x"0";
+ data_waiting_sig <= '0';
+ state <= idle;
+ end if;
+
+ end process;
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity uart_trans is
+-- generic(
+-- CLK_DIV : integer
+-- );
+ port(
+ CLK_DIV : in integer;
+ CLK : in std_logic;
+ RST : in std_logic;
+
+ DATA_IN : in std_logic_vector(7 downto 0);
+ SEND : in std_logic;
+ READY : out std_logic;
+
+ TX : out std_logic;
+ DEBUG : out std_logic_vector(3 downto 0)
+
+ );
+end entity;
+
+
+
+architecture uart_trans_arch of uart_trans is
+
+
+
+signal clk_div_counter: unsigned(15 downto 0) := x"0000";
+signal symbol_start_pulse : std_logic := '0';
+signal symbol_counter: unsigned(3 downto 0) := x"0";
+
+type state_type is (idle,transmitting);
+signal state: state_type := idle;
+
+-- MSB is the stopbit, LSB is the start bit, both are never changed
+signal tx_shift_register: std_logic_vector(9 downto 0) := "1000000000";
+signal symbol: std_logic := '1';
+signal ready_sig: std_logic := '1';
+signal rst_clk_div_counter : std_logic;
+
+
+begin
+----------------------------
+-- debug
+----------------------------
+
+DEBUG(0) <= symbol_start_pulse;
+DEBUG(1) <= '0';
+DEBUG(2) <= ready_sig;
+DEBUG(3) <= '0';
+
+----------------------------
+-- Inputs
+----------------------------
+-- sync_input : process begin
+-- wait until rising_edge(CLK);
+-- synced_send <= SEND;
+-- end process;
+-- hard wired stuff
+
+----------------------------
+-- Outputs
+----------------------------
+ sync_output : process begin
+ wait until rising_edge(CLK);
+ TX <= symbol;
+ READY <= ready_sig;
+ end process;
+
+----------------------------
+-- Generate Serial Clock
+----------------------------
+ clock_division : process begin
+ wait until rising_edge(CLK);
+ -- scaling down the main clock to the desired baudrate
+ if clk_div_counter < CLK_DIV-1 then
+ clk_div_counter <= clk_div_counter + 1;
+ else
+ clk_div_counter <= x"0000";
+ end if;
+
+
+ if clk_div_counter = x"0000" then
+ symbol_start_pulse <= '1';
+ else
+ symbol_start_pulse <= '0';
+ end if;
+ if (RST or rst_clk_div_counter) = '1' then
+ clk_div_counter <= x"0000";
+ end if;
+
+ end process;
+
+----------------------------
+-- State Machine of the Transmitter
+----------------------------
+
+ state_machine : process begin
+ wait until rising_edge(CLK);
+ -- state machine rules:
+ rst_clk_div_counter <= '0';
+
+ case state is
+ when idle =>
+ if SEND = '1' then
+ state <= transmitting;
+ symbol_counter <= x"0";
+ -- capture the byte at the parallel input
+ tx_shift_register(8 downto 1) <= DATA_IN;
+ ready_sig <= '0';
+ end if;
+
+ when transmitting =>
+ if symbol_start_pulse = '1' then
+ if symbol_counter <= 9 then -- transmission process
+ symbol <= tx_shift_register(to_integer(symbol_counter));
+ symbol_counter <= symbol_counter + 1;
+ end if;
+
+ end if;
+ if symbol_counter = 10 then -- pulse #10 (1 start, 8 data, 1 stop) has been sent
+ --, time to go to idle mode again
+ -- pull the tx line high again, actually obsolete, because stop bit is 1
+ symbol <= '1';
+ ready_sig <= '1';
+ state <= idle;
+ end if;
+
+ end case;
+
+ -- reset clock divider counters when reset signal is on
+ if RST = '1' then
+ state <= idle;
+ end if;
+
+ end process;
+
+
+
+end architecture;
+
###################################################################################
#Settings for this project
my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64';
-my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
+my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
###################################################################################
#create full lpf file
-system("cp ../base/".$TOPNAME."1.lpf workdir/$TOPNAME.lpf");
+system("cp ../pinout/".$TOPNAME."1.lpf workdir/$TOPNAME.lpf");
system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
#project files
add_file -vhdl -lib work "/d/jspc29/lattice/diamond/2.2_x64/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "../..//trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+#add_file -vhdl -lib work "../base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "source/spi_slave.vhd"
+add_file -vhdl -lib work "../source/spi_slave.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "source/pwm.vhd"
-add_file -vhdl -lib work "cores/pll_shifted_clocks.vhd"
-add_file -vhdl -lib work "cores/fifo_1kx8.vhd"
-add_file -vhdl -lib work "source/ffarray.vhd"
-
-
-add_file -vhdl -lib work "cores/oddr16.vhd"
-add_file -vhdl -lib work "cores/flash.vhd"
-add_file -vhdl -lib work "cores/flashram.vhd"
-add_file -vhdl -lib work "cores/pll.vhd"
-add_file -verilog -lib work "cores/efb_define_def.v"
-add_file -verilog -lib work "cores/UFM_WB.v"
+add_file -vhdl -lib work "../source/pwm.vhd"
+add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
+add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
+add_file -vhdl -lib work "../source/ffarray.vhd"
+
+
+add_file -vhdl -lib work "../cores/oddr16.vhd"
+add_file -vhdl -lib work "../cores/flash.vhd"
+add_file -vhdl -lib work "../cores/flashram.vhd"
+add_file -vhdl -lib work "../cores/pll.vhd"
+add_file -verilog -lib work "../cores/efb_define_def.v"
+add_file -verilog -lib work "../cores/UFM_WB.v"
add_file -vhdl -lib work "panda_dirc_wasa.vhd"
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
-use work.trb3_components.all;
+-- use work.trb3_components.all;
use work.version.all;
library machxo2;
jspc29 / padiwa.git / commitdiff