Updating registers for Trb3sc and Padiwa

diff --git a/xml-db/database/InputMonitorTrb3sc.xml b/xml-db/database/InputMonitorTrb3sc.xml
index 81378ed4f8c3afdcefeb988878dcaa39b2372db0..31b72725eb2d29598fbd4b7b9091e72e2008c761 100644 (file)
--- a/xml-db/database/InputMonitorTrb3sc.xml
+++ b/xml-db/database/InputMonitorTrb3sc.xml
@@ -82,45 +82,45 @@
     </register>    
   </group>
 
-  <group name="Trigger" purpose="config" address="0000" size="37" mode="rw" continuous="false">
+  <group name="Trigger" purpose="config" address="0000" size="256" mode="rw" continuous="false">
     <description>Registers of the trigger generation logic</description>  
-    <group name="TriggerGeneration" purpose="config" address="0000" size="2" repeat="16" continuous="true">
-      <register name="TriggerEnable" address="0000"  mode="rw" >
-         <description>Enables individual inputs for trigger generation. If enabled, the input adds to the common or</description>
-         <field  name="TriggerEnable" start="0" bits="32" format="bitmask" noflag="true">
-         </field>
+    <group name="TriggerGeneration" purpose="config" address="0000" size="4" repeat="16" continuous="false">
+      <register name="TriggerEnable1" address="0000"  mode="rw" >
+        <description>Enables individual inputs 0 - 31 for trigger generation. If enabled, the input adds to the common or</description>
+        <field  name="TriggerEnable" start="0" bits="32" format="bitmask" noflag="true" />
       </register>
-      <register name="TriggerInvertOld" address="0001" mode="rw" >
-         <description>Inverts individual inputs for trigger generation. DOES NOT EXIST IN NEW DESIGNS</description>
-         <field  name="TriggerInvertOld" start="0" bits="32" format="bitmask" noflag="true">
-         </field>
+      <register name="TriggerEnable2" address="0001"  mode="rw" >
+        <description>Enables individual inputs 63 - 32 for trigger generation. If enabled, the input adds to the common or</description>
+        <field  name="TriggerEnable2" start="0" bits="32" format="bitmask" noflag="true" />
       </register>
+      <register name="TriggerEnable3" address="0002"  mode="rw" >
+        <description>Enables individual inputs 95 - 64 for trigger generation. If enabled, the input adds to the common or</description>
+        <field  name="TriggerEnable3" start="0" bits="32" format="bitmask" noflag="true" />
+      </register>      
     </group>
-    <register name="TriggerInput" address="0020" mode="r" >
-      <description>Current status of all inputs</description>
-      <field  name="TriggerInput" start="0"   bits="32" format="bitmask" />
-    </register>         
-    <register name="TriggerOutput" address="0021" mode="r" >
-      <description>Current status of all inputs</description>
-      <field  name="TriggerOutput" start="0"   bits="32" format="bitmask" />
-    </register>         
-    <register name="TriggerStretch" address="0022" mode="rw" >
+      
+
+    <register name="TriggerStretch" address="0020" mode="rw" repeat="3">
       <description>Enable stretching of individual input channels by adding 10 to 20 ns to the signal length</description>
       <field  name="TriggerStretch" start="0"   bits="32" format="bitmask" />
     </register>             
-    <register name="TriggerInvert" address="0024" mode="rw" >
+    <register name="TriggerInvert" address="0024" mode="rw" repeat="3" >
       <description>Inverts individual inputs for trigger generation.</description>
       <field  name="TriggerInvert" start="0"   bits="32" format="bitmask" />
     </register>     
-    <register name="TriggerCoincidence1" address="0025" mode="rw" >
+    <register name="TriggerCoincidence1" address="0028" mode="rw" repeat="3" >
       <description>Enable input to be used in coincidence logic. First group of signals or'ed. At least one of the inputs to each group must fire within 40 ns to get a coincidence.</description>
       <field  name="TriggerCoincidence1" start="0"   bits="32" format="bitmask" />
     </register>  
-    <register name="TriggerCoincidence2" address="0026" mode="rw" >
+    <register name="TriggerCoincidence2" address="002c" mode="rw" repeat="3" >
       <description>Enable input to be used in coincidence logic. Second group of signals or'ed. At least one of the inputs to each group must fire within 40 ns to get a coincidence.</description>
       <field  name="TriggerCoincidence2" start="0"   bits="32" format="bitmask" />
     </register>      
-    <register name="TriggerConfig" address="0027" mode="r" >
+    <register name="TriggerOutput" address="0030" mode="r" >
+      <description>Current status of all outputs</description>
+      <field  name="TriggerOutput" start="0"   bits="32" format="bitmask" />
+    </register>     
+    <register name="TriggerConfig" address="0031" mode="r" >
       <description>Information about configuration.</description>
       <field  name="TriggerInputs" start="0" bits="6" format="unsigned" noflag="true">
          <description>Number of inputs to the trigger logic</description>
@@ -128,7 +128,9 @@
       <field  name="TriggerOutputs" start="8" bits="4" format="unsigned" noflag="true">
          <description>Number of outputs of the trigger logic</description>
       </field>
-    </register>     
+    </register>
+    
+        
    </group>  
   
 </TrbNetEntity>

diff --git a/xml-db/database/Padiwa.xml b/xml-db/database/Padiwa.xml
index 15f12413e6e845511193016d7a303a0ff0e51dbb..75f6e1990df9aaaaf4b833d09901e983150770ec 100644 (file)
--- a/xml-db/database/Padiwa.xml
+++ b/xml-db/database/Padiwa.xml
@@ -82,6 +82,10 @@
       thresholds when temperature is changing. See Padiwa manual.</description>
       <field name="TemperatureCompensation" start="0" bits="16" format="hex" />
     </register>
+    <register name="DelaySelect" address="000b">
+      <description>Select one of the internal taps of the delay line. Approx. 4.5ns per tap.</description>
+      <field name="DelaySelect" start="0" bits="4" format="hex" />
+    </register>    
   </group>
 
 </SpiEntity>