Multicycle on busy_in, maybe that produces a timing error free design

diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf
index d6fccd7f5b403582da3835bfeae515d6c2dfdae1..6d7446d0ab1926e2817f7dfef6c4e7e38d945c58 100644 (file)
--- a/ADC/trb3_periph_adc_constraints.lpf
+++ b/ADC/trb3_periph_adc_constraints.lpf
@@ -92,7 +92,7 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c";
 #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X;
 
 MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X;
-
+MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X;
 
 # we define everything doubled to make it work with all lattice/synplify versions
 # due to _ vs . notation of generate statements args...