$lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g;
-# for TDC v1.6.3
-$lpf =~ s#ff_array_en#ff_array_en_i#g;
-$lpf =~ s#hit_mux_ch#hit_mux_ch/hit_i_5_u#g;
-
-# make the LPF diamond 2.1 compatible
-# we assume that generate loops are all named with "gen_"
-sub replace_dot {
- my @m = @_;
- $m[1] =~ s/\./_/g;
- return join("", @m);
-}
-$lpf =~ s#(BLKNAME\s+)(.+?)([;\s])#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#(CELL\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#(NET\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#(COMP\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
-
-
open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!";
print FILE $lpf;
close FILE;
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity
-my $lattice_path = '/opt/lattice/diamond/2.1_x64';
+my $lattice_path = '/opt/lattice/diamond/3.4_x64';
my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
-my $synplify_path = '/opt/synplicity/F-2012.03-SP1';
+my $synplify_path = '/opt/synplicity/J-2014.09-SP2';
my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de';
my $lm_license_file_for_par = '1702@hadeb05.gsi.de';
###################################################################################
constant ADC_TRIGGER_LOGIC : integer := c_YES;
-- ADC channels may be 48 or 36, the latter for enabling compilation
-- with TDC and lattice diamond version >2.1
- constant ADC_CHANNELS : integer := 48;
+ constant ADC_CHANNELS : integer := 36;
--Include the TDC (only useful for CFD readout mode)
constant INCLUDE_TDC : integer := c_YES;
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0;
--> change names in constraints file
- --ring buffer size: 32,64,96,128,dyn
- --for TDC v1.6.3, only 0,1,3 are valid
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size: 0, 1, 2, 3, 7
+ --ring buffer size: 32,64,96,128,dyn
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7
- constant TDC_CONTROL_REG_NR : integer := 6;
-
-
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
-../../tdc/releases/tdc_v1.6.3
\ No newline at end of file
+../../tdc/releases/tdc_v2.1.3/
\ No newline at end of file
set_option -part_companion ""
# compilation/mapping options
-#set_option -default_enum_encoding sequential
+set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -top_module "trb3_periph_adc"
-#set_option -resource_sharing true
-
-
-
-# Lattice XP
-set_option -maxfan 100
-set_option -fix_gated_and_generated_clocks 1
-set_option -RWCheckOnRam 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-
+set_option -resource_sharing true
# map options
set_option -frequency 200
-set_option -fanout_limit 1000
+set_option -fanout_limit 100
set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+#set_option -force_gsr
set_option -force_gsr false
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
set_option -compiler_compatible true
-set_option -retiming 0
-set_option -pipe 1
-set_option -max_parallel_jobs 3
-#set_option -automatic_compile_point 1
-#set_option -continue_on_error 1
-set_option -resolve_multiple_driver 1
# simulation options
set_option -write_verilog 0
set_option -write_vhdl 1
# automatic place and route (vendor) options
-set_option -write_apr_constraint 1
+set_option -write_apr_constraint 0
# set result format/file last
project -result_format "edif"
add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
- add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
+ add_file -vhdl -lib "work" "tdc_release/ROM_encoder_ecp3.vhd"
add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
+ add_file -vhdl -lib "work" "tdc_release/Stretcher_A.vhd"
+ add_file -vhdl -lib "work" "tdc_release/Stretcher_B.vhd"
+ add_file -vhdl -lib "work" "tdc_release/Stretcher.vhd"
add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"
signal tdc_inputs : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0);
+ constant TDC_CONTROL_REG_NR : integer := 8;
type tdc_ctrl_reg_arr_t is array (0 to TDC_CONTROL_REG_NR-1) of std_logic_vector(31 downto 0);
signal tdc_ctrl_reg_arr : tdc_ctrl_reg_arr_t;
signal tdc_ctrl_reg : std_logic_vector(TDC_CONTROL_REG_NR*32-1 downto 0);
generic map (
CHANNEL_NUMBER => TDC_CHANNEL_NUMBER, -- Number of TDC channels
STATUS_REG_NR => 21, -- Number of status regs
- TDC_VERSION => TDC_VERSION,
CONTROL_REG_NR => TDC_CONTROL_REG_NR, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- DEBUG => c_YES
+ DEBUG => c_NO
)
port map (
RESET => reset_i,
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
HIT_IN => tdc_inputs, -- Channel start signals
- HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC
+ HIT_CAL_IN => osc_int, --clk_20_i, -- Hits for calibrating the TDC
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
--
GSR_NET NET "GSR_N";
MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
-MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
#################################################################
# Locate Serdes and media interfaces
#MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X;
MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X;
-MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X;
+MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/proc_readout*busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X;
MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_q_*" TO CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_qq_*" 2 X;
# left are ADCs 0-5 and 7 (counted from 0)
UGROUP "EF_LT2" BBOX 10 51
BLKNAME THE_TDC/ReferenceChannel/Channel200
- BLKNAME THE_TDC/ReferenceChannel/Buffer_32.The_Buffer
+ BLKNAME THE_TDC/ReferenceChannel/Buffer_128.The_Buffer
BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200
- BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_32.The_Buffer
+ BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer
;
LOCATE UGROUP "EF_LT2" SITE "R105C2D" ;
BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en_1_i;
LOCATE UGROUP "ff_en_1" SITE "R113C27D" ;
-# TDC control register in top-level entity
-MULTICYCLE FROM CELL "tdc_ctrl_reg*" 4x;
-
-# For v2.1.3
-
-# #############################################################################
-# ## Unimportant Data Lines ##
-# #############################################################################
-# #MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_RIGHT_c 2x;
-# MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x;
-
-# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x;
-# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x;
-
-# MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr[*]" 4 X;
-# MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/epoch_cntr[*]" 4 X;
-
-# MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x;
-# MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x;
-
-# MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory[*]" 2.000000 X ;
-
-# MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x;
-
-# #MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ;
-
-
-# BLOCK NET "THE_TDC/pulse[*]";
-# BLOCK NET "THE_TDC/hit_in_s*";
-
-# MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;
-
-
-
-
-
-
-# # MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x;
-# # MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x;
-# # MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x;
-
-# ## Maybe effective
-
-# # MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X;
-
-
-
-# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en";
-# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en";
-
-
-### For v1.6.3
-
#############################################################################
## Unimportant Data Lines ##
#############################################################################
+#MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x;
MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_RIGHT_c 2x;
-
MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x;
-# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x;
-
-MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x;
-MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x;
-
-# only relevant when TDC debug mode is c_YES
-MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x;
-MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x;
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x;
MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x;
+MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x;
-MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 3 X;
-MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 3 X;
+MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr[*]" 4 X;
+MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/epoch_cntr[*]" 4 X;
MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x;
MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x;
+MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory[*]" 2.000000 X ;
+MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x;
-# #MAXDELAY FROM GROUP "hitBuf*" TO GROUP "FC*" 0.600000 nS;
-# #MAXDELAY FROM GROUP "hitBuf_ref*" TO GROUP "Ref_Ch" 0.600000 nS;
+#MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ;
-MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;
+BLOCK NET "THE_TDC/pulse[*]";
+BLOCK NET "THE_TDC/hit_in_s*";
-## Maybe effective
+MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ;
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Buffer*The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X;
-# # BLOCK NET "THE_TDC/reset_tdc*" ;
-# # BLOCK NET "THE_TDC/reset_rdo*" ;
-# # #BLOCK NET "THE_TDC/hit_in_i_*" ;
-# # BLOCK NET "THE_TDC/hit_latch*" ;
-# # BLOCK NET "THE_TDC/reset_counters_i*" ;
+# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x;
+MULTICYCLE FROM CELL "tdc_ctrl_reg*" 4x;
+# MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x;
+# MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x;
+
+## Maybe effective
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X;
-# # PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i";
-# # PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i";
+PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en";
+PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en";
jspc29 / trb3.git / commitdiff