added onewire interface, Jan

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index b0a887e4f5bc3b4cd637dd644eab3f08a5f6e9c3..37251b8558ce85fb41679d184ac1ebb8f2f3cf2c 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -61,19 +61,12 @@ signal matching_counter : std_logic_vector(2 downto 0);
 signal ram_read_addr1 : std_logic_vector(2 downto 0);
 signal ram_read_addr2 : std_logic_vector(2 downto 0);
 signal buf_API_READ_OUT, next_API_READ_OUT : std_logic;
+signal write_UNIQUE_ID : std_logic;
 
-type state_t is (IDLE, SEND1, SEND2, SEND3);
+type state_t is (IDLE, SEND1, SEND2, SEND3, SEND_UNIQUE_ID);
 signal next_state, state : state_t;
 
---memory
---00: SET_ADDRESS & endpoint_id
---01: unique_id_0
---02: unique_id_1
---03: unique_id_2
---04: unique_id_3
---05: 00 & board_info0
---06: board_info1
---07: ACK_ADDRESS
+
 
 begin
 
@@ -123,33 +116,46 @@ begin
       case state is
         when IDLE =>
           if write_ADDRESS = '1' then
-            ram_read_addr2 <= "101";
+            ram_read_addr2 <= "111";
             next_state <= SEND1;
+          elsif write_UNIQUE_ID = '1' then
+            ram_read_addr2 <= "001";
+            next_state <= SEND_UNIQUE_ID;
           end if;
         when SEND1 =>
           API_DATAREADY_OUT <= '1';
           API_PACKET_NUM_OUT <= "01";
-          ram_read_addr2 <= "101";
+          ram_read_addr2 <= "111";
           if API_READ_IN = '1' then
-            ram_read_addr2 <= "110";
+            ram_read_addr2 <= "101";
             next_state <= SEND2;
           end if;
         when SEND2 =>
           API_DATAREADY_OUT <= '1';
           API_PACKET_NUM_OUT <= "10";
-          ram_read_addr2 <= "110";
+          ram_read_addr2 <= "101";
           if API_READ_IN = '1' then
-            ram_read_addr2 <= "111";
+            ram_read_addr2 <= "110";
             next_state <= SEND3;
           end if;
         when SEND3 =>
           API_DATAREADY_OUT <= '1';
           API_PACKET_NUM_OUT <= "11";
-          ram_read_addr2 <= "111";
+          ram_read_addr2 <= "110";
           if API_READ_IN = '1' then
             next_state <= IDLE;
             ram_read_addr2 <= "000";
           end if;
+        when SEND_UNIQUE_ID =>
+          API_DATAREADY_OUT <= '1';
+          API_PACKET_NUM_OUT <= "01";
+          ram_read_addr2 <= "001";
+          if API_READ_IN = '1' then
+            ram_read_addr2 <= ram_read_addr2 + 1;
+            if ram_read_addr2 = "110" then
+              next_state <= IDLE;
+            end if;
+          end if;
       end case;
     end process;
 
@@ -169,9 +175,9 @@ begin
       INIT2 => INIT_UNIQUE_ID(31 downto 16),
       INIT3 => INIT_UNIQUE_ID(47 downto 32),
       INIT4 => INIT_UNIQUE_ID(63 downto 48),
-      INIT5 => ACK_ADDRESS,
-      INIT6 => x"00" & INIT_UNIQUE_ID(79 downto 72),
-      INIT7 => INIT_UNIQUE_ID(95 downto 80)
+      INIT5 => INIT_UNIQUE_ID(79 downto 64),
+      INIT6 => INIT_UNIQUE_ID(95 downto 80),
+      INIT7 => ACK_ADDRESS
       )
     port map(
       CLK     => CLK,

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index d9a7cd5631c0b687d8118b0174269e4f7f002e31..320b5a6185ba97456f431695d977d06bde58bca4 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -154,7 +154,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal HC_DATAREADY_OUT :  std_logic;
   signal HC_READ_IN       :  std_logic;
   signal HC_RUN_OUT       :  std_logic;
-  signal HC_MY_ADDRESS_IN :  std_logic_vector (15 downto 0);
   signal HC_SEQNR_OUT     :  std_logic_vector (7 downto 0);
   signal HC_STAT_REGS     :  std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
   signal HC_CTRL_REGS     :  std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0);
@@ -683,7 +682,7 @@ begin
         APL_READ_IN           => HC_READ_IN,
         -- APL Control port
         APL_RUN_OUT           => HC_RUN_OUT,
-        APL_MY_ADDRESS_IN     => HC_MY_ADDRESS_IN(15 downto 0),
+        APL_MY_ADDRESS_IN     => HUB_ADDRESS,
         APL_SEQNR_OUT         => HC_SEQNR_OUT(7 downto 0),
         -- Internal direction port
         INT_MASTER_DATAREADY_OUT  => buf_to_hub_REPLY_DATAREADY(i),

diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
new file mode 100644 (file)
index 0000000..2b28c0b
--- /dev/null
+++ b/trb_net_onewire.vhd
@@ -0,0 +1,378 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity trb_net_onewire is
+  generic(
+    USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
+    CLK_PERIOD : integer := 10  --clk period in ns
+    );
+  port(
+    CLK      : in std_logic;
+    RESET    : in std_logic;
+    --connection to 1-wire interface
+    ONEWIRE  : inout std_logic;
+    --connection to id ram, according to memory map in TrbNetRegIO
+    DATA_OUT : out std_logic_vector(15 downto 0);
+    ADDR_OUT : out std_logic_vector(2 downto 0);
+    WRITE_OUT: out std_logic;
+    TEMP_OUT : out std_logic_vector(11 downto 0);
+    STAT     : out std_logic_vector(31 downto 0)
+    );
+end entity;
+
+
+architecture trb_net_onewire_arch of trb_net_onewire is
+  constant MAX_COUNTER : integer := 2**17-1;
+  type state_t is (IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_READ_ROM, READ_WAIT,
+                   WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
+                   READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, SEND_SKIP_ROM);
+  signal state, next_state : state_t;
+  signal timecounter : integer range 0 to MAX_COUNTER;
+  signal bitcounter  : integer range 0 to 127;
+  signal bitcounter_vector : std_logic_vector(6 downto 0);
+  signal inc_bitcounter, reset_bitcounter : std_logic;
+  signal output, next_output      : std_logic;
+  signal input       : std_logic;
+  signal reset_timecounter : std_logic;
+  signal send_bit, next_send_bit : std_logic;
+  signal recv_bit,next_recv_bit : std_logic;
+  signal recv_bit_ready : std_logic;
+  signal output_tmp, next_output_tmp : std_logic;
+  signal word : std_logic_vector(15 downto 0);
+  signal ram_addr : std_logic_vector(2 downto 0);
+  signal ram_wr : std_logic;
+  signal send_rom, next_send_rom : std_logic;
+  signal conv_temp, next_conv_temp : std_logic;
+  signal reading_temp, next_reading_temp : std_logic;
+  signal skip_rom, next_skip_rom : std_logic;
+  signal buf_TEMP_OUT, temp_shift : std_logic_vector(11 downto 0);
+
+begin
+
+  ONEWIRE <= '0' when output = '0' else 'Z';
+  input <= ONEWIRE;
+
+  bitcounter_vector <= conv_std_logic_vector(bitcounter,7);
+
+  process(state, timecounter, bitcounter_vector, input,
+          send_bit, output_tmp, skip_rom, recv_bit, conv_temp, reading_temp, send_rom)
+    begin
+      next_state <= state;
+      next_output <= '1';
+      reset_timecounter <= '0';
+      reset_bitcounter <= '0';
+      next_output_tmp <= output_tmp;
+      inc_bitcounter <= '0';
+      next_send_bit <= send_bit;
+      next_recv_bit <= '0';
+      recv_bit_ready <= '0';
+      next_send_rom <= send_rom;
+      next_conv_temp <= conv_temp;
+      next_reading_temp <= reading_temp;
+      next_recv_bit <= recv_bit;
+      next_skip_rom <= skip_rom;
+      case state is
+--reset / presence
+        when IDLE =>
+          if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then
+            next_state <= SEND_RESET;
+            reset_timecounter <= '1';
+          end if;
+        when SEND_RESET =>
+          next_output <= '0';
+          if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then
+            reset_timecounter <= '1';
+            next_state <= WAIT_AFTER_RESET;
+          end if;
+        when WAIT_AFTER_RESET =>
+          if is_time_reached(timecounter,640000,CLK_PERIOD) = '1' then --1200
+            reset_timecounter <= '1';
+            if send_rom = '1' then
+              next_state <= SEND_READ_ROM;
+            else
+              next_skip_rom <= '1';
+              next_state <= SEND_SKIP_ROM;
+            end if;
+          end if;
+          --presence is not checked
+--sending rom commands
+        when SEND_READ_ROM =>
+          next_send_bit <= not bitcounter_vector(1); --this is x33, lsb first
+          inc_bitcounter <= '1';
+          if bitcounter_vector(3) = '1' then  --send 8 bit
+            next_state <= READ_READ_ROM;
+            reset_bitcounter <= '1';
+          else
+            next_state <= WRITE_START;
+          end if;
+
+        when SEND_SKIP_ROM =>
+          next_send_bit <= bitcounter_vector(1);     --this is xCC, lsb first
+          inc_bitcounter <= '1';
+          if bitcounter_vector(3) = '1' then  --send 8 bit
+            next_skip_rom <= '0';
+            if conv_temp = '1' then
+              next_state <= SEND_CONV_TEMP;
+            else
+              next_state <= SEND_READ_TEMP;
+            end if;
+            reset_bitcounter <= '1';
+          else
+            next_state <= WRITE_START;
+          end if;
+
+--sending sensor commands
+        when SEND_CONV_TEMP =>
+          next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0);
+                                                     --this is x44, lsb first
+          inc_bitcounter <= '1';
+          if bitcounter_vector(3) = '1' then  --send 8 bit
+            next_state <= READ_CONV_TEMP;
+            reset_bitcounter <= '1';
+            next_recv_bit <= '0';
+          else
+            next_state <= WRITE_START;
+          end if;
+
+        when SEND_READ_TEMP =>
+          next_send_bit <= (or_all(bitcounter_vector(2 downto 0)))
+                           and not((bitcounter_vector(2) and bitcounter_vector(1) and not bitcounter_vector(0)));
+                                                     --this is xBE, lsb first
+          inc_bitcounter <= '1';
+          if bitcounter_vector(3) = '1' then  --send 8 bit
+            next_state <= READ_READ_TEMP;
+            reset_bitcounter <= '1';
+            next_recv_bit <= '0';
+          else
+            next_state <= WRITE_START;
+          end if;
+
+--reading rom answers
+        when READ_READ_ROM =>
+          inc_bitcounter <= '1';
+          if bitcounter_vector(6) = '1' then --read 64 bit
+            next_state <= IDLE;
+            if USE_TEMPERATURE_READOUT = 1 then
+              next_send_rom <= '0';
+              next_conv_temp <= '1';
+            end if;
+            reset_bitcounter <= '1';
+          else
+            next_state <= READ_BIT;
+          end if;
+
+--reading sensor answers
+        when READ_CONV_TEMP => --waiting for end of conversion
+          if recv_bit = '1' then
+            next_state <= IDLE;
+            if USE_TEMPERATURE_READOUT = 1 then
+              next_conv_temp <= '0';
+              next_reading_temp <= '1';
+            end if;
+          else
+            next_state <= READ_BIT;
+          end if;
+
+        when READ_READ_TEMP => --waiting for end of conversion
+          inc_bitcounter <= '1';
+          if bitcounter_vector(3 downto 2) = "11" then --read 12 bit
+            next_state <= IDLE;
+            if USE_TEMPERATURE_READOUT = 1 then
+              next_send_rom <= '1';
+              next_reading_temp <= '0';
+            end if;
+            reset_bitcounter <= '1';
+          else
+            next_state <= READ_BIT;
+          end if;
+
+
+--write cycle
+        when WRITE_START =>
+          next_output <= output_tmp;
+          if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then
+            next_output_tmp <= send_bit;
+          end if;
+          if is_time_reached(timecounter,80000,CLK_PERIOD) = '1' then
+            next_state <= WRITE_WAIT;
+            next_output_tmp <= '0';
+            reset_timecounter <= '1';
+          end if;
+        when WRITE_WAIT =>
+          if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then
+            reset_timecounter <= '1';
+            if send_rom = '1' then
+              next_state <= SEND_READ_ROM;
+            elsif skip_rom = '1' then
+              next_state <= SEND_SKIP_ROM;
+            elsif conv_temp = '1' then
+              next_state <= SEND_CONV_TEMP;
+            elsif reading_temp = '1' then
+              next_state <= SEND_READ_TEMP;
+            end if;
+          end if;
+
+--read cycle
+        when READ_BIT =>
+          next_output <= output_tmp;
+          if is_time_reached(timecounter,1200,CLK_PERIOD) = '1' then
+            next_output_tmp <= '1';
+          end if;
+          if is_time_reached(timecounter,10000,CLK_PERIOD) = '1' then
+            next_recv_bit <= input;
+            recv_bit_ready <= '1';
+            next_state <= READ_WAIT;
+          end if;
+        when READ_WAIT => 
+          if is_time_reached(timecounter,80000,CLK_PERIOD) = '1' then
+            reset_timecounter <= '1';
+            next_output_tmp <= '0';
+            if send_rom = '1' then
+              next_state <= READ_READ_ROM;
+            elsif conv_temp = '1' then
+              next_state <= READ_CONV_TEMP;
+            else
+              next_state <= READ_READ_TEMP;
+            end if;
+          end if;
+
+        when others =>
+          next_state <= IDLE;
+      end case;
+    end process;
+
+--counting time and bits
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if reset_timecounter = '1' then
+          timecounter <= 0;
+        else
+          timecounter <= timecounter + 1;
+        end if;
+      end if;
+    end process;
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if reset_bitcounter = '1' then
+          bitcounter <= 0;
+        elsif inc_bitcounter = '1' then
+          bitcounter <= bitcounter + 1;
+        end if;
+      end if;
+    end process;
+
+--registers for state machine
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          send_bit <= '0';
+          output_tmp <= '0';
+          recv_bit <= '0';
+        else
+          state <= next_state;
+          send_bit <= next_send_bit;
+          output <= next_output;
+          output_tmp <= next_output_tmp;
+          recv_bit <= next_recv_bit;
+        end if;
+      end if;
+    end process;
+
+--save current kind of operation
+  gen_stat_sig : if USE_TEMPERATURE_READOUT = 1 generate
+    process(CLK)
+      begin
+        if rising_edge(CLK) then
+          if RESET = '1' then
+            send_rom <= '1';
+            conv_temp <= '0';
+            reading_temp <= '0';
+            skip_rom <= '0';
+          else
+            send_rom <= next_send_rom;
+            conv_temp <= next_conv_temp;
+            reading_temp <= next_reading_temp;
+            skip_rom <= next_skip_rom;
+          end if;
+        end if;
+      end process;
+  end generate;
+  gen_stat_sig_1 : if USE_TEMPERATURE_READOUT = 0 generate
+    send_rom <= '1';
+    conv_temp <= '0';
+    reading_temp <= '0';
+    skip_rom <= '0';
+  end generate;
+
+
+--saving received id data
+  process(CLK)
+    begin 
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          ram_wr <= '0';
+        else
+          ram_wr <= '0';
+          if recv_bit_ready = '1' and send_rom = '1' then
+            ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
+            ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
+            word(15 downto 1) <= word(14 downto 0);
+            word(0) <= recv_bit;
+            if bitcounter_vector(3 downto 0) = "0000" then
+              ram_wr <= '1';
+            end if;
+          end if;
+        end if;
+      end if;
+    end process;
+
+--saving temperature
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if recv_bit_ready = '1' and reading_temp = '1' then
+          temp_shift(10 downto 0) <= temp_shift(11 downto 1);
+          temp_shift(11) <= recv_bit;
+          if bitcounter_vector(3 downto 0) = "1100" then
+            buf_TEMP_OUT <= temp_shift;
+          end if;
+        end if;
+      end if;
+    end process;
+
+  ADDR_OUT <= ram_addr;
+  DATA_OUT <= word;
+  WRITE_OUT <= ram_wr;
+
+  TEMP_OUT <= buf_TEMP_OUT;
+
+  STAT(1) <= input;
+  STAT(2) <= output;
+  STAT(3) <= send_rom;
+  STAT(4) <= skip_rom;
+  STAT(5) <= conv_temp;
+  STAT(6) <= reading_temp;
+  STAT(7) <= '0';
+  STAT(11 downto 8) <= bitcounter_vector(3 downto 0);
+  STAT(31 downto 12) <= (others => '0');
+
+end architecture;
+
+
+
+
+
+
+
+
+