signal spi_sdi, spi_sdo, spi_sck : std_logic_vector(15 downto 0);
signal spi_cs : std_logic_vector(15 downto 0);
-signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic;
+--signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic;
signal uart_rx, uart_tx : std_logic;
signal flashset_active, debug_active : std_logic;
---------------------------------------------------------------------------
-- LCD
---------------------------------------------------------------------------
-gen_lcd : if INCLUDE_LCD = 1 generate
- THE_LCD : entity work.lcd
- port map(
- CLK => CLK,
- RESET => RESET,
-
- MOSI => lcd_mosi,
- SCK => lcd_sck,
- DC => lcd_dc,
- CS => lcd_cs,
- RST => lcd_rst,
-
- INPUT => LCD_DATA_IN,
- DEBUG => open
- );
-end generate;
+-- gen_lcd : if INCLUDE_LCD = 1 generate
+-- THE_LCD : entity work.lcd
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET,
+--
+-- MOSI => lcd_mosi,
+-- SCK => lcd_sck,
+-- DC => lcd_dc,
+-- CS => lcd_cs,
+-- RST => lcd_rst,
+--
+-- INPUT => LCD_DATA_IN,
+-- DEBUG => open
+-- );
+-- end generate;
---------------------------------------------------------------------------
-- SPI
HEADER_IO(1) <= uart_tx;
uart_rx <= HEADER_IO(2);
-gen_lcdio : if INCLUDE_LCD = 1 generate
- HEADER_IO(3) <= lcd_mosi;
- HEADER_IO(5) <= lcd_sck;
- HEADER_IO(6) <= lcd_cs;
-end generate;
-gen_nolcdio : if INCLUDE_LCD = 0 generate
+-- gen_lcdio : if INCLUDE_LCD = 1 generate
+-- HEADER_IO(3) <= lcd_mosi;
+-- HEADER_IO(5) <= lcd_sck;
+-- HEADER_IO(6) <= lcd_cs;
+-- end generate;
+-- gen_nolcdio : if INCLUDE_LCD = 0 generate
HEADER_IO(3) <= spi_sdo(8);
-- HEADER_IO(4) <= ;
HEADER_IO(5) <= spi_sck(8);
HEADER_IO(6) <= spi_cs(8);
-end generate;
+-- end generate;
-HEADER_IO(7) <= lcd_dc;
-HEADER_IO(8) <= lcd_rst;
+--HEADER_IO(7) <= lcd_dc;
+--HEADER_IO(8) <= lcd_rst;
debug_rx <= HEADER_IO(9);
HEADER_IO(10) <= debug_tx;