Update dirich diamond project and combiner trigger output

diff --git a/combiner/combiner.vhd b/combiner/combiner.vhd
index 1ffb95fbc44ff6286cdd71a9a3dd004d3c8d363e..a1847f0d308f923a5445bdeab6735646cf458fe0 100644 (file)
--- a/combiner/combiner.vhd
+++ b/combiner/combiner.vhd
@@ -584,7 +584,8 @@ end generate;
 -- Monitoring & Trigger
 ---------------------------------------------------------------------------  
 
-  TRIGGER_TO_CTS <= trig_gen_out_i(0);
+  TRIGGER_TO_CTS <= trig_gen_out_i(1);
+  RJ45_SIG_4     <= trig_gen_out_i(0);
   TRIGGER_OUT    <= RJ45_SIG_1;
   
   monitor_inputs_i(11 downto  0) <= BACK_TRIG1;

diff --git a/dirich/diamond/dirich.ldf b/dirich/diamond/dirich.ldf
index f3c8efb1450705ad8fc601b6c9e5384ae0c981da..8f182a596a370da82ab0a8824c608b98108c57ee 100644 (file)
--- a/dirich/diamond/dirich.ldf
+++ b/dirich/diamond/dirich.ldf
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="d" device="LFE5UM-85F-8BG381C" default_implementation="p">
+<BaliProject version="3.2" title="d" device="LFE5UM5G-85F-8BG381C" default_implementation="p">
     <Options/>
     <Implementation title="p" dir="project" description="project" synthesis="synplify" default_strategy="Strategy1">
         <Options def_top="fifo_18x8k_oreg" top="dirich"/>
@@ -387,6 +387,9 @@
         <Source name="../../../trbnet/lattice/ecp5/FIFO/fifo_18x8k_oreg/fifo_18x8k_oreg.sbx" type="sbx" type_short="SBX">
             <Options/>
         </Source>
+        <Source name="../../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../workdir/dirich.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>

diff --git a/dirich/diamond/dirich1.sty b/dirich/diamond/dirich1.sty
index 2f4c1191dc5a39547d7755c50cd974c22e844d8a..264271b26bf214863bf048d41e559d8642c42a03 100644 (file)
--- a/dirich/diamond/dirich1.sty
+++ b/dirich/diamond/dirich1.sty
@@ -30,7 +30,7 @@
     <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
     <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
     <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
-    <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
     <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
     <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
     <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
@@ -51,7 +51,7 @@
     <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
     <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
     <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
-    <Property name="PROP_LST_EdfFrequency" value="" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
     <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
     <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
     <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>