signal rclk_250_i : std_logic; -- recovered word clock
signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word
signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL
-
+
+ signal clk_tx_half_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL
+
signal rst_i : std_logic; -- High-active reset driven by external logic
signal rst_n_i : std_logic; -- Low-active version of rst_i
+ signal clk_serdes_rx_ref : std_logic;
+ signal clk_serdes_tx_ref : std_logic;
+
-- SERDES/PCS
-- status
signal rx_los_low_i : std_logic;
rst_n_i <= not rst_i;
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
- clk_125_i <= rclk_125_i;
+ clk_125_i <= rclk_125_i;
+ clk_serdes_rx_ref <= clk_125_local;
+ clk_serdes_tx_ref <= rclk_125_i;
end generate;
gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
- clk_125_i <= clk_125_local;
+ clk_125_i <= clk_tx_half_i;
+ clk_serdes_rx_ref <= clk_tx_half_i;
+ clk_serdes_tx_ref <= clk_125_local;
end generate;
-------------------------------------------------
hdoutn_ch0 => SD_TXD_N_OUT,
-- CLOCKS
- txiclk_ch0 => clk_125_i,
-
rx_full_clk_ch0 => rclk_250_i,
rx_half_clk_ch0 => open, -- recovered (and correctly aligned) 125 MHz clock is generated by gear
tx_full_clk_ch0 => clk_tx_full_i,
tx_half_clk_ch0 => open,
- fpga_rxrefclk_ch0 => clk_125_local,
- fpga_txrefclk => clk_125_i,
+ fpga_rxrefclk_ch0 => clk_serdes_rx_ref,
+ fpga_txrefclk => clk_serdes_tx_ref,
+ txiclk_ch0 => clk_tx_full_i,
-- RESETS
rst_qd_c => rst_qd_i,
rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES);
- THE_TX_GEAR: CBMNET_PHY_TX_GEAR port map (
+ THE_TX_GEAR: CBMNET_PHY_TX_GEAR
+ generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)
+ port map (
CLK_250_IN => clk_tx_full_i, -- in std_logic;
CLK_125_IN => clk_125_i, -- in std_logic;
+ CLK_125_OUT => clk_tx_half_i,
+
RESET_IN => tx_gear_reset_i, -- in std_logic;
DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0)
);
tx_gear_reset_i <= not tx_rst_fsm_ready_i;
- process is begin
+ process is
+ begin
wait until rising_edge(clk_tx_full_i);
tx_data_debug_state_i <= not tx_data_debug_state_i;
use work.cbmnet_phy_pkg.all;
entity CBMNET_PHY_TX_GEAR is
+ generic (
+ IS_SYNC_SLAVE : integer range 0 to 1 := c_YES
+ );
port (
-- SERDES PORT
CLK_250_IN : in std_logic;
CLK_125_IN : in std_logic;
+ CLK_125_OUT : out std_logic;
+
RESET_IN : in std_logic;
DATA_IN : in std_logic_vector(17 downto 0);
clk_125_xfer_buf_i <= clk_125_xfer_i;
clk_125_xfer_del_i <= clk_125_xfer_buf_i;
+ CLK_125_OUT <= '0';
case fsm_i is
when FSM_WAIT =>
- if clk_125_xfer_buf_i /= clk_125_xfer_del_i then
+ if clk_125_xfer_buf_i /= clk_125_xfer_del_i or IS_SYNC_SLAVE = c_NO then
fsm_i <= FSM_HIGH;
end if;
when FSM_HIGH =>
+ CLK_125_OUT <= '1';
DATA_OUT <= data_in_buf125_i(17) & data_in_buf125_i(15 downto 8);
low_data_i <= data_in_buf125_i(16) & data_in_buf125_i( 7 downto 0);
fsm_i <= FSM_LOW;
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