LOCATE COMP "TEST_LINE_14" SITE "H10";
LOCATE COMP "TEST_LINE_15" SITE "H11";
DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST DRIVE=12;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST DRIVE=20;
#################################################################
# Connection to AddOn
DATAWIDTH : integer := 16;
SINGLE_DEST : integer := 1;
DATA_PADDING : integer := 0;
- CTRL_PADDING : integer := 16#A5A5#;
-
- ROC_ADDR : std_logic_vector(15 downto 0) := "00000000XXXXXXXX";
- OWN_ADDR : std_logic_vector(15 downto 0) := "1000000000000000"
+ CTRL_PADDING : integer := 16#A5A5#
+
+ -- cannot use X's here, as the synplify seems to not support this for
+ -- multi-language projects
+ -- ROC_ADDR : std_logic_vector(15 downto 0) := "00000000XXXXXXXX";
+ -- OWN_ADDR : std_logic_vector(15 downto 0) := "1000000000000000"
);
port (
clk : in std_logic;
MIN_PACKET_SIZE : integer := 8;
MAX_PACKET_SIZE : integer := 64;
PACKET_GRAN : integer := 2;
-
MIN_CTRL_PACKET_SIZE : integer := 12;
MAX_CTRL_PACKET_SIZE : integer := 60;
- DATAWIDTH : integer := 16;
- SINGLE_DEST : integer := 1;
- DATA_PADDING : integer := 0;
+
CTRL_PADDING : integer := 16#A5A5#;
-
- ROC_ADDR : std_logic_vector(15 downto 0) := "0000000000000000";
OWN_ADDR : std_logic_vector(15 downto 0) := "1000000000000000";
-
+ DEST_ADDR : std_logic_vector(15 downto 0) := "0000000000000000";
PACKET_MODE : integer := 1 --if enabled generates another packet size order to test further corner cases
);
port (
ctrl_rec_start : in std_logic;
ctrl_rec_end : in std_logic;
ctrl_rec : in std_logic_vector(15 downto 0);
- ctrl_rec_stop : std_logic
+ ctrl_rec_stop : out std_logic
);
end component;
end package cbmnet_interface_pkg;
wait until rising_edge(rclk_125_i);
CLK_RX_RESET_OUT <= '1';
- if rx_cdr_lol_i = '1' then
+ if serdes_ready_i = '0' then
counter := (others => '0');
elsif counter(counter'high) = '0' then
#-- Synopsys, Inc.
#-- Version F-2012.03-SP1
-#-- Project file /u/mpenschuck/Documents/trb3/cbmnet/trb3_periph_cbmnet.prj
+#-- Project file /d/jspc29/mpenschuck/trb3/cbmnet/trb3_periph_cbmnet.prj
#project files
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_2c.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w2r_1c.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_1c.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_2c.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c_enable.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fast_fifo.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_ram.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_reg.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_fwft_fifo.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_standard_fifo.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_spec_so.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_wo_spec.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v"
-
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/async_input_sync.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_ready_module.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_rm_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_ready_module.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_rm_fsm.v"
-
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_in.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_out.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in_decode.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_out.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_packet_gen.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_buffer.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service_ctrl.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_slave_top.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_top.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v"
-
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_send_fsm.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_random_stopper.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_be.v"
-add_file -verilog -lib work "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_fe.v"
-
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_2c.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w2r_1c.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_1c.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_2c.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c_enable.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fast_fifo.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_ram.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_reg.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_fwft_fifo.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_standard_fifo.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_spec_so.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_wo_spec.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v"
+add_file -verilog "./cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/async_input_sync.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_ready_module.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_rx_rm_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_ready_module.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_init/gtp_tx_rm_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_in.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_out.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in_decode.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_init.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_in.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_out.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_packet_gen.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_buffer.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service_ctrl.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_service.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_slave_top.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_top.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_send_fsm.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/lt_random_stopper.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_be.v"
+add_file -verilog "./cbmnet/cores/CBMnet/building_blocks/link_tester/link_tester_fe.v"
add_file -vhdl -lib work "./version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
-
add_file -vhdl -lib work "./code/cbmnet_interface_pkg.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_pkg.vhd"
-
add_file -vhdl -lib work "./cores/cbmnet_sfp1.vhd"
-
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
-
add_file -vhdl -lib work "./code/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_rx_gear.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_tx_gear.vhd"
add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd"
-
add_file -vhdl -lib work "./trb3_periph_cbmnet.vhd"
+
#implementation: "workdir"
impl -add workdir -type fpga
#set result format/file last
project -result_file "./workdir/trb3_periph_cbmnet.edf"
+
+#design plan options
impl -active "workdir"
attribute syn_keep of CLK_GPLL_LEFT, CLK_GPLL_RIGHT, CLK_PCLK_LEFT, CLK_PCLK_RIGHT, TRIGGER_LEFT, TRIGGER_RIGHT : signal is true;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
+
end entity;
architecture trb3_periph_arch of trb3_periph_cbmnet is
signal clear_i : std_logic;
signal reset_i : std_logic;
signal GSR_N : std_logic;
+
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
signal cbm_ctrl_rec : std_logic_vector(15 downto 0); -- receive control interface
signal cbm_ctrl_rec_start : std_logic;
signal cbm_ctrl_rec_end : std_logic;
- signal cbm_ctrl_rec_stop : std_logic := '0';
+ signal cbm_ctrl_rec_stop : std_logic;
signal cbm_data_from_link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY
signal cbm_data2link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY
signal link_tester_dlm_valid :std_logic;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
signal link_tester_ctrl : std_logic_vector(31 downto 0) := (others => '0');
signal link_tester_stat : std_logic_vector(31 downto 0) := (others => '0');
+ signal dummy : std_logic;
+
begin
clk_125_i <= CLK_GPLL_LEFT;
-- CBMNet Link Tester
---------------------------------------------------------------------------
GEN_LINK_TESTER_BE: if CBM_FEE_MODE = c_NO generate
- THE_LINK_TESTER: link_tester_be
- generic map (
- MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12;
- MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60;
-
- DATAWIDTH => 16, -- : integer := 16;
- SINGLE_DEST => 1, -- : integer := 1;
- DATA_PADDING => 0, -- : integer := 0;
- CTRL_PADDING => 16#A5A5#, -- : integer := 16#A5A5#;
-
- ROC_ADDR => "00000000XXXXXXXX", -- : std_logic_vector(15 downto 0) := "00000000xxxxxxxx";
- OWN_ADDR => "1000000000000000" -- : std_logic_vector(15 downto 0) := "1000000000000000";
- )
- port map (
- clk => rclk_125_i, -- in std_logic;
- res_n => cbm_res_n, -- in std_logic;
- link_active => cbm_link_active, -- in std_logic;
-
- ctrl_en => link_tester_ctrl_en, -- in std_logic; //enable ctrl packet generation
- dlm_en => link_tester_dlm_en, -- in std_logic; //enable dlm generation
- force_rec_data_stop => link_tester_data_stop, -- in std_logic; //force data flow to stop
- force_rec_ctrl_stop => link_tester_ctrl_stop, -- in std_logic; //force ctrl flow to stop
-
- ctrl2send_stop => cbm_ctrl2send_stop, -- in std_logic;
- ctrl2send_start => cbm_ctrl2send_start, -- out std_logic;
- ctrl2send_end => cbm_ctrl2send_end, -- out std_logic;
- ctrl2send => cbm_ctrl2send, -- out std_logic_vector(15 downto 0);
-
- dlm2send_valid => cbm_dlm2send_va, -- out std_logic;
- dlm2send => cbm_dlm2send, -- out std_logic_vector(3 downto 0);
-
- dlm_rec => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0);
- dlm_rec_valid => cbm_dlm_rec_va, -- in std_logic;
-
- data_rec_start => cbm_data_rec_start(0), -- in std_logic;
- data_rec_end => cbm_data_rec_end(0), -- in std_logic;
- data_rec => cbm_data_rec, -- in std_logic_vector(DATAWIDTH-1 downto 0);
- data_rec_stop => cbm_data_rec_stop(0), -- out std_logic;
-
- ctrl_rec_start => cbm_ctrl_rec_start, -- in std_logic;
- ctrl_rec_end => cbm_ctrl_rec_end, -- in std_logic;
- ctrl_rec => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0);
- ctrl_rec_stop => cbm_ctrl_rec_stop, -- out std_logic;
-
- data_valid => link_tester_data_valid, -- out std_logic;
- ctrl_valid => link_tester_ctrl_valid, -- out std_logic;
- dlm_valid => link_tester_dlm_valid -- out std_logic
- );
+-- THE_LINK_TESTER: link_tester_be
+-- generic map (
+-- MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12;
+-- MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60;
+--
+-- DATAWIDTH => 16, -- : integer := 16;
+-- SINGLE_DEST => 1, -- : integer := 1;
+-- DATA_PADDING => 0, -- : integer := 0;
+-- CTRL_PADDING => 16#A5A5# -- : integer := 16#A5A5#;
+-- )
+-- port map (
+-- clk => rclk_125_i, -- in std_logic;
+-- res_n => cbm_res_n, -- in std_logic;
+-- link_active => cbm_link_active, -- in std_logic;
+--
+-- ctrl_en => link_tester_ctrl_en, -- in std_logic; //enable ctrl packet generation
+-- dlm_en => link_tester_dlm_en, -- in std_logic; //enable dlm generation
+-- force_rec_data_stop => link_tester_data_stop, -- in std_logic; //force data flow to stop
+-- force_rec_ctrl_stop => link_tester_ctrl_stop, -- in std_logic; //force ctrl flow to stop
+--
+-- ctrl2send_stop => cbm_ctrl2send_stop, -- in std_logic;
+-- ctrl2send_start => cbm_ctrl2send_start, -- out std_logic;
+-- ctrl2send_end => cbm_ctrl2send_end, -- out std_logic;
+-- ctrl2send => cbm_ctrl2send, -- out std_logic_vector(15 downto 0);
+--
+-- dlm2send_valid => cbm_dlm2send_va, -- out std_logic;
+-- dlm2send => cbm_dlm2send, -- out std_logic_vector(3 downto 0);
+--
+-- dlm_rec => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0);
+-- dlm_rec_valid => cbm_dlm_rec_va, -- in std_logic;
+--
+-- data_rec_start => cbm_data_rec_start(0), -- in std_logic;
+-- data_rec_end => cbm_data_rec_end(0), -- in std_logic;
+-- data_rec => cbm_data_rec, -- in std_logic_vector(DATAWIDTH-1 downto 0);
+-- data_rec_stop => cbm_data_rec_stop(0), -- out std_logic;
+--
+-- ctrl_rec_start => cbm_ctrl_rec_start, -- in std_logic;
+-- ctrl_rec_end => cbm_ctrl_rec_end, -- in std_logic;
+-- ctrl_rec => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0);
+-- ctrl_rec_stop => cbm_ctrl_rec_stop, -- out std_logic;
+--
+-- data_valid => link_tester_data_valid, -- out std_logic;
+-- ctrl_valid => link_tester_ctrl_valid, -- out std_logic;
+-- dlm_valid => link_tester_dlm_valid -- out std_logic
+-- );
end generate;
GEN_LINK_TESTER_FE: if CBM_FEE_MODE = c_YES generate
THE_LINK_TESTER: link_tester_fe
- -- generic map (
- -- MIN_PACKET_SIZE => 8, -- : integer := 8;
- -- MAX_PACKET_SIZE => 64, -- : integer := 64;
- -- PACKET_GRAN => 2, -- : integer := 2;
- --
- -- MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12;
- -- MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60;
- --
- -- DATAWIDTH => 16, -- : integer := 16;
- -- SINGLE_DEST => 1, -- : integer := 1;
- -- DATA_PADDING => 0, -- : integer := 0;
- -- CTRL_PADDING => 16#A5A5#, -- : integer := 16#A5A5#;
- --
- -- ROC_ADDR => "0000000000000000", -- : std_logic_vector(15 downto 0) := "0000000000000000";
- -- OWN_ADDR => "1000000000000000", -- : std_logic_vector(15 downto 0) := "1000000000000000";
- --
- -- PACKET_MODE : integer := 1 --if enabled generates another packet size order to test further corner cases
- -- )
+ generic map (
+ MIN_PACKET_SIZE => 8, -- : integer := 8;
+ MAX_PACKET_SIZE => 64, -- : integer := 64;
+ PACKET_GRAN => 2, -- : integer := 2;
+ MIN_CTRL_PACKET_SIZE => 12, -- : integer := 12;
+ MAX_CTRL_PACKET_SIZE => 60, -- : integer := 60;
+
+ CTRL_PADDING => 16#A5A5#, -- : integer := 16#A5A5#;
+
+ OWN_ADDR => "1000000000000000", -- : std_logic_vector(15 downto 0) := "1000000000000000";
+ DEST_ADDR => "1000000000000000", -- : std_logic_vector(15 downto 0) := "0000000000000000";
+
+ PACKET_MODE => 1 -- : integer := 1 --if enabled generates another packet size order to test further corner cases
+ )
port map (
clk => rclk_125_i, -- in std_logic;
res_n => cbm_res_n, -- in std_logic;
ctrl_rec_start => cbm_ctrl_rec_start, -- in std_logic;
ctrl_rec_end => cbm_ctrl_rec_end, -- in std_logic;
ctrl_rec => cbm_ctrl_rec, -- in std_logic_vector(15 downto 0);
- ctrl_rec_stop => cbm_ctrl_rec_stop -- std_logic
+ ctrl_rec_stop => cbm_ctrl_rec_stop -- out std_logic
);
end generate;
wait until rising_edge(clk_100_i);
time_counter <= time_counter + 1;
end process;
-end architecture;
+end architecture;
\ No newline at end of file
jspc29 / trb3.git / commitdiff