ADC: Adding many missing things to LPF files...how stupid!

diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf
index 8c243a8b77b691721f70e77e14e824e8acf90c47..d1099d240e4d764935abcf0eed75038371add5b3 100644 (file)
--- a/ADC/trb3_periph_adc_constraints.lpf
+++ b/ADC/trb3_periph_adc_constraints.lpf
@@ -6,12 +6,12 @@ BLOCK RD_DURING_WR_PATHS ;
 # Basic Settings
 #################################################################
 
-  SYSCONFIG MCCLK_FREQ = 20;
+SYSCONFIG MCCLK_FREQ = 20;
 
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
   
 #################################################################
 # Reset Nets
@@ -20,6 +20,14 @@ GSR_NET NET "GSR_N";
 
 MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns;
 
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+
+LOCATE COMP          "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION               "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP        "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+
 
 #################################################################
 # Clocks
@@ -30,4 +38,3 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c";
 
 #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0";
 #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1";
-

diff --git a/base/trb3_periph_adc.lpf b/base/trb3_periph_adc.lpf
index 109757a24962bbbeff0614ca2856c8e5f1a10b2b..11fe6b24897faed966cb86440be60c81d452f3b5 100644 (file)
--- a/base/trb3_periph_adc.lpf
+++ b/base/trb3_periph_adc.lpf
@@ -198,3 +198,48 @@ LOCATE COMP  "FPGA_SDO_1"            SITE "T24";
 DEFINE PORT GROUP "FPGA_group" "FPGA_*" ;
 IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
 
+
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+
+LOCATE COMP  "FLASH_CLK"    SITE "B12";
+LOCATE COMP  "FLASH_CS"   SITE "E11";
+LOCATE COMP  "FLASH_DIN"   SITE "E12";
+LOCATE COMP  "FLASH_DOUT"    SITE "A12";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP  "PROGRAMN"   SITE "B11";
+IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP  "TEMPSENS"    SITE "A13";
+IOBUF  PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1"    SITE "AA20";
+LOCATE COMP "CODE_LINE_0"    SITE "Y21";
+IOBUF  PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
+IOBUF  PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
+
+#terminated differential pair to pads
+#LOCATE COMP  "SUPPL"   SITE "C14";
+#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25   ;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP  "LED_GREEN"    SITE "F12";
+LOCATE COMP  "LED_ORANGE"   SITE "G13";
+LOCATE COMP  "LED_RED"      SITE "A15";
+LOCATE COMP  "LED_YELLOW"   SITE "A16";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+