entity trb_net16_cri_interface is
generic(
- INCLUDE_READOUT : std_logic := '0';
- INCLUDE_SLOWCTRL : std_logic := '1';
+ INCLUDE_READOUT : integer range 0 to 1 := 1;
+ INCLUDE_SLOWCTRL : integer range 0 to 1 := 1;
READOUT_BUFFER_SIZE : integer range 1 to 4 := 1
);
port(
signal cfg_allow_rx : std_logic;
signal cfg_max_frame : std_logic_vector(15 downto 0);
+ signal tc_rd_en : std_logic := '0';
+ signal resp_ready : std_logic := '0';
+
+ signal cri_init_dataready_out : std_logic;
+ signal cri_init_data_out : std_logic_vector(15 downto 0);
+ signal cri_init_packet_num_out : std_logic_vector( 2 downto 0);
+ signal cri_init_read_in : std_logic;
+
+ signal cri_reply_dataready_in : std_logic;
+ signal cri_reply_data_in : std_logic_vector(15 downto 0);
+ signal cri_reply_packet_num_in : std_logic_vector( 2 downto 0);
+ signal cri_reply_read_out : std_logic;
+
--DEBUG SIGNALS:
signal debug_resp_control : std_logic_vector(63 downto 0);
signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0);
signal last_cts_readout_finished, last_cts_readout_start : std_logic;
+
+ signal dbg_pc_wr_en : std_logic;
+ signal dbg_pc_data : std_logic_vector( 7 downto 0);
+ signal dbg_pc_sos : std_logic;
+ signal dbg_pc_eos : std_logic;
+ signal dbg_pc_eoq : std_logic;
+ signal dbg_pc_sub_size : std_logic_vector(31 downto 0);
+ signal dbg_pc_trig_nr : std_logic_vector(31 downto 0);
+ signal dbg_pc_trig_type : std_logic_vector( 3 downto 0);
+
+ signal last_dbg_pc_wr_en : std_logic;
+ signal last_dbg_pc_sos : std_logic;
+ signal last_dbg_pc_eos : std_logic;
+ signal last_dbg_pc_eoq : std_logic;
+
+ signal dbg_pc_wr_en_cnt : unsigned(15 downto 0);
+ signal dbg_pc_sos_cnt : unsigned(15 downto 0);
+ signal dbg_pc_eos_cnt : unsigned(15 downto 0);
+ signal dbg_pc_eoq_cnt : unsigned(15 downto 0);
begin
end process;
----------------------------------------------------------------------
--- active API for Data Channel
----------------------------------------------------------------------
--- TRG_CHANNEL_API: trb_net16_api_base
--- generic map (
--- API_TYPE => c_API_ACTIVE,
--- FIFO_TO_INT_DEPTH => 6,
--- FIFO_TO_APL_DEPTH => 6,
--- FORCE_REPLY => 1,
--- SBUF_VERSION => 0,
--- USE_VENDOR_CORES => c_YES,
--- SECURE_MODE_TO_APL => c_YES,
--- SECURE_MODE_TO_INT => c_YES,
--- APL_WRITE_ALL_WORDS=> c_YES
--- )
--- port map (
--- -- Misc
--- CLK => CLK,
--- RESET => reset_i,
--- CLK_EN => '1',
--- -- APL Transmitter port
--- APL_DATA_IN => (others => '0'),
--- APL_PACKET_NUM_IN => "000",
--- APL_DATAREADY_IN => '0',
--- APL_READ_OUT => open,
--- APL_SHORT_TRANSFER_IN => '1',
--- APL_DTYPE_IN => CTS_TRG_TYPE_IN,
--- APL_ERROR_PATTERN_IN => trg_apl_error_pattern_in(31 downto 0),
--- APL_SEND_IN => CTS_TRG_SEND_IN,
--- APL_TARGET_ADDRESS_IN => (others => '0'),
--- -- Receiver port
--- APL_DATA_OUT => trg_apl_data_out(15 downto 0),
--- APL_PACKET_NUM_OUT=> trg_apl_packet_num_out(2 downto 0),
--- APL_TYP_OUT => trg_apl_typ_out(2 downto 0),
--- APL_DATAREADY_OUT => trg_apl_dataready_out,
--- APL_READ_IN => trg_apl_read_in,
--- -- APL Control port
--- APL_RUN_OUT => trg_apl_run_out,
--- APL_MY_ADDRESS_IN => my_address,
--- APL_SEQNR_OUT => open,
--- APL_LENGTH_IN => (others => '0'),
---
---
--- -- Internal direction port
--- INT_MASTER_DATAREADY_OUT => hub_init_dataready_in(2),
--- INT_MASTER_DATA_OUT => tmp_hub_init_data_in,
--- INT_MASTER_PACKET_NUM_OUT=> hub_init_packet_num_in(8 downto 6),
--- INT_MASTER_READ_IN => hub_init_read_out(2),
--- INT_MASTER_DATAREADY_IN => '0',
--- INT_MASTER_DATA_IN => (others => '0'),
--- INT_MASTER_PACKET_NUM_IN => "000",
--- INT_MASTER_READ_OUT => open,
--- INT_SLAVE_DATAREADY_OUT => open,
--- INT_SLAVE_DATA_OUT => open,
--- INT_SLAVE_PACKET_NUM_OUT => open,
--- INT_SLAVE_READ_IN => '1',
--- INT_SLAVE_DATAREADY_IN => hub_reply_dataready_out(2),
--- INT_SLAVE_DATA_IN => hub_reply_data_out(47 downto 32),
--- INT_SLAVE_PACKET_NUM_IN=> hub_reply_packet_num_out(8 downto 6),
--- INT_SLAVE_READ_OUT => hub_reply_read_in(2),
--- -- Status and control port
--- CTRL_SEQNR_RESET => common_ctrl(10),
--- STAT_FIFO_TO_INT => open,
--- STAT_FIFO_TO_APL => open
--- );
+
---------------------------------------------------------------------
---------------------------------------------------------------------
-- TrbNet Data Readout
---------------------------------------------------------------------
- trbnet_gen : if INCLUDE_READOUT = '1' generate
+ trbnet_gen : if INCLUDE_READOUT = 1 generate
- TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
+ TrbNetData : entity work.trb_net16_cri_response_constructor_TrbNetData
generic map(
RX_PATH_ENABLE => 0,
DO_SIMULATION => 0,
PS_DATA_IN => (others => '0'),
PS_WR_EN_IN => '0',
PS_ACTIVATE_IN => '0',
- PS_RESPONSE_READY_OUT => open,--resp_ready(3), -- TODO: make use of it
+ PS_RESPONSE_READY_OUT => open, -- TODO: make use of it
PS_BUSY_OUT => open,--busy(3), -- TODO: make use of it
PS_SELECTED_IN => '1',
PS_SRC_MAC_ADDRESS_IN => (others => '0'),
PS_DEST_UDP_PORT_IN => (others => '0'),
-- BEGIN TODO : Connect this to the ouside world. Now data is just thrown away
- TC_RD_EN_IN => '1',--TC_RD_EN_IN,
+ TC_RD_EN_IN => tc_rd_en,--'1',--TC_RD_EN_IN,
TC_DATA_OUT => open,--tc_data(4 * 9 - 1 downto 3 * 9),
TC_FRAME_SIZE_OUT => open,--tc_size(4 * 16 - 1 downto 3 * 16),
TC_FRAME_TYPE_OUT => open,--tc_type(4 * 16 - 1 downto 3 * 16),
STAT_DATA_OUT => open,
STAT_ADDR_OUT => open,
STAT_DATA_RDY_OUT => open,
- STAT_DATA_ACK_IN => '0',
+ STAT_DATA_ACK_IN => '0', -- not used in code
DEBUG_OUT => debug_resp_control,--MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
-- END OF INTERFACE
CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
CFG_AUTO_THROTTLE_IN => '0',
CFG_THROTTLE_PAUSE_IN => (others => '0'),
- MONITOR_SELECT_REC_OUT => open,--MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_REC_BYTES_OUT => open,--MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_BYTES_OUT => open,--MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_OUT => open,--MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_DROP_OUT_OUT => open,--MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_REC_OUT => open,
+ MONITOR_SELECT_REC_BYTES_OUT => open,
+ MONITOR_SELECT_SENT_BYTES_OUT => open,
+ MONITOR_SELECT_SENT_OUT => open,
+ MONITOR_SELECT_DROP_OUT_OUT => open,
MONITOR_SELECT_DROP_IN_OUT => open,
- DATA_HIST_OUT => open--DATA_HIST_OUT
+ DATA_HIST_OUT => open,--DATA_HIST_OUT
+
+ BUS_DBG_RX => BUS_DBG_RX,
+ BUS_DBG_TX => BUS_DBG_TX
);
+
+ THE_CRI_TRANSPORT_CONTROL_CONTROLER : process begin
+ wait until rising_edge(CLK);
+ if RESET = '1' then
+ --tc_rd_en <= '0';
+ else
+ -- if resp_ready = '1' then --maybe not good in timing; then maybe event_bytes != loaded_bytes for ever
+ -- tc_rd_en <= '1';
+ -- else
+ -- tc_rd_en <= '0'; --includes also busy state
+ -- end if;
+
+ if (debug_resp_control(35 downto 32) <= x"2") then
+ tc_rd_en <= '0';
+ else
+ tc_rd_en <= '1';
+ end if;
+
+ end if;
+ end process;
+
+
+---------------------------------------------------------------------
+-- active API for Data Channel
+---------------------------------------------------------------------
+-- TRG_CHANNEL_API: trb_net16_api_base
+-- generic map (
+-- API_TYPE => c_API_ACTIVE,
+-- FIFO_TO_INT_DEPTH => 6,
+-- FIFO_TO_APL_DEPTH => 6,
+-- FORCE_REPLY => 1,
+-- SBUF_VERSION => 6,
+-- USE_VENDOR_CORES => c_YES,
+-- SECURE_MODE_TO_APL => c_YES,
+-- SECURE_MODE_TO_INT => c_YES,
+-- APL_WRITE_ALL_WORDS=> c_NO
+-- )
+-- port map (
+-- -- Misc
+-- CLK => CLK,
+-- RESET => reset_i,
+-- CLK_EN => '1',
+-- -- APL Transmitter port
+-- APL_DATA_IN => (others => '0'),
+-- APL_PACKET_NUM_IN => "000",
+-- APL_DATAREADY_IN => '0', -- almostfullflag ; daten in fifo von 8 auf 16 bit packen
+-- APL_READ_OUT => open,
+-- APL_SHORT_TRANSFER_IN => '0',
+-- APL_DTYPE_IN => CTS_TRG_TYPE_IN,
+-- APL_ERROR_PATTERN_IN => trg_apl_error_pattern_in(31 downto 0),
+-- APL_SEND_IN => CTS_TRG_SEND_IN,
+-- APL_TARGET_ADDRESS_IN => (others => '0'),
+-- -- Receiver port
+-- APL_DATA_OUT => trg_apl_data_out(15 downto 0),
+-- APL_PACKET_NUM_OUT=> trg_apl_packet_num_out(2 downto 0),
+-- APL_TYP_OUT => trg_apl_typ_out(2 downto 0),
+-- APL_DATAREADY_OUT => trg_apl_dataready_out,
+-- APL_READ_IN => trg_apl_read_in,
+-- -- APL Control port
+-- APL_RUN_OUT => trg_apl_run_out,
+-- APL_MY_ADDRESS_IN => my_address,
+-- APL_SEQNR_OUT => open,
+-- APL_LENGTH_IN => (others => '0'),
+--
+--
+-- -- Internal direction port
+-- INT_MASTER_DATAREADY_OUT => cri_init_dataready_out,
+-- INT_MASTER_DATA_OUT => cri_init_data_out,
+-- INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out,
+-- INT_MASTER_READ_IN => cri_init_read_in,
+-- INT_MASTER_DATAREADY_IN => '0',
+-- INT_MASTER_DATA_IN => (others => '0'),
+-- INT_MASTER_PACKET_NUM_IN => "000",
+-- INT_MASTER_READ_OUT => open,
+-- INT_SLAVE_DATAREADY_OUT => open,
+-- INT_SLAVE_DATA_OUT => open,
+-- INT_SLAVE_PACKET_NUM_OUT => open,
+-- INT_SLAVE_READ_IN => '1',
+-- INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in,
+-- INT_SLAVE_DATA_IN => cri_reply_data_in,
+-- INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in,
+-- INT_SLAVE_READ_OUT => cri_reply_read_out,
+-- -- Status and control port
+-- CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
+-- STAT_FIFO_TO_INT => open,
+-- STAT_FIFO_TO_APL => open
+-- );
+
--iobuf on streaming api, towards CRI, data channel
-- THE_IOBUF_1 : trb_net16_iobuf
-- generic map(
-- IBUF_DEPTH => 6,
-- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
-- USE_CHECKSUM => cfg_USE_CHECKSUM(1),
--- INIT_CAN_SEND_DATA => c_NO,
+-- INIT_CAN_SEND_DATA => c_YES,
-- INIT_CAN_RECEIVE_DATA => c_YES,
-- REPLY_CAN_SEND_DATA => c_YES,
-- REPLY_CAN_RECEIVE_DATA => c_NO
--
-- -- Internal direction port
--
--- INT_INIT_DATAREADY_OUT => cts_init_dataready_out,
--- INT_INIT_DATA_OUT => cts_init_data_out,
--- INT_INIT_PACKET_NUM_OUT => cts_init_packet_num_out,
--- INT_INIT_READ_IN => cts_init_read_in,
+-- INT_INIT_DATAREADY_OUT => open,
+-- INT_INIT_DATA_OUT => open,
+-- INT_INIT_PACKET_NUM_OUT => open,
+-- INT_INIT_READ_IN => '1',
--
--- INT_INIT_DATAREADY_IN => '0',
--- INT_INIT_DATA_IN => (others => '0'),
--- INT_INIT_PACKET_NUM_IN => (others => '0'),
--- INT_INIT_READ_OUT => open,
+-- INT_INIT_DATAREADY_IN => cri_init_dataready_out,
+-- INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI
+-- INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out,
+-- INT_INIT_READ_OUT => cri_init_read_in,
--
--- INT_REPLY_DATAREADY_OUT => open,
--- INT_REPLY_DATA_OUT => open,
--- INT_REPLY_PACKET_NUM_OUT => open,
--- INT_REPLY_READ_IN => '1',
+-- INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in,
+-- INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI
+-- INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in,
+-- INT_REPLY_READ_IN => cri_reply_read_out,
--
--- INT_REPLY_DATAREADY_IN => cts_reply_dataready_in,
--- INT_REPLY_DATA_IN => cts_reply_data_in,
--- INT_REPLY_PACKET_NUM_IN => cts_reply_packet_num_in,
--- INT_REPLY_READ_OUT => cts_reply_read_out,
+-- INT_REPLY_DATAREADY_IN => '0',
+-- INT_REPLY_DATA_IN => (others => '0'),
+-- INT_REPLY_PACKET_NUM_IN => (others => '0'),
+-- INT_REPLY_READ_OUT => open,
--
-- -- Status and control port
-- STAT_GEN => open,
- no_readout_gen : if INCLUDE_READOUT = '0' generate
+ no_readout_gen : if INCLUDE_READOUT = 0 generate
-- terminate data channel if no readout
THE_IOBUF_1 : trb_net16_term_buf
port map (
START_CONFIG_OUT => open,
BANK_SELECT_OUT => open,
CONFIG_DONE_IN => '1',
- DATA_GBE_ENABLE_IN => '1',
- DATA_IPU_ENABLE_IN => '0', -- never used in code
- MULT_EVT_ENABLE_IN => '0',
- MAX_SUBEVENT_SIZE_IN => x"ffff",
- MAX_QUEUE_SIZE_IN => x"ffff",
- MAX_SUBS_IN_QUEUE_IN => x"ffff",
- MAX_SINGLE_SUB_SIZE_IN => x"ffff",
- READOUT_CTR_IN => x"000000",
- READOUT_CTR_VALID_IN => '0',
+ DATA_GBE_ENABLE_IN => cfg_gbe_enable,
+ DATA_IPU_ENABLE_IN => cfg_ipu_enable, -- never used in code
+ MULT_EVT_ENABLE_IN => cfg_mult_enable,
+ MAX_SUBEVENT_SIZE_IN => cfg_max_sub,
+ MAX_QUEUE_SIZE_IN => cfg_max_queue,
+ MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ MAX_SINGLE_SUB_SIZE_IN => cfg_max_single_sub,
+ READOUT_CTR_IN => cfg_readout_ctr,
+ READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
CFG_AUTO_THROTTLE_IN => '0',
CFG_THROTTLE_PAUSE_IN => (others => '0'),
-- PacketConstructor interface
- PC_WR_EN_OUT => open,
- PC_DATA_OUT => open,
+ PC_WR_EN_OUT => dbg_pc_wr_en,
+ PC_DATA_OUT => dbg_pc_data,
PC_READY_IN => '1',
- PC_SOS_OUT => open,
- PC_EOS_OUT => open,
- PC_EOQ_OUT => open,
- PC_SUB_SIZE_OUT => open,
- PC_TRIG_NR_OUT => open,
- PC_TRIGGER_TYPE_OUT => open,
+ PC_SOS_OUT => dbg_pc_sos,
+ PC_EOS_OUT => dbg_pc_eos,
+ PC_EOQ_OUT => dbg_pc_eoq,
+ PC_SUB_SIZE_OUT => dbg_pc_sub_size,
+ PC_TRIG_NR_OUT => dbg_pc_trig_nr,
+ PC_TRIGGER_TYPE_OUT => dbg_pc_trig_type,
MONITOR_OUT => open,
DEBUG_OUT => open
);
);
+ debug_gen : if INCLUDE_READOUT = 0 generate
-THE_CTS_READOUT_FINISHED_CNT : process begin
- wait until rising_edge(CLK);
-
- if RESET = '1' then
- last_cts_readout_finished <= '0';
- last_cts_readout_start <= '0';
- readout_finished_cnt <= 0;
- readout_start_cnt <= 0;
- else
- last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT;
- last_cts_readout_start <= CTS_START_READOUT_IN;
- if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then
- readout_finished_cnt <= readout_finished_cnt + 1;
- end if;
-
- if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then
- readout_start_cnt <= readout_start_cnt + 1;
- end if;
- end if;
-end process;
-
-
-THE_CRI_READOUT_DEBUG : process begin
- wait until rising_edge(CLK);
- BUS_DBG_TX.ack <= '0';
- BUS_DBG_TX.nack <= '0';
- BUS_DBG_TX.unknown <= '0';
+ THE_CTS_READOUT_FINISHED_CNT : process begin
+ wait until rising_edge(CLK);
- if BUS_DBG_RX.read = '1' then
- if BUS_DBG_RX.addr(7 downto 0) = x"00" then
- BUS_DBG_TX.data <= debug_resp_control(31 downto 0);
- BUS_DBG_TX.ack <= '1';
+ if RESET = '1' then
+ last_cts_readout_finished <= '0';
+ last_cts_readout_start <= '0';
+
+ last_dbg_pc_wr_en <= '0';
+ last_dbg_pc_sos <= '0';
+ last_dbg_pc_eos <= '0';
+ last_dbg_pc_eoq <= '0';
+
+ readout_finished_cnt <= 0;
+ readout_start_cnt <= 0;
+
+ dbg_pc_wr_en_cnt <= 0;
+ dbg_pc_sos_cnt <= 0;
+ dbg_pc_eos_cnt <= 0;
+ dbg_pc_eoq_cnt <= 0;
+ else
+ last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT;
+ last_cts_readout_start <= CTS_START_READOUT_IN;
+ if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then
+ readout_finished_cnt <= readout_finished_cnt + 1;
+ end if;
+
+ if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then
+ readout_start_cnt <= readout_start_cnt + 1;
+ end if;
+
+ -------------------
+
+ last_dbg_pc_wr_en <= dbg_pc_wr_en;
+ if ((dbg_pc_wr_en and (not last_dbg_pc_wr_en)) = '1') then
+ dbg_pc_wr_en_cnt <= dbg_pc_wr_en_cnt + 1;
+ end if;
+
+ last_dbg_pc_sos <= dbg_pc_sos;
+ if ((dbg_pc_sos and (not last_dbg_pc_sos)) = '1') then
+ dbg_pc_sos_cnt <= dbg_pc_sos_cnt + 1;
+ end if;
+
+ last_dbg_pc_eos <= dbg_pc_eos;
+ if ((dbg_pc_eos and (not last_dbg_pc_eos)) = '1') then
+ dbg_pc_eos_cnt <= dbg_pc_eos_cnt + 1;
+ end if;
+
+ last_dbg_pc_eoq <= dbg_pc_eoq;
+ if ((dbg_pc_eoq and (not last_dbg_pc_eoq)) = '1') then
+ dbg_pc_eoq_cnt <= dbg_pc_eoq_cnt + 1;
+ end if;
+
+ -------------------
end if;
+ end process;
+
+
+ THE_CRI_READOUT_DEBUG : process begin
+ wait until rising_edge(CLK);
+ BUS_DBG_TX.ack <= '0';
+ BUS_DBG_TX.nack <= '0';
+ BUS_DBG_TX.unknown <= '0';
- if BUS_DBG_RX.addr(7 downto 0) = x"01" then
- BUS_DBG_TX.data <= debug_resp_control(63 downto 32);
+ if BUS_DBG_RX.read = '1' then
+ if BUS_DBG_RX.addr(7 downto 0) = x"00" then
+ BUS_DBG_TX.data <= debug_resp_control(31 downto 0);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"01" then
+ BUS_DBG_TX.data <= debug_resp_control(63 downto 32);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"02" then
+ BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN;
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"03" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt);
+ BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable;
+ BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable;
+ BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable;
+ BUS_DBG_TX.data(31 downto 28) <= "0000";
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"04" then
+ BUS_DBG_TX.data(7 downto 0) <= dbg_pc_data;
+ BUS_DBG_TX.data(15 downto 8) <= x"00";
+ BUS_DBG_TX.data(19 downto 16) <= dbg_pc_trig_type;
+ BUS_DBG_TX.data(23 downto 20) <= x"0";
+ BUS_DBG_TX.data(24) <= dbg_pc_wr_en;
+ BUS_DBG_TX.data(25) <= dbg_pc_sos;
+ BUS_DBG_TX.data(26) <= dbg_pc_eos;
+ BUS_DBG_TX.data(27) <= dbg_pc_eoq;
+ BUS_DBG_TX.data(31 downto 28) <= x"0";
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"05" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_wr_en_cnt);
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_sos_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"06" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_eos_cnt);
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_eoq_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ elsif BUS_DBG_RX.write = '1' then
+ --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
+ -- MUX_cal_sw <= BUS_DBG_RX.data(0);
+ --end if;
BUS_DBG_TX.ack <= '1';
end if;
+ end process;
+ end generate debug_gen;
- if BUS_DBG_RX.addr(7 downto 0) = x"02" then
- BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN;
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"03" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt);
- BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable;
- BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable;
- BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable;
- BUS_DBG_TX.data(31 downto 28) <= "0000";
- BUS_DBG_TX.ack <= '1';
- end if;
-
- elsif BUS_DBG_RX.write = '1' then
- --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
- -- MUX_cal_sw <= BUS_DBG_RX.data(0);
- --end if;
- BUS_DBG_TX.ack <= '1';
- end if;
- end process;
-
end architecture;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+entity trb_net16_cri_response_constructor_TrbNetData is
+ generic(
+ RX_PATH_ENABLE : integer range 0 to 1 := 1;
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ READOUT_BUFFER_SIZE : integer range 1 to 4 := 1
+ );
+ port(
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+ -- INTERFACE
+ MY_MAC_IN : in std_logic_vector(47 downto 0);
+ MY_IP_IN : in std_logic_vector(31 downto 0);
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+ DEBUG_OUT : out std_logic_vector(63 downto 0);
+ -- END OF INTERFACE
+
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ -- ip configurator
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ CFG_GBE_ENABLE_IN : in std_logic;
+ CFG_IPU_ENABLE_IN : in std_logic;
+ CFG_MULT_ENABLE_IN : in std_logic;
+ CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
+ CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
+ CFG_READOUT_CTR_VALID_IN : in std_logic;
+ CFG_INSERT_TTYPE_IN : in std_logic;
+ CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_AUTO_THROTTLE_IN : in std_logic;
+ CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+ MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0);
+ DATA_HIST_OUT : out hist_array;
+
+ BUS_DBG_RX : in CTRLBUS_RX;
+ BUS_DBG_TX : out CTRLBUS_TX
+ );
+end trb_net16_cri_response_constructor_TrbNetData;
+
+architecture trb_net16_cri_response_constructor_TrbNetData of trb_net16_cri_response_constructor_TrbNetData is
+ attribute syn_encoding : string;
+
+ signal ip_cfg_start : std_logic;
+ signal ip_cfg_bank : std_logic_vector(3 downto 0);
+ signal ip_cfg_done : std_logic;
+ signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
+ signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
+ signal ip_cfg_mem_clk : std_logic;
+
+ signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0);
+ signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0);
+ signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0);
+ signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0);
+ signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0);
+ signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0);
+
+ signal pc_wr_en : std_logic;
+ signal pc_data : std_logic_vector(7 downto 0);
+ signal pc_eoq : std_logic;
+ signal pc_sos : std_logic;
+ signal pc_ready : std_logic;
+ signal pc_sub_size : std_logic_vector(31 downto 0);
+ signal pc_trig_nr : std_logic_vector(31 downto 0);
+ signal pc_eos : std_logic;
+
+ signal tc_rd_en : std_logic;
+ signal tc_data : std_logic_vector(8 downto 0);
+ signal tc_size : std_logic_vector(15 downto 0);
+ signal tc_sod : std_logic;
+ signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0);
+
+ type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP);
+ signal dissect_current_state, dissect_next_state : dissect_states;
+ attribute syn_encoding of dissect_current_state : signal is "onehot";
+
+ signal event_bytes : std_logic_vector(15 downto 0);
+ signal loaded_bytes : std_logic_vector(15 downto 0);
+ signal sent_packets : std_logic_vector(15 downto 0);
+
+ signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0);
+ signal ipu_dbg : std_logic_vector(383 downto 0);
+ signal constr_dbg : std_logic_vector(63 downto 0);
+
+ signal hist_inst : hist_array;
+ signal tc_sod_flag : std_logic;
+ signal reset_all_hist : std_logic_vector(31 downto 0);
+ signal ipu_monitor : std_logic_vector(223 downto 0);
+
+ -- JUST FOR DEBUGING PURPOSE
+ type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP);
+ signal sim_check_current, sim_check_next : sim_check_states;
+
+ signal hdr, tlr : std_logic_vector(255 downto 0);
+
+ --debug
+ signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0);
+ signal last_cts_readout_finished, last_cts_readout_start : std_logic;
+
+ signal last_pc_wr_en : std_logic;
+ signal last_pc_sos : std_logic;
+ signal last_pc_eos : std_logic;
+ signal last_pc_eoq : std_logic;
+
+ signal pc_wr_en_cnt : unsigned(15 downto 0);
+ signal pc_sos_cnt : unsigned(15 downto 0);
+ signal pc_eos_cnt : unsigned(15 downto 0);
+ signal pc_eoq_cnt : unsigned(15 downto 0);
+
+ signal constr_state_cnt : unsigned(15 downto 0);
+ signal constr_state_sub_cnt : unsigned(15 downto 0);
+ signal last_constr_state : std_logic_vector(3 downto 0);
+
+begin
+ sim_check_gen : if DO_SIMULATION = 1 generate
+ process(RESET, CLK)
+ begin
+ if RESET = '1' then
+ sim_check_current <= IDLE;
+ elsif rising_edge(CLK) then
+ sim_check_current <= sim_check_next;
+ end if;
+ end process;
+
+ process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes)
+ begin
+ case (sim_check_current) is
+ when IDLE =>
+ if (tc_sod = '1') then
+ sim_check_next <= SAVE_HDR;
+ else
+ sim_check_next <= IDLE;
+ end if;
+
+ when SAVE_HDR =>
+ if (loaded_bytes = x"001f" + x"0002") then
+ sim_check_next <= GO_OVER_DATA;
+ else
+ sim_check_next <= SAVE_HDR;
+ end if;
+
+ when GO_OVER_DATA =>
+ if (loaded_bytes = tc_size + x"0001") then
+ sim_check_next <= SAVE_TLR;
+ else
+ sim_check_next <= GO_OVER_DATA;
+ end if;
+
+ when SAVE_TLR =>
+ if (loaded_bytes = event_bytes) then
+ sim_check_next <= GET_ONE_MORE;
+ else
+ sim_check_next <= SAVE_TLR;
+ end if;
+
+ when GET_ONE_MORE =>
+ sim_check_next <= GET_SECOND_MORE;
+
+ when GET_SECOND_MORE =>
+ sim_check_next <= CLEANUP;
+
+ when CLEANUP =>
+
+ --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure;
+
+ sim_check_next <= IDLE;
+
+ end case;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then
+ hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0);
+ else
+ hdr <= hdr;
+ end if;
+ end if;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (sim_check_current = SAVE_TLR) then
+ tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0);
+ elsif (sim_check_current = GET_ONE_MORE) then
+ tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0);
+ elsif (sim_check_current = GET_ONE_MORE) then
+ tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0);
+ else
+ tlr <= tlr;
+ end if;
+ end if;
+ end process;
+
+ end generate sim_check_gen;
+
+-- THE_IP_CONFIGURATOR : ip_configurator
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET,
+-- -- configuration interface
+-- START_CONFIG_IN => ip_cfg_start,
+-- BANK_SELECT_IN => ip_cfg_bank,
+-- CONFIG_DONE_OUT => ip_cfg_done,
+-- MEM_ADDR_OUT => ip_cfg_mem_addr,
+-- MEM_DATA_IN => ip_cfg_mem_data,
+-- MEM_CLK_OUT => ip_cfg_mem_clk,
+-- -- information for IP cores
+-- DEST_MAC_OUT => ic_dest_mac,
+-- DEST_IP_OUT => ic_dest_ip,
+-- DEST_UDP_OUT => ic_dest_udp,
+-- SRC_MAC_OUT => ic_src_mac,
+-- SRC_IP_OUT => ic_src_ip,
+-- SRC_UDP_OUT => ic_src_udp,
+-- MTU_OUT => open,
+-- -- Debug
+-- DEBUG_OUT => open
+-- );
+--
+-- MB_IP_CONFIG : slv_mac_memory
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET,
+-- BUSY_IN => '0',
+-- -- Slave bus
+-- SLV_ADDR_IN => SLV_ADDR_IN,
+-- SLV_READ_IN => SLV_READ_IN,
+-- SLV_WRITE_IN => SLV_WRITE_IN,
+-- SLV_BUSY_OUT => SLV_BUSY_OUT,
+-- SLV_ACK_OUT => SLV_ACK_OUT,
+-- SLV_DATA_IN => SLV_DATA_IN,
+-- SLV_DATA_OUT => SLV_DATA_OUT,
+-- -- I/O to the backend
+-- MEM_CLK_IN => ip_cfg_mem_clk,
+-- MEM_ADDR_IN => ip_cfg_mem_addr,
+-- MEM_DATA_OUT => ip_cfg_mem_data,
+-- -- Status lines
+-- STAT => open
+-- );
+
+ THE_IPU_INTERFACE : entity work.trb_net16_gbe_ipu_interface
+ generic map(
+ DO_SIMULATION => DO_SIMULATION
+ )
+ port map(
+ CLK_IPU => CLK,
+ CLK_GBE => CLK,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => ip_cfg_start, -- just to shift Trigger for packer
+ BANK_SELECT_OUT => ip_cfg_bank, -- not used
+ CONFIG_DONE_IN => ip_cfg_done, -- just to shift Trigger for packer
+ DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
+ DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
+ MULT_EVT_ENABLE_IN => CFG_MULT_ENABLE_IN,
+ MAX_SUBEVENT_SIZE_IN => CFG_MAX_SUB_IN,
+ MAX_QUEUE_SIZE_IN => CFG_MAX_QUEUE_IN,
+ MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
+ MAX_SINGLE_SUB_SIZE_IN => CFG_MAX_SINGLE_SUB_IN,
+ READOUT_CTR_IN => CFG_READOUT_CTR_IN,
+ READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
+ CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => pc_wr_en,
+ PC_DATA_OUT => pc_data,
+ PC_READY_IN => pc_ready,
+ PC_SOS_OUT => pc_sos,
+ PC_EOS_OUT => pc_eos,
+ PC_EOQ_OUT => pc_eoq,
+ PC_SUB_SIZE_OUT => pc_sub_size,
+ PC_TRIG_NR_OUT => pc_trig_nr,
+ PC_TRIGGER_TYPE_OUT => pc_trig_type,
+ MONITOR_OUT => ipu_monitor,
+ DEBUG_OUT => ipu_dbg
+ );
+
+ MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0);
+
+ PACKET_CONSTRUCTOR : entity work.trb_net16_gbe_event_constr
+ generic map(
+ READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
+ DO_SIMULATION => DO_SIMULATION
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ PC_WR_EN_IN => pc_wr_en,
+ PC_DATA_IN => pc_data,
+ PC_READY_OUT => pc_ready,
+ PC_START_OF_SUB_IN => pc_sos,
+ PC_END_OF_SUB_IN => pc_eos,
+ PC_END_OF_QUEUE_IN => pc_eoq,
+ PC_SUB_SIZE_IN => pc_sub_size,
+ PC_DECODING_IN => CFG_SUBEVENT_DEC_IN,
+ PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN,
+ PC_TRIG_NR_IN => pc_trig_nr,
+ PC_TRIGGER_TYPE_IN => pc_trig_type_shift,
+ PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
+ PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
+ TC_RD_EN_IN => tc_rd_en,
+ TC_DATA_OUT => tc_data,
+ TC_EVENT_SIZE_OUT => tc_size,
+ TC_SOD_OUT => tc_sod,
+ DEBUG_OUT => constr_dbg
+ );
+
+ tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0';
+
+ DISSECT_MACHINE_PROC : process(RESET, CLK)
+ begin
+ if RESET = '1' then
+ dissect_current_state <= IDLE;
+ elsif rising_edge(CLK) then
+ dissect_current_state <= dissect_next_state;
+ end if;
+ end process DISSECT_MACHINE_PROC;
+
+ DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN)
+ begin
+ case dissect_current_state is
+ when IDLE =>
+ if (tc_sod = '1') then
+ dissect_next_state <= WAIT_FOR_LOAD;
+ else
+ dissect_next_state <= IDLE;
+ end if;
+
+ when WAIT_FOR_LOAD =>
+ if (PS_SELECTED_IN = '1') then
+ dissect_next_state <= LOAD;
+ else
+ dissect_next_state <= WAIT_FOR_LOAD;
+ end if;
+
+ when LOAD =>
+ if (event_bytes = loaded_bytes) then
+ dissect_next_state <= CLEANUP;
+ else
+ dissect_next_state <= LOAD;
+ end if;
+
+ when CLEANUP =>
+ dissect_next_state <= IDLE;
+
+ end case;
+ end process DISSECT_MACHINE;
+
+ PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
+ PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0';
+
+ TC_DATA_OUT <= tc_data;
+
+ EVENT_BYTES_PROC : process(clk) is
+ begin
+ if rising_edge(clk) then
+ if dissect_current_state = IDLE and tc_sod = '1' then
+ event_bytes <= tc_size + x"20"; -- adding termination bytes
+ else
+ event_bytes <= event_bytes;
+ end if;
+ end if;
+ end process EVENT_BYTES_PROC;
+
+ LOADED_BYTES_PROC : process(clk) is
+ begin
+ if rising_edge(clk) then
+ if (dissect_current_state = IDLE) then
+ loaded_bytes <= (others => '0');
+ elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then
+ loaded_bytes <= loaded_bytes + x"1";
+ else
+ loaded_bytes <= loaded_bytes;
+ end if;
+ end if;
+ end process LOADED_BYTES_PROC;
+
+ TC_FRAME_SIZE_OUT <= event_bytes;
+ TC_FRAME_TYPE_OUT <= x"0008";
+
+ TC_DEST_MAC_OUT <= x"c4e870211b00"; --ic_dest_mac;
+ TC_DEST_IP_OUT <= x"0300a8c0"; --ic_dest_ip;
+ TC_DEST_UDP_OUT <= x"c35c"; --ic_dest_udp;
+
+ --TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac;
+ --TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip;
+ --TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ ip_cfg_done <= '0';
+ if (ip_cfg_start = '1') then
+ ip_cfg_done <= '1';
+-- ic_dest_mac_shift <= ic_dest_mac;
+-- ic_dest_ip_shift <= ic_dest_ip;
+-- ic_dest_udp_shift <= ic_dest_udp;
+--
+-- ic_src_mac_shift <= ic_src_mac;
+-- ic_src_ip_shift <= ic_src_ip;
+-- ic_src_udp_shift <= ic_src_udp;
+
+ pc_trig_type_shift <= pc_trig_type;
+ else
+-- ic_dest_mac_shift <= ic_dest_mac_shift;
+-- ic_dest_ip_shift <= ic_dest_ip_shift;
+-- ic_dest_udp_shift <= ic_dest_udp_shift;
+--
+-- ic_src_mac_shift <= ic_src_mac_shift;
+-- ic_src_ip_shift <= ic_src_ip_shift;
+-- ic_src_udp_shift <= ic_src_udp_shift;
+
+ pc_trig_type_shift <= pc_trig_type_shift;
+ end if;
+ end if;
+ end process;
+
+ rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
+ TC_SRC_MAC_OUT <= MY_MAC_IN;
+ TC_SRC_IP_OUT <= MY_IP_IN;
+ end generate rx_enable_gen;
+
+ rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
+ TC_SRC_MAC_OUT <= MY_MAC_IN;
+ TC_SRC_IP_OUT <= ic_src_ip_shift;
+ end generate rx_disable_gen;
+
+ TC_SRC_UDP_OUT <= ic_src_udp_shift;
+ TC_IP_PROTOCOL_OUT <= x"11";
+ TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0);
+
+ SENT_PACKETS_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ sent_packets <= (others => '0');
+ elsif (dissect_current_state = IDLE and tc_sod = '1') then
+ sent_packets <= sent_packets + x"1";
+ end if;
+ end if;
+ end process SENT_PACKETS_PROC;
+
+ -- monitoring
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (tc_sod = '1' and tc_sod_flag = '0') then
+ tc_sod_flag <= '1';
+ elsif (tc_sod = '0') then
+ tc_sod_flag <= '0';
+ else
+ tc_sod_flag <= tc_sod_flag;
+ end if;
+ end if;
+ end process;
+
+ hist_ctrs_gen : for i in 0 to 31 generate
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ reset_all_hist(i) <= '1';
+ elsif (hist_inst(i) = x"ffff_ffff") then
+ reset_all_hist(i) <= '1';
+ else
+ reset_all_hist(i) <= '0';
+ end if;
+ end if;
+ end process;
+
+ HIST_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (reset_all_hist /= x"0000_0000") then
+ hist_inst(i) <= (others => '0');
+ elsif (tc_sod = '1' and tc_sod_flag = '0' and i = to_integer(unsigned(event_bytes(15 downto 11)))) then
+ hist_inst(i) <= hist_inst(i) + x"1";
+ else
+ hist_inst(i) <= hist_inst(i);
+ end if;
+ end if;
+ end process;
+ end generate hist_ctrs_gen;
+
+ DATA_HIST_OUT <= hist_inst;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ mon_sent_frames <= (others => '0');
+ elsif (dissect_current_state = LOAD and event_bytes = loaded_bytes) then
+ mon_sent_frames <= mon_sent_frames + x"1";
+ else
+ mon_sent_frames <= mon_sent_frames;
+ end if;
+ end if;
+ end process;
+ MONITOR_SELECT_SENT_OUT <= mon_sent_frames;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ mon_sent_bytes <= (others => '0');
+ elsif (tc_rd_en = '1') then
+ mon_sent_bytes <= mon_sent_bytes + x"1";
+ else
+ mon_sent_bytes <= mon_sent_bytes;
+ end if;
+ end if;
+ end process;
+
+ MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
+
+ MONITOR_SELECT_REC_BYTES_OUT <= (others => '0');
+ MONITOR_SELECT_REC_OUT <= (others => '0');
+
+ DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0);
+ DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0);
+
+
+THE_CTS_READOUT_FINISHED_CNT : process begin
+ wait until rising_edge(CLK);
+
+ if RESET = '1' then
+ last_cts_readout_finished <= '0';
+ last_cts_readout_start <= '0';
+
+ last_pc_wr_en <= '0';
+ last_pc_sos <= '0';
+ last_pc_eos <= '0';
+ last_pc_eoq <= '0';
+
+ readout_finished_cnt <= 0;
+ readout_start_cnt <= 0;
+
+ pc_wr_en_cnt <= 0;
+ pc_sos_cnt <= 0;
+ pc_eos_cnt <= 0;
+ pc_eoq_cnt <= 0;
+
+ constr_state_cnt <= 0;
+ constr_state_sub_cnt <= 0;
+
+ last_constr_state <= x"0";
+ else
+ last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT;
+ last_cts_readout_start <= CTS_START_READOUT_IN;
+ if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then
+ readout_finished_cnt <= readout_finished_cnt + 1;
+ end if;
+
+ if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then
+ readout_start_cnt <= readout_start_cnt + 1;
+ end if;
+
+ -------------------
+
+ last_pc_wr_en <= pc_wr_en;
+ if ((pc_wr_en and (not last_pc_wr_en)) = '1') then
+ pc_wr_en_cnt <= pc_wr_en_cnt + 1;
+ end if;
+
+ last_pc_sos <= pc_sos;
+ if ((pc_sos and (not last_pc_sos)) = '1') then
+ pc_sos_cnt <= pc_sos_cnt + 1;
+ end if;
+
+ last_pc_eos <= pc_eos;
+ if ((pc_eos and (not last_pc_eos)) = '1') then
+ pc_eos_cnt <= pc_eos_cnt + 1;
+ end if;
+
+ last_pc_eoq <= pc_eoq;
+ if ((pc_eoq and (not last_pc_eoq)) = '1') then
+ pc_eoq_cnt <= pc_eoq_cnt + 1;
+ end if;
+
+ last_constr_state <= constr_dbg(3 downto 0);
+ if (last_constr_state /= constr_dbg(3 downto 0)) then
+ constr_state_cnt <= constr_state_cnt + 1;
+ if (constr_dbg(3 downto 0) = x"2") then
+ constr_state_sub_cnt <= constr_state_sub_cnt + 1;
+ end if;
+ end if;
+
+
+ -------------------
+ end if;
+end process;
+
+
+THE_CRI_READOUT_DEBUG : process begin
+ wait until rising_edge(CLK);
+ BUS_DBG_TX.ack <= '0';
+ BUS_DBG_TX.nack <= '0';
+ BUS_DBG_TX.unknown <= '0';
+
+ if BUS_DBG_RX.read = '1' then
+ if BUS_DBG_RX.addr(7 downto 0) = x"00" then
+ BUS_DBG_TX.data <= ipu_dbg(31 downto 0);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"01" then
+ BUS_DBG_TX.data <= constr_dbg(31 downto 0);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"02" then
+ BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN;
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"03" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt);
+ BUS_DBG_TX.data(19 downto 16) <= "000" & CFG_GBE_ENABLE_IN;
+ BUS_DBG_TX.data(23 downto 20) <= "000" & CFG_IPU_ENABLE_IN;
+ BUS_DBG_TX.data(27 downto 24) <= "000" & CFG_MULT_ENABLE_IN;
+ BUS_DBG_TX.data(31 downto 28) <= "0000";
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"04" then
+ BUS_DBG_TX.data(7 downto 0) <= pc_data;
+ BUS_DBG_TX.data(15 downto 8) <= x"00";
+ BUS_DBG_TX.data(19 downto 16) <= pc_trig_type;
+ BUS_DBG_TX.data(23 downto 20) <= x"0";
+ BUS_DBG_TX.data(24) <= pc_wr_en;
+ BUS_DBG_TX.data(25) <= pc_sos;
+ BUS_DBG_TX.data(26) <= pc_eos;
+ BUS_DBG_TX.data(27) <= pc_eoq;
+ BUS_DBG_TX.data(31 downto 28) <= x"0";
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"05" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(pc_wr_en_cnt);
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(pc_sos_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"06" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(pc_eos_cnt);
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(pc_eoq_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"07" then
+ BUS_DBG_TX.data( 8 downto 0) <= tc_data;
+ BUS_DBG_TX.data(11 downto 9) <= (others => '0');
+ BUS_DBG_TX.data(15 downto 12) <= "000" & tc_sod;
+ BUS_DBG_TX.data(31 downto 16) <= tc_size;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ if BUS_DBG_RX.addr(7 downto 0) = x"08" then
+ BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(constr_state_cnt);
+ BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(constr_state_sub_cnt);
+ BUS_DBG_TX.ack <= '1';
+ end if;
+
+ elsif BUS_DBG_RX.write = '1' then
+ --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then
+ -- MUX_cal_sw <= BUS_DBG_RX.data(0);
+ --end if;
+ BUS_DBG_TX.ack <= '1';
+ end if;
+ end process;
+
+end trb_net16_cri_response_constructor_TrbNetData;
+
+
jspc29 / dirich.git / commitdiff