, output reg[3:0] mem_addr
, output reg[7:0] mem_wr_data
, input [7:0] mem_rd_data
-
);
//*****************
--- /dev/null
+// --------------------------------------------------------------------
+// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// --------------------------------------------------------------------
+// Copyright (c) 2001 - 2012 by Lattice Semiconductor Corporation
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code for use
+// in synthesis for any Lattice programmable logic product. Other
+// use of this code, including the selling or duplication of any
+// portion is strictly prohibited.
+//
+// Disclaimer:
+//
+// This verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Lattice Semiconductor provides no warranty
+// regarding the use or functionality of this code.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-268-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+// Code Revision History :
+// --------------------------------------------------------------------
+// Ver: | Author |Mod. Date |Changes Made:
+// V1.0 | Vijay |3/09/12 |Initial ver
+// V1.1 | SHossner|6/08/12 |Added READ_DELAY parameter
+//
+// --------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+`include "efb_define_def.v"
+//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v"
+//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v"
+
+module UFM_WB_I2C_Prog(
+ input clk_i
+ , input rst_n
+ , input[2:0] cmd
+ , input[15:0] ufm_page //changed to 16bit, IF
+ , input select_cfg //added, IF
+ , input GO
+ , output reg BUSY
+ , output reg ERR
+
+ /***************** DPRAM port B signals *************/
+ , output reg mem_clk
+ , output reg mem_we
+ , output reg mem_ce
+ , output reg[3:0] mem_addr
+ , output reg[7:0] mem_wr_data
+ , input [7:0] mem_rd_data
+ , inout i2c_scl
+ , inout i2c_sda
+ );
+
+ //*****************
+ // For clk_i speeds less than 16.6MHz, set READ_DELAY to zero for fastest UFM read operation
+ // For clk_i speeds greater than 16.6MHz, set READ_DELAY as follows:
+ // Calculate minimum READ_DELAY as follows:
+ // READ_DELAY(min) = 240/PERIOD - 4
+ // Where PERIOD = clk_i period in ns
+ // Example, for clk_i = 45MHz, PERIOD = 22.22ns and READ_DELAY = 7 (6.8 rounded up)
+ //
+ // Or choose from the following table:
+ // READ_DELAY | Max Clk_i
+ // ------------+-------------
+ // 0 | 16.6 Mhz
+ // 2 | 25.0 Mhz
+ // 4 | 33.3 Mhz
+ // 8 | 50.0 Mhz
+ // 12 | 66.6 Mhz
+ // 14 | 75.0 Mhz
+
+ parameter READ_DELAY = 4;
+ //*****************
+
+ wire ufm_enable_cmd;
+ wire ufm_read_cmd;
+ wire ufm_write_cmd;
+ wire ufm_erase_cmd;
+ wire ufm_disable_cmd;
+ reg ufm_enabled;
+ reg n_ufm_enabled;
+ wire ufm_repeated_read;
+ wire ufm_repeated_write;
+
+
+
+ reg [7:0] wb_dat_i ;
+ reg wb_stb_i ;
+ wire wb_cyc_i = wb_stb_i ;
+ reg [7:0] wb_adr_i ;
+ reg wb_we_i ;
+ wire [7:0] wb_dat_o ;
+ wire wb_ack_o ;
+
+ reg [7:0] n_wb_dat_i ;
+ reg n_wb_stb_i ;
+ reg [7:0] n_wb_adr_i ;
+ reg n_wb_we_i ;
+ reg n_busy;
+ reg n_error;
+ reg [7:0] c_state ,n_state;
+ reg efb_flag,n_efb_flag;
+ reg [7:0] sm_wr_data;
+ reg [3:0] sm_addr;
+ reg sm_ce;
+ reg sm_we;
+ reg [4:0] count;
+ reg sm_addr_MSB;
+ reg [7:0] sm_rd_data;
+
+
+ reg [7:0] n_data_frm_ufm;
+ reg [3:0] n_addr_ufm;
+ reg n_clk_en_ufm;
+ reg n_wr_en_ufm;
+ reg [4:0] n_count;
+ reg n_ufm_addr_MSB;
+
+ wire [7:0] cmd_read;
+ wire [7:0] cmd_erase;
+ wire [7:0] cmd_program;
+ wire [7:0] cmd_select_sector;
+ wire [12:0] real_address;
+
+
+ PUR PUR_INST (.PUR(1'b1));
+ GSR GSR_INST (.GSR(1'b1));
+
+ flash_I2C_Prog inst1 (
+ .wb_clk_i(clk_i ), // EFB with UFM enabled
+ .wb_rst_i(!rst_n ),
+ .wb_cyc_i(wb_cyc_i ),
+ .wb_stb_i(wb_stb_i ),
+ .wb_we_i(wb_we_i ),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i ),
+ .wb_dat_o(wb_dat_o ),
+ .wb_ack_o(wb_ack_o ),
+ .wbc_ufm_irq( ),
+ .i2c1_irqo( ),
+ .i2c1_scl(i2c_scl),
+ .i2c1_sda(i2c_sda)
+ );
+
+ // flashram inst2 ( .DataInA(sm_wr_data ), // True dual port RAM. Port A controlled by internal SM and port B controlled by user.
+ // .DataInB(mem_wr_data ),
+ // .AddressA({sm_addr_MSB,sm_addr} ),
+ // .AddressB({!sm_addr_MSB,mem_addr} ),
+ // .ClockA(clk_i ),
+ // .ClockB(mem_clk ),
+ // .ClockEnA(sm_ce ),
+ // .ClockEnB(mem_ce ),
+ // .WrA(sm_we ),
+ // .WrB(mem_we ),
+ // .ResetA(!rst_n ),
+ // .ResetB(!rst_n ),
+ // .QA(sm_rd_data ),
+ // .QB(mem_rd_data ));
+
+
+ always @ (*)
+ begin
+ sm_rd_data <= mem_rd_data;
+ mem_we <= sm_we;
+ mem_ce <= sm_ce;
+ mem_clk <= clk_i;
+ mem_addr <= sm_addr;
+ mem_wr_data <= sm_wr_data;
+ end
+
+ assign ufm_enable_cmd = (cmd == 3'b100) ? 1'b1 : 1'b0 ;
+ assign ufm_read_cmd = ((cmd == 3'b000) || (cmd == 3'b001)) ? 1'b1 : 1'b0 ;
+ assign ufm_write_cmd = ((cmd == 3'b010) || (cmd == 3'b011)) ? 1'b1 : 1'b0 ;
+ assign ufm_erase_cmd = (cmd == 3'b111) ? 1'b1 : 1'b0 ;
+ assign ufm_disable_cmd = (cmd == 3'b101) ? 1'b1 : 1'b0 ;
+ assign ufm_repeated_read = (cmd == 3'b001) ? 1'b1 : 1'b0 ;
+ assign ufm_repeated_write = (cmd == 3'b011) ? 1'b1 : 1'b0 ;
+
+
+
+ assign cmd_read = (select_cfg == 1'b0)? `CMD_UFM_READ : `CMD_CFG_READ ;
+ assign cmd_erase = (select_cfg == 1'b0)? `CMD_UFM_ERASE : `CMD_CFG_ERASE ;
+ assign cmd_program = (select_cfg == 1'b0)? `CMD_UFM_PROGRAM : `CMD_CFG_PROGRAM ;
+// assign real_address= (ufm_page[12:10] == 3'b111)? {3'b000,ufm_page[9:0]} : ufm_page ;
+ assign cmd_select_sector = (select_cfg == 1'b0)? 8'h40 : 8'h00 ;
+
+
+ always @ (posedge clk_i or negedge rst_n) // generate clk enable and write enable signals for port A of the DPRAM
+ begin
+ if(!rst_n)
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ else if (((c_state == `state58) && (n_state == `state59)) || ((c_state == `state51)))
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ else if ((n_state == `state58) || ((c_state == `state50) && (n_state == `state51)))
+ begin
+ sm_ce <= 1'b1;
+ if (ufm_read_cmd)
+ sm_we <= 1'b1;
+ else
+ sm_we <= 1'b0;
+ end
+ else
+ begin
+ sm_ce <= 1'b0;
+ sm_we <= 1'b0;
+ end
+ end
+
+
+ always @ (posedge clk_i or negedge rst_n)
+ begin
+ if(!rst_n)
+ begin
+ wb_dat_i <= 8'h00;
+ wb_stb_i <= 1'b0 ;
+ wb_adr_i <= 8'h00;
+ wb_we_i <= 1'b0;
+ end
+ else
+ begin
+ wb_dat_i <= n_wb_dat_i;
+ wb_stb_i <= #0.1 n_wb_stb_i;
+ wb_adr_i <= n_wb_adr_i;
+ wb_we_i <= n_wb_we_i ;
+
+ end
+ end
+
+ always @ (posedge clk_i or negedge rst_n)
+ begin
+ if(!rst_n) begin
+ c_state <= 10'h000;
+ BUSY <= 1'b1;
+ efb_flag <= 1'b0 ;
+ ERR <= 1'b0;
+ ufm_enabled <= 1'b0;
+ sm_wr_data <= 8'h00;
+ sm_addr <= 4'b0000;
+ count <= 4'hF;
+ sm_addr_MSB <= 1'b0;
+ end
+ else begin
+ c_state <= n_state ;
+ BUSY <= n_busy;
+ efb_flag <= n_efb_flag;
+ ERR <= n_error;
+ ufm_enabled <= n_ufm_enabled;
+ sm_wr_data <= n_data_frm_ufm;
+ sm_addr <= n_addr_ufm;
+ count <= n_count;
+ sm_addr_MSB <= n_ufm_addr_MSB;
+ end
+ end
+
+
+
+ always @ (*)
+ begin
+ n_state = c_state;
+ n_efb_flag = 1'b0 ;
+ n_busy = BUSY;
+ n_error = ERR;
+ n_ufm_enabled = ufm_enabled;
+ n_data_frm_ufm = sm_wr_data;
+ n_addr_ufm = sm_addr;
+ n_clk_en_ufm = sm_ce;
+ n_wr_en_ufm = sm_we;
+ n_count = count;
+ n_ufm_addr_MSB = sm_addr_MSB;
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_efb_flag = `LOW ;
+ case (c_state)
+
+ `state0 : begin
+ n_busy = 1'b1;
+ n_error = 1'b0;
+ n_ufm_enabled = 1'b0;
+ n_state = `state1; // (state1 - state8)--check if UFM is busy and deassert BUSY flag if free.
+ end
+
+ `state1: begin // enable WB-UFM interface
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state2;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ end
+ end
+
+
+ `state2: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state3;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_CHECK_BUSY_FLAG;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ end
+ end
+
+
+ `state3: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state4;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ end
+ end
+
+
+ `state4: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state5;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state5: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state6;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ end
+ end
+
+
+ `state6: begin // Return Back to State 2
+ if (wb_ack_o && efb_flag) begin
+ if(wb_dat_o & (8'h80) )
+ n_state = `state7;
+ else
+ n_state = `state8;
+ end
+ else begin
+ n_wb_we_i = `READ_STATUS;
+ n_wb_adr_i = `CFGRXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_efb_flag = 1'b1 ;
+ end
+ end
+
+ `state7: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state1;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ end
+ end
+
+ `state8: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_busy = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ end
+ end
+
+ `state9: begin
+ if (GO)
+ begin
+ n_busy = 1'b1;
+ n_error = 1'b0;
+ if (ufm_enabled && ufm_write_cmd)
+ n_ufm_addr_MSB = !sm_addr_MSB;
+ n_state = `state10;
+ end
+ else
+ begin
+ n_wb_dat_i = `ALL_ZERO ;
+ n_wb_adr_i = `ALL_ZERO ;
+ n_wb_we_i = `LOW ;
+ n_wb_stb_i = `LOW ;
+ n_busy = 1'b0;
+ n_error = ERR;
+ end
+ end
+
+
+ `state10: begin
+ if(ufm_enable_cmd) // enable UFM
+ n_state = `state11;
+ else if (ufm_enabled)begin // decode command only if UFM is already enabled
+ if (ufm_read_cmd)
+ n_state = `state35;
+ else if (ufm_write_cmd)
+ n_state = `state35;
+ else if (ufm_erase_cmd)
+ n_state = `state17;
+ else if (ufm_disable_cmd)
+ n_state = `state23;
+ end
+ else begin // set ERR if a command is sent when UFM is disabled and go to previous state and wait for GO
+ n_busy = 1'b0;
+ n_error = 1'b1;
+ n_state = `state9;
+ end
+ end
+
+ `state11: begin // (state11 - state16) enable UFM
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state12;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state12: begin // enable configuration
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state13;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_ENABLE_INTERFACE;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state13: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state14;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h08;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state14: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state15;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state15: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state16;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state16: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_ufm_enabled = 1'b1;
+ n_state = `state1; // check for busy flag after enabling UFM
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ n_ufm_enabled = 1'b0;
+ end
+ end
+
+
+ `state17: begin // (state17- state22) erase UFM
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state18;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state18: begin
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state19;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = cmd_erase;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state19: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state20;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h04; //JM added for 0xE to erase CFG Flash
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state20: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state21;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state21: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state22;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state22: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state1; // check for busy flag after erasing UFM
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state23: begin // open frame // (state23 - state 32) disable UFM
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state24;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_efb_flag = 1'b1 ;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state24: begin // disable configuration
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state25;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_DISABLE_INTERFACE;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state25: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state26;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state26: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state27;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state27: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state28;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+ `state28: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state29;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state29: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state30;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+ `state30: begin // bypass command
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state31;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_BYPASS;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state31: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state32;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_BYPASS;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state32: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state33;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_BYPASS;
+ n_efb_flag = 1'b1 ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state33: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state34;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_BYPASS;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state34: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_busy = 1'b0;
+ n_ufm_enabled = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state35: begin // (state35 - state60 ) UFM read/write operations
+ if (wb_ack_o && efb_flag) begin
+ if (ufm_repeated_read)
+ n_state = `state46;
+ else if (ufm_repeated_write)
+ n_state = `state54;
+ else
+ n_state = `state36;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h80;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state36: begin // Set UFM Page Address
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state37;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = `CMD_SET_ADDRESS;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state37: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state38;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state38: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state39;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state39: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state40;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state40: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state41;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = cmd_select_sector;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state41: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state42;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state42: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state43;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ // n_wb_dat_i = {3'b000,real_address[12:8]};
+ n_wb_dat_i = ufm_page[15:8] ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state43: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state44;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ // n_wb_dat_i = real_address[7:0];
+ n_wb_dat_i = ufm_page[7:0] ;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state44: begin //
+ if (wb_ack_o && efb_flag) begin
+ if (ufm_write_cmd)
+ n_state = `state53;
+ else
+ n_state = `state45;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state45: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state46;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state46: begin // Read Operation
+ if (wb_ack_o && efb_flag) begin
+ n_count = READ_DELAY;
+ n_state = `stateRD_delay;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = cmd_read;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `stateRD_delay: begin
+ if (count == 0)
+ n_state = `state47;
+ else begin
+ n_count = count - 1;
+ end
+ end
+
+ `state47: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state48;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h10;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state48: begin //
+ if (wb_ack_o && efb_flag)
+ n_state = `state49;
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state49: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_count = 5'b10000;
+ n_addr_ufm = 4'h0;
+ n_clk_en_ufm = 1'b1;
+ n_state = `state50;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h01;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state50: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_count = count - 1;
+ n_data_frm_ufm = wb_dat_o;
+ n_state = `state51;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `READ_DATA;
+ n_wb_adr_i = `CFGRXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state51: begin //
+ n_addr_ufm = sm_addr + 1;
+ if (count == 0)
+ n_state = `state52;
+ else begin
+ n_state = `state50;
+ end
+ end
+
+
+ `state52: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_ufm_addr_MSB = !sm_addr_MSB;
+ n_busy = 1'b0;
+ n_state = `state9;
+ end
+ else begin
+ n_wb_we_i = `WRITE;
+ n_efb_flag = 1'b1 ;
+ n_wb_adr_i = `CFGCR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ n_busy = 1'b1;
+ end
+ end
+
+ `state53: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state54;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h80;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+ `state54: begin // Write Operation
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state55;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = cmd_program;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state55: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state56;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state56: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state57;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h00;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state57: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_count = 5'b10000;
+ n_addr_ufm = 4'h0;
+ n_clk_en_ufm = 1'b1;
+ n_wr_en_ufm = 1'b0;
+ n_state = `state58;
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = 8'h01;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+
+ `state58: begin //
+ n_count = count - 1;
+ n_state = `state59;
+ end
+
+ `state59: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_addr_ufm = sm_addr + 1;
+ if (count == 0)
+ n_state = `state60;
+ else begin
+ n_state = `state58;
+ end
+ end
+ else begin
+ n_efb_flag = `HIGH ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGTXDR;
+ n_wb_dat_i = sm_rd_data;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+
+ `state60: begin //
+ if (wb_ack_o && efb_flag) begin
+ n_state = `state1;
+ end
+ else begin
+ n_efb_flag = 1'b1 ;
+ n_wb_we_i = `WRITE;
+ n_wb_adr_i = `CFGCR ;
+ n_wb_dat_i = 8'h00;
+ n_busy = 1'b1;
+ n_wb_stb_i = `HIGH ;
+ end
+ end
+ endcase
+ end
+
+
+
+endmodule
+
+
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 09 29 10:00:22.906" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 01 03 11:06:23.144" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="flash.lpc" type="lpc" modified="2016 09 29 10:00:20.000"/>
- <File name="flash.vhd" type="top_level_vhdl" modified="2016 09 29 10:00:20.000"/>
- <File name="flash_tmpl.vhd" type="template_vhdl" modified="2016 09 29 10:00:20.000"/>
+ <File name="flash.lpc" type="lpc" modified="2020 01 03 11:06:21.000"/>
+ <File name="flash.vhd" type="top_level_vhdl" modified="2020 01 03 11:06:21.000"/>
+ <File name="flash_tmpl.vhd" type="template_vhdl" modified="2020 01 03 11:06:21.000"/>
</Package>
</DiamondModule>
[Device]
Family=machxo3lf
-PartType=LCMXO3LF-2100E
-PartName=LCMXO3LF-2100E-5UWG49CTR
+PartType=LCMXO3LF-4300E
+PartName=LCMXO3LF-4300E-5UWG81CTR
SpeedGrade=5
-Package=WLCSP49
+Package=WLCSP81
OperatingCondition=COM
Status=S
ModuleName=flash
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=09/29/2016
-Time=10:00:20
+Date=01/03/2020
+Time=11:06:21
[Parameters]
Verilog=0
ufm=1
wb_clk_freq=33.33
ufm_usage=SHARED_EBR_TAG
-ufm_ebr=629
+ufm_ebr=757
ufm_remain=
mem_size=10
ufm_start=
wb=1
[Command]
-cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100
+cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 757 -mem_size 10 -ufm_0 -wb -dev 4300
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119
-- Module Version: 1.2
---/opt/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100
+--/home/soft/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 757 -mem_size 10 -ufm_0 -wb -dev 4300
--- Thu Sep 29 10:00:20 2016
+-- Fri Jan 3 11:06:21 2020
library IEEE;
use IEEE.std_logic_1164.all;
EFBInst_0: EFB
generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
- UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 0,
- UFM_INIT_PAGES=> 0, DEV_DENSITY=> "2100L", EFB_UFM=> "ENABLED",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 757,
+ UFM_INIT_PAGES=> 10, DEV_DENSITY=> "4300L", EFB_UFM=> "ENABLED",
TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="flash_I2C_Prog" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 01 03 11:06:05.631" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="flash_I2C_Prog.lpc" type="lpc" modified="2020 01 03 11:05:54.000"/>
+ <File name="flash_I2C_Prog.vhd" type="top_level_vhdl" modified="2020 01 03 11:05:54.000"/>
+ <File name="flash_I2C_Prog_tmpl.vhd" type="template_vhdl" modified="2020 01 03 11:05:54.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-4300E
+PartName=LCMXO3LF-4300E-5UWG81CTR
+SpeedGrade=5
+Package=WLCSP81
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=flash_I2C_Prog
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=01/03/2020
+Time=11:05:54
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=1
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+wb_clk_freq=33.33
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=757
+ufm_remain=
+mem_size=10
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+wb=1
+
+[Command]
+cmd_line= -w -n flash_I2C_Prog -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -i2c1config -i2c1_freq 100 -i2c1_sa 1000001 -i2c1_addr 7 -ufm -ufm_ebr 757 -mem_size 10 -ufm_0 -wb -dev 4300
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119
+-- Module Version: 1.2
+--/home/soft/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n flash_I2C_Prog -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -i2c1config -i2c1_freq 100 -i2c1_sa 1000001 -i2c1_addr 7 -ufm -ufm_ebr 757 -mem_size 10 -ufm_0 -wb -dev 4300
+
+-- Fri Jan 3 11:05:54 2020
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity flash_I2C_Prog is
+ port (
+ wb_clk_i: in std_logic;
+ wb_rst_i: in std_logic;
+ wb_cyc_i: in std_logic;
+ wb_stb_i: in std_logic;
+ wb_we_i: in std_logic;
+ wb_adr_i: in std_logic_vector(7 downto 0);
+ wb_dat_i: in std_logic_vector(7 downto 0);
+ wb_dat_o: out std_logic_vector(7 downto 0);
+ wb_ack_o: out std_logic;
+ i2c1_scl: inout std_logic;
+ i2c1_sda: inout std_logic;
+ i2c1_irqo: out std_logic;
+ wbc_ufm_irq: out std_logic);
+end flash_I2C_Prog;
+
+architecture Structure of flash_I2C_Prog is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal i2c1_sdaoen: std_logic;
+ signal i2c1_sdao: std_logic;
+ signal i2c1_scloen: std_logic;
+ signal i2c1_sclo: std_logic;
+ signal i2c1_sdai: std_logic;
+ signal i2c1_scli: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component BB
+ port (I: in std_logic; T: in std_logic; O: out std_logic;
+ B: inout std_logic);
+ end component;
+ component EFB
+ generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
+ EFB_SPI : in String; EFB_TC : in String;
+ EFB_TC_PORTMODE : in String; EFB_UFM : in String;
+ EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
+ UFM_INIT_PAGES : in Integer;
+ UFM_INIT_START_PAGE : in Integer;
+ UFM_INIT_ALL_ZEROS : in String;
+ UFM_INIT_FILE_NAME : in String;
+ UFM_INIT_FILE_FORMAT : in String;
+ I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
+ I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
+ I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
+ I2C1_CLK_DIVIDER : in Integer;
+ I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
+ I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
+ I2C2_WAKEUP : in String; SPI_MODE : in String;
+ SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
+ SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
+ SPI_SLAVE_HANDSHAKE : in String;
+ SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
+ SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
+ SPI_WAKEUP : in String; TC_MODE : in String;
+ TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
+ GSR : in String; TC_TOP_SET : in Integer;
+ TC_OCR_SET : in Integer; TC_OC_MODE : in String;
+ TC_RESETN : in String; TC_TOP_SEL : in String;
+ TC_OV_INT : in String; TC_OCR_INT : in String;
+ TC_ICR_INT : in String; TC_OVERFLOW : in String;
+ TC_ICAPTURE : in String);
+ port (WBCLKI: in std_logic; WBRSTI: in std_logic;
+ WBCYCI: in std_logic; WBSTBI: in std_logic;
+ WBWEI: in std_logic; WBADRI7: in std_logic;
+ WBADRI6: in std_logic; WBADRI5: in std_logic;
+ WBADRI4: in std_logic; WBADRI3: in std_logic;
+ WBADRI2: in std_logic; WBADRI1: in std_logic;
+ WBADRI0: in std_logic; WBDATI7: in std_logic;
+ WBDATI6: in std_logic; WBDATI5: in std_logic;
+ WBDATI4: in std_logic; WBDATI3: in std_logic;
+ WBDATI2: in std_logic; WBDATI1: in std_logic;
+ WBDATI0: in std_logic; PLL0DATI7: in std_logic;
+ PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
+ PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
+ PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
+ PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
+ PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
+ PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
+ PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
+ PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
+ PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
+ I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
+ I2C2SDAI: in std_logic; SPISCKI: in std_logic;
+ SPIMISOI: in std_logic; SPIMOSII: in std_logic;
+ SPISCSN: in std_logic; TCCLKI: in std_logic;
+ TCRSTN: in std_logic; TCIC: in std_logic;
+ UFMSN: in std_logic; WBDATO7: out std_logic;
+ WBDATO6: out std_logic; WBDATO5: out std_logic;
+ WBDATO4: out std_logic; WBDATO3: out std_logic;
+ WBDATO2: out std_logic; WBDATO1: out std_logic;
+ WBDATO0: out std_logic; WBACKO: out std_logic;
+ PLLCLKO: out std_logic; PLLRSTO: out std_logic;
+ PLL0STBO: out std_logic; PLL1STBO: out std_logic;
+ PLLWEO: out std_logic; PLLADRO4: out std_logic;
+ PLLADRO3: out std_logic; PLLADRO2: out std_logic;
+ PLLADRO1: out std_logic; PLLADRO0: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic;
+ I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
+ I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
+ I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
+ I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
+ I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
+ SPISCKO: out std_logic; SPISCKEN: out std_logic;
+ SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
+ SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
+ SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
+ SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
+ SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
+ SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
+ SPICSNEN: out std_logic; SPIIRQO: out std_logic;
+ TCINT: out std_logic; TCOC: out std_logic;
+ WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
+ CFGSTDBY: out std_logic);
+ end component;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ BB1_sda: BB
+ port map (I=>i2c1_sdao, T=>i2c1_sdaoen, O=>i2c1_sdai,
+ B=>i2c1_sda);
+
+ BB1_scl: BB
+ port map (I=>i2c1_sclo, T=>i2c1_scloen, O=>i2c1_scli,
+ B=>i2c1_scl);
+
+ EFBInst_0: EFB
+ generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 757,
+ UFM_INIT_PAGES=> 10, DEV_DENSITY=> "4300L", EFB_UFM=> "ENABLED",
+ TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
+ TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
+ TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
+ TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
+ TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
+ SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
+ SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED",
+ SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
+ SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
+ SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
+ EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
+ I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000001",
+ I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
+ I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 84,
+ I2C1_BUS_PERF=> "100kHz", I2C1_SLAVE_ADDR=> "0b1000001",
+ I2C1_ADDRESSING=> "7BIT", EFB_I2C1=> "ENABLED", EFB_WB_CLK_FREQ=> "33.3")
+ port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
+ WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
+ WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
+ WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
+ WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
+ WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
+ WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
+ WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
+ WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
+ WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
+ PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
+ PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
+ PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
+ PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
+ PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
+ PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
+ PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
+ PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
+ PLL1ACKI=>scuba_vlo, I2C1SCLI=>i2c1_scli,
+ I2C1SDAI=>i2c1_sdai, I2C2SCLI=>scuba_vlo,
+ I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo,
+ SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo,
+ TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi,
+ WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6),
+ WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4),
+ WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2),
+ WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o,
+ PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open,
+ PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
+ PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
+ PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
+ PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
+ PLLDATO0=>open, I2C1SCLO=>i2c1_sclo, I2C1SCLOEN=>i2c1_scloen,
+ I2C1SDAO=>i2c1_sdao, I2C1SDAOEN=>i2c1_sdaoen, I2C2SCLO=>open,
+ I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
+ I2C1IRQO=>i2c1_irqo, I2C2IRQO=>open, SPISCKO=>open,
+ SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open,
+ SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open,
+ SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open,
+ SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open,
+ SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open,
+ TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open,
+ CFGSTDBY=>open);
+
+end Structure;
generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00";
USE_OLD_13BIT_MODE : integer := c_NO;
DATA_BUS_WIDTH : integer := 16;
- CFG_FLASH_DISABLE_COUNTER_WIDTH : integer := 32 --42sec@100MHz
+ CFG_FLASH_DISABLE_COUNTER_WIDTH : integer := 32; --42sec@100MHz
+ USE_I2C_PROG : integer := c_YES
);
port(
CLK_l : in std_logic; --local clock
LOC_WRITE_OUT : out std_logic;
LOC_READ_OUT : out std_logic;
LOC_READY_IN : in std_logic;
- LOC_BUSY_OUT : out std_logic
+ LOC_BUSY_OUT : out std_logic;
+
+ SCL : inout std_logic;
+ SDA : inout std_logic
);
end entity;
mem_rd_data : in std_logic_vector(7 downto 0)
);
end component;
+
+ component UFM_WB_I2C_Prog
+ port(
+ clk_i : in std_logic;
+ rst_n : in std_logic;
+ cmd : in std_logic_vector(2 downto 0);
+ ufm_page : in std_logic_vector(15 downto 0);
+ select_cfg : in std_logic;
+ GO : in std_logic;
+ BUSY : out std_logic;
+ ERR : out std_logic;
+ mem_clk : out std_logic;
+ mem_we : out std_logic;
+ mem_ce : out std_logic;
+ mem_addr : out std_logic_vector(3 downto 0);
+ mem_wr_data : out std_logic_vector(7 downto 0);
+ mem_rd_data : in std_logic_vector(7 downto 0);
+ i2c_scl : inout std_logic;
+ i2c_sda : inout std_logic
+ );
+ end component;
signal reg_SPI_DATA_OUT : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
signal reg_SPI_READY_OUT : std_logic;
QB => flashram_data_o
);
- THE_FLASH : UFM_WB
- port map(
- clk_i => CLK_f,
- rst_n => not RESET,
- cmd => flash_command,
- ufm_page => flash_page,
- select_cfg => select_cfg,
- GO => flash_go,
- BUSY => flash_busy,
- ERR => flash_err,
- mem_clk => open,
- mem_we => flashram_write_i,
- mem_ce => flashram_cen_i,
- mem_addr => flashram_addr_i,
- mem_wr_data => flashram_data_i,
- mem_rd_data => flashram_data_o
+ GEN_UFM_WB : if USE_I2C_PROG = 0 generate
+ THE_FLASH : UFM_WB
+ port map(
+ clk_i => CLK_f,
+ rst_n => not RESET,
+ cmd => flash_command,
+ ufm_page => flash_page,
+ select_cfg => select_cfg,
+ GO => flash_go,
+ BUSY => flash_busy,
+ ERR => flash_err,
+ mem_clk => open,
+ mem_we => flashram_write_i,
+ mem_ce => flashram_cen_i,
+ mem_addr => flashram_addr_i,
+ mem_wr_data => flashram_data_i,
+ mem_rd_data => flashram_data_o
);
-
+
+ SCL <= 'Z';
+ SDA <= 'Z';
+ end generate GEN_UFM_WB;
+
+ GEN_UFM_WB_I2C : if USE_I2C_PROG = 1 generate
+ THE_FLASH : UFM_WB_I2C_Prog
+ port map(
+ clk_i => CLK_f,
+ rst_n => not RESET,
+ cmd => flash_command,
+ ufm_page => flash_page,
+ select_cfg => select_cfg,
+ GO => flash_go,
+ BUSY => flash_busy,
+ ERR => flash_err,
+ mem_clk => open,
+ mem_we => flashram_write_i,
+ mem_ce => flashram_cen_i,
+ mem_addr => flashram_addr_i,
+ mem_wr_data => flashram_data_i,
+ mem_rd_data => flashram_data_o,
+ i2c_scl => SCL,
+ i2c_sda => SDA
+ );
+ end generate GEN_UFM_WB_I2C;
+
LOC_DATA_OUT <= reg_LOC_DATA_OUT;
LOC_ADDR_OUT <= reg_LOC_ADDR_OUT;
LOC_WRITE_OUT <= reg_LOC_WRITE_OUT;
jspc29 / vhdlbasics.git / commitdiff