new

diff --git a/etrax_interfacev2.vhd b/etrax_interfacev2.vhd
index bee1ac377481030d8487bc9d38f84e582b34240d..8351c20f4633090eff1053c43c695236174daa19 100644 (file)
--- a/etrax_interfacev2.vhd
+++ b/etrax_interfacev2.vhd
@@ -111,6 +111,8 @@ architecture etrax_interfacev2 of etrax_interfacev2 is
   signal reg_address : integer range 0 to 256 :=1;
   signal data_valid_synch : std_logic;
   signal how_many_data_was_sent : std_logic_vector(4 downto 0);
+  signal time_out_cntr : std_logic_vector(31 downto 0);
+  signal time_out_pulse : std_logic;
 begin
 
   
@@ -186,12 +188,18 @@ begin
           ETRAX_DATA_BUS_E(8)                <= 'Z';
           enable_transmition                  <= '0';
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
-        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
+        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) = x"00" then
           data_from_etrax                     <= data_from_etrax;
-          ETRAX_DATA_BUS_E(8)                <= data_to_etrax(0);
-          etrax_data_counter                := etrax_data_counter + 1;
+          ETRAX_DATA_BUS_E(8)                 <= data_to_etrax(0);
+          etrax_data_counter                  := etrax_data_counter + 1;
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
           enable_transmition                  <= '0';
+        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) /= x"00" and (rw_operation_finished_pulse = '1' or time_out_pulse = '1') then
+          data_from_etrax                     <= data_from_etrax;
+          ETRAX_DATA_BUS_E(8)                 <= data_to_etrax(0);
+          etrax_data_counter                  := etrax_data_counter + 1;
+          etrax_std_data_counter              <= etrax_std_data_counter + 1;
+          enable_transmition                  <= '0';  
         elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
           data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_E(8)                <= data_to_etrax((etrax_data_counter-81) mod 32);--+reg_address*32
@@ -217,6 +225,26 @@ begin
     end if;
   end process SYNC_DATA_TO_ETRAX;
 
+  TIME_OUT : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        time_out_cntr <= x"00000000";
+      elsif etrax_std_data_counter = 81 then
+        time_out_cntr <= time_out_cntr + 1;
+      else
+        time_out_cntr <= x"00000000";
+      end if;
+    end if;
+  end process TIME_OUT;
+
+  TIME_OUT_PULSER       : edge_to_pulse
+    port map (
+      clock     => CLK,
+      en_clk    => '1',
+      signal_in => time_out_cntr(26),
+      pulse     => time_out_pulse);
+  
   RW_FINISHED_PULSER       : edge_to_pulse
     port map (
       clock     => CLK,
@@ -416,8 +444,7 @@ begin
       etrax_is_ready_to_read_i <= IPU_READY_IN;
       ETRAX_DATA_BUS_B(16)          <= '0';
     end generate WITH_TRBNET;
-    IPU_DATAREADY_OUT <= DATA_VALID and (not LVL2_VALID);
-    IPU_DATA_OUT <= data_bus_reg;
+    
     
     WITHOUT_TRBNET: if TRBNET_ENABLE /= 1 generate
       ETRAX_READY_PULSE      : edge_to_pulse
@@ -467,8 +494,12 @@ begin
       if rising_edge(CLK) then
         if RESET = '1' then       
           data_bus_reg <= (others => '0');
+          IPU_DATAREADY_OUT <= '0';
+          IPU_DATA_OUT <= (others => '0');
         else
           data_bus_reg <= DATA_BUS;
+          IPU_DATAREADY_OUT <= DATA_VALID and (not LVL2_VALID);
+          IPU_DATA_OUT <= DATA_BUS;
         end if;
       end if;
     end process REG_DATA_TO_ETRAXb;

diff --git a/tdc_interfacev2.vhd b/tdc_interfacev2.vhd
index bf55eb15531f8dfcf37ea781c3b096c01ba78972..d91f6ed16748dabd796b1a5819d574cb38f4218c 100644 (file)
--- a/tdc_interfacev2.vhd
+++ b/tdc_interfacev2.vhd
@@ -148,7 +148,7 @@ architecture tdc_interfacev2 of tdc_interfacev2 is
 
   --lvl1
   type LVL1_START_FSM is
-      (IDLE, WAIT_BEFORE_TRIGG, SEND_TRIGGER, WAIT_BEFORE_TOKEN, WAIT_FOR_TOKEN,SEND_AND_WAIT_FOR_TOKEN,SAVE_DATA_MARKER,SAVE_EB_HEADER_1,SAVE_EB_HEADER_2,SAVE_EB_HEADER_3,SAVE_EB_HEADER_4,SAVE_HEADER_1,SAVE_HEADER_2,SAVE_TRBNET_HEADER_1,SAVE_TRBNET_HEADER_2,SAVE_ADD_DATA,SAVE_HEADER_MARKER);
+      (IDLE, WAIT_BEFORE_TRIGG, SEND_TRIGGER, WAIT_BEFORE_TOKEN, WAIT_FOR_TOKEN,SEND_AND_WAIT_FOR_TOKEN,SAVE_DATA_MARKER,SAVE_EB_HEADER_1,SAVE_EB_HEADER_2,SAVE_EB_HEADER_3,SAVE_EB_HEADER_4,SAVE_HEADER_1,SAVE_HEADER_2,SAVE_TRBNET_HEADER_1,SAVE_TRBNET_HEADER_2,SAVE_ADD_DATA,SAVE_HEADER_MARKER,WAIT_FOR_EMPTYING_BUFFERS);
   signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
   signal lvl1_busy_i : std_logic;
   signal lvl1_busy_i_not : std_logic;  
@@ -259,13 +259,13 @@ begin
       TDC_REGISTER_00(13 downto 4)  <= (others => '0');
       TDC_REGISTER_00(14)           <= lvl1_busy_i;
       TDC_REGISTER_00(15)           <= lvl1_memory_busy_i;    
-      TDC_REGISTER_00(30)           <= hd_wr_en_i & hd_dout_i(32) & hd_rd_data_count_i & hd_full_i & hd_empty_i & data_wr_en_i  & data_dout_i(32) & data_rd_data_count_i & data_full_i & data_empty_i;
+      TDC_REGISTER_00(30)           <= '0';
       TDC_REGISTER_00(31)           <= lvl2_busy_i;
       TDC_REGISTER_00(29 downto 16) <= (others => '0');
       TDC_REGISTER_01(27 downto 0)  <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& words_in_event(15 downto 0);
       TDC_REGISTER_01(30 downto 28) <= (others => '0');
       TDC_REGISTER_01(31)           <= ETRAX_IS_BUSY;
-      TDC_REGISTER_02(31 downto 0)  <= (others => '0');  
+      TDC_REGISTER_02(31 downto 0)  <=  hd_full_i & hd_empty_i & hd_wr_en_i & hd_dout_i(32) & hd_rd_data_count_i & data_full_i & data_empty_i & data_wr_en_i  & data_dout_i(32) & data_rd_data_count_i(11 downto 0);
       TDC_REGISTER_03(31 downto 0)  <= x"0"& LVL1_CODE & LVL1_TAG(7 downto 0) & x"0" & lvl1_code_i & lvl1_tag_minus1;
       TDC_REGISTER_04(31 downto 0)  <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
     end if;
@@ -562,7 +562,19 @@ begin
         hd_wr_en_i_fsm           <= '1';
         hd_din_i_fsm             <= (others => '0');
         --here add memory busy
-        LVL1_START_fsm_nextstate   <= IDLE;
+        if lvl1_memory_busy_i = '0'  then
+          LVL1_START_fsm_nextstate   <= IDLE;
+        else
+          LVL1_START_fsm_nextstate   <= WAIT_FOR_EMPTYING_BUFFERS;
+        end if;
+
+      when WAIT_FOR_EMPTYING_BUFFERS => 
+        trigger_register_00_i(5 downto 2) <= x"d";
+        if lvl1_memory_busy_i = '0'  then
+          LVL1_START_fsm_nextstate   <= IDLE;
+        else
+          LVL1_START_fsm_nextstate   <= WAIT_FOR_EMPTYING_BUFFERS;
+        end if;
 
       when others =>
         trigger_register_00_i(5 downto 2) <= x"0";  
@@ -658,7 +670,7 @@ begin
         lvl1_tag_minus1 <= trigger_counter;
         lvl1_code_i <= x"1";
       else
-        lvl1_tag_minus1 <= LVL1_TAG(7 downto 0) - 1;
+        lvl1_tag_minus1 <= LVL1_TAG(7 downto 0);
         lvl1_code_i <= LVL1_CODE;
       end if;
     end if;
@@ -863,7 +875,7 @@ begin
     if rising_edge(CLK) then  
       if RESET = '1' then
         lvl1_memory_busy_i <= '0';     
-      elsif (data_wr_data_count_i(14 downto 13)= "11") or (hd_wr_data_count_i(11 downto 1) = "11111111111") then
+      elsif (data_wr_data_count_i(14 downto 13)= "11") or (hd_wr_data_count_i(11 downto 2) = "1111111111") then
         lvl1_memory_busy_i <= '1';           
       else
         lvl1_memory_busy_i <= '0';     

diff --git a/trb_v2b_fpga.stapl b/trb_v2b_fpga.stapl
index a41f3ecfe40cbf8fa89173f53c9114c6131cefac..0e5c19e11c10864fd9ae0be776e1a3023e9f5ef7 100644 (file)
--- a/trb_v2b_fpga.stapl
+++ b/trb_v2b_fpga.stapl
@@ -1,5 +1,5 @@
 NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2009/08/06";
+NOTE "DATE" "2009/08/14";
 NOTE "STAPL_VERSION" "JESD71";
 NOTE "ALG_VERSION" "1";
 NOTE "DEVICE" "UNSPECIFIED";
@@ -1258,6912 +1258,5959 @@ IF (!X) THEN GOTO F;
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 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -8212,9 +7973,16 @@ Nvp@J6zVaJ@@Or@DUz@YP@dus@7szVXV@FOu@1E_@Vb@ttv@xb_VUh@VNx@rz_@Sn@7ty@lL
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@FC00W1000WUmelPD3080010000520000m002
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-060O0020000060G106zW100GvLLdm7zW100M2oTu70
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@r200m0000GePMG0c1040W0000W210000O00108
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+0C0010000030e00ZUm000eyggJuZUm000B1vEy3
  ;
 ' // Loading device with a `jstart` instruction. 
 IRSCAN 10, $03cc
@@ -8291,4 +8059,4 @@ IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
 IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
 ENDPROC;
 
-CRC EA35;
+CRC 1C6B;

diff --git a/trb_v2b_fpga.ucf b/trb_v2b_fpga.ucf
index 43fb62b2b3104a93285b65184509a552546467fb..625d27e4a196a073124cf9d275da867389244058 100644 (file)
--- a/trb_v2b_fpga.ucf
+++ b/trb_v2b_fpga.ucf
@@ -483,9 +483,12 @@
  # NET  SFP_MOD<0>       LOC ="R23"| IOSTANDARD = "LVTTL";
 #  NET  SFP_MOD<1>       LOC ="K32"| IOSTANDARD = "LVTTL";
 #  NET  SFP_MOD<2>       LOC ="K33"| IOSTANDARD = "LVTTL";
+  NET  SFP_MOD_LOW       LOC ="R23"| IOSTANDARD = "LVTTL";
 #names not like in the schematics !
-  NET  SCL       LOC ="K32"| IOSTANDARD = "LVTTL";
-  NET  SDA       LOC ="K33"| IOSTANDARD = "LVTTL";
+#  NET  SCL      LOC ="K32"| IOSTANDARD = "LVTTL"; wrong !!!!!
+#  NET  SDA      LOC ="K33"| IOSTANDARD = "LVTTL"; wrong !!!!!
+ NET  SCL        LOC ="K33"| IOSTANDARD = "LVTTL"; 
+ NET  SDA        LOC ="K32"| IOSTANDARD = "LVTTL"; 
  # NET  SFP_RATE_SEL     LOC ="P27"| IOSTANDARD = "LVTTL";
    NET  SFP_TX_DIS       LOC ="N27"| IOSTANDARD = "LVTTL";
    NET  SFP_TX_FAULT     LOC ="J32"| IOSTANDARD = "LVTTL";
@@ -524,7 +527,7 @@
    NET  TDC_RESET        LOC ="C5"| IOSTANDARD = "LVTTL";
     NET  TLK_CLK         LOC ="AG16"| IOSTANDARD = "LVTTL";
     NET "TLK_CLK" TNM_NET =TLK_CLK;
-   TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 8 ns;
+   TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9.5 ns;
     NET  TLK_ENABLE      LOC ="R24"| IOSTANDARD = "LVTTL";
     NET  TLK_LCKREFN     LOC ="L28"| IOSTANDARD = "LVTTL";
     NET  TLK_LOOPEN      LOC ="R19"| IOSTANDARD = "LVTTL";
@@ -547,7 +550,7 @@
     NET  TLK_RXD<15>     LOC ="G33"| IOSTANDARD = "LVTTL";
     NET  TLK_RX_CLK      LOC ="AF18"| IOSTANDARD = "LVTTL";
     NET "TLK_RX_CLK" TNM_NET =TLK_RX_CLK;
-   TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 8 ns;
+   TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9.5 ns;
     NET  TLK_RX_DV       LOC ="M30"| IOSTANDARD = "LVTTL";
     NET  TLK_RX_ER       LOC ="P20"| IOSTANDARD = "LVTTL";
     NET  TLK_TXD<0>      LOC ="H27"| IOSTANDARD = "LVTTL";
@@ -644,12 +647,12 @@
 # OFFSET=OUT 2 ns BEFORE "REF_TDC_CLK" HIGH;
 
  NET "VIRT_CLK" TNM_NET =VIRT_CLK;
- TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
+ TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9.5 ns;
  NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
  TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 22 ns;
 
  NET "CLK" TNM_NET=CLK;
- TIMESPEC TS_CLK =PERIOD "CLK" 9 ns;
+ TIMESPEC TS_CLK =PERIOD "CLK" 9.5 ns;
 
  NET "A_DATA_READY" TNM = TDC_NET_GROUP ;
  NET "B_DATA_READY" TNM = TDC_NET_GROUP ;

diff --git a/trb_v2b_fpga.vhd b/trb_v2b_fpga.vhd
index dce33d7d45e9f6d280b082ee204a2b6d6d2ef8fb..6ec9dcc88c826ea965a70c07e3e374cedc932084 100644 (file)
--- a/trb_v2b_fpga.vhd
+++ b/trb_v2b_fpga.vhd
@@ -1,7 +1,7 @@
 library IEEE;
 use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
 use ieee.numeric_std.all;
 library UNISIM;
 use UNISIM.VCOMPONENTS.all;
@@ -14,35 +14,39 @@ entity trb_v2b_fpga is
   generic (
     RW_SYSTEM            : integer range 1 to 2   := 1;  --1 -trb, 2 -addon with portE 10 9 as rw
     TRBV2_TYPE           : integer range 0 to 5   := 5;
-                                        -- 0 - trbv2 + RPC or TOF or FWALL or Start or Veto,
-                                        -- 1 - MDC,
-                                        -- 2 - SHOWER,
-                                        -- 3 - RICH
-                                        -- 4 - CTS+VULOM
-                                        -- 5 - CTS only, lvl2 is automatic
+                                   -- 0 - trbv2 + RPC or TOF or FWALL or Start or Veto,
+                                   -- 1 - MDC,
+                                   -- 2 - SHOWER,
+                                   -- 3 - RICH
+                                   -- 4 - CTS+VULOM
+                                   -- 5 - CTS only, lvl2 is automatic
     TRBNET_ENABLE        : integer range 0 to 3   := 2;  -- 0 - disable,
-                                        -- 1 - end point
-                                        -- 2 - cts
-                                        -- 3 - slow ctrl
+                                                         -- 1 - end point
+                                                         -- 2 - cts
+                                                         -- 3 - slow ctrl
     DTU_ENABLE           : integer range 0 to 2   := 0;  -- 0 - disable, 1 - old
-                                        -- HADES bus, 2 - opt
-                                        -- without trbnet
+                                                         -- HADES bus, 2 - opt
+                                                         -- without trbnet
     CTU_ENABLE           : integer range 0 to 1   := 0;
     HADES_OLD_BUS_ENABLE : integer range 0 to 1   := 0;
     DSP_INT_ENABLE       : integer range 0 to 1   := 0;  -- dsp interface enable
     SDRAM_INT_ENABLE     : integer range 0 to 1   := 0;  -- sdram interface enable
     SCALERS_ENABLE       : integer range 0 to 1   := 0;
     RW_REGISTERS_NUMBER  : integer range 0 to 40  := 8;  --32 bit registers
-                                        --accesed by trbnet or
-                                        --etrax (read/write) -
-                                        --control
-    R_REGISTERS_NUMBER   : integer range 0 to 40  := 22; --only read  - status
+                                                         --accesed by trbnet or
+                                                         --etrax (read/write) -
+                                                         --control
+    R_REGISTERS_NUMBER   : integer range 0 to 40  := 22;  --only read  - status
     ENABLE_DMA           : integer range 1 to 2   := 1;  --1- DMA , 2 - no DMA
                                                          --2- also for trbnet
                                                          --end point !
     NUMBER_OFF_ADD_DATA  : integer range 0 to 255 := 8;
     REGIO_NUM_STAT_REGS  : integer range 0 to 255 := 2;
-    REGIO_NUM_CTRL_REGS : integer range  0 to 255 := 3
+    REGIO_NUM_CTRL_REGS  : integer range 0 to 255 := 3;
+    DEBUG_OPTION         : integer range 0 to 8   := 2   --0 no debug
+                                                         --1 trbnet enpoit
+                                                         --2 trbent cts
+                                                         --3 sfp
     );
   port (
     -------------------------------------------------------------------------
@@ -56,147 +60,147 @@ entity trb_v2b_fpga is
     DINT       : out   std_logic;       --diode
     DWAIT      : out   std_logic;       --diode
     A_RESERVED : in    std_logic;       --TDC connector 75,76(line 3 from end)
-    TEMP_SENS  : inout std_logic_vector(3 downto 0);  -- on the schematics
-                                        -- A_TEMP,B_TEMP ...
-
-    B_RESERVED : in std_logic;
-    C_RESERVED : in std_logic;
-    D_RESERVED : in std_logic;
-    VIR_TRIG   : in std_logic;          --fast trigger 
-    VIR_TRIGB  : in std_logic;
+    TEMP_SENS  : inout std_logic_vector(3 downto 0);     -- on the schematics
+                                                         -- A_TEMP,B_TEMP ...
+
+    B_RESERVED      : in  std_logic;
+    C_RESERVED      : in  std_logic;
+    D_RESERVED      : in  std_logic;
+    VIR_TRIG        : in  std_logic;    --fast trigger 
+    VIR_TRIGB       : in  std_logic;
     -------------------------------------------------------------------------
     -- TDC connections
     -------------------------------------------------------------------------
-     A_TDC_ERROR     : in  std_logic;
-     B_TDC_ERROR     : in  std_logic;
-     C_TDC_ERROR     : in  std_logic;
-     D_TDC_ERROR     : in  std_logic;
-     A_TDC_POWERUP   : out std_logic;    --turn on TDC -should be one ?
-     B_TDC_POWERUP   : out std_logic;
-     C_TDC_POWERUP   : out std_logic;
-     D_TDC_POWERUP   : out std_logic;
-     TOKEN_IN        : in  std_logic;
-     TOKEN_OUT       : out std_logic;
-     C_TOKEN_OUT_TTL : in  std_logic;
-     GET_DATA        : out std_logic;
-     A_DATA_READY    : in  std_logic;
-     B_DATA_READY    : in  std_logic;
-     C_DATA_READY    : in  std_logic;
-     D_DATA_READY    : in  std_logic;
-     REF_TDC_CLK     : in  std_logic;
-     REF_TDC_CLKB    : in  std_logic;
-  --   TDC_BU_RESET    : out std_logic;
-  --   TDC_BU_RESETB   : out std_logic;
-  --   TDC_EV_RESET    : out std_logic;
-  --   TDC_EV_RESETB   : out std_logic;
-     A_TDC_BU_RESET  : out std_logic;
-     A_TDC_BU_RESETB : out std_logic;
-     A_TDC_EV_RESET  : out std_logic;
-     A_TDC_EV_RESETB : out std_logic;
-     B_TDC_BU_RESET  : out std_logic;
-     B_TDC_BU_RESETB : out std_logic;
-     B_TDC_EV_RESET  : out std_logic;
-     B_TDC_EV_RESETB : out std_logic;
-     C_TDC_BU_RESET  : out std_logic;
-     C_TDC_BU_RESETB : out std_logic;
-     C_TDC_EV_RESET  : out std_logic;
-     C_TDC_EV_RESETB : out std_logic;
-     D_TDC_BU_RESET  : out std_logic;
-     D_TDC_BU_RESETB : out std_logic;
-     D_TDC_EV_RESET  : out std_logic;
-     D_TDC_EV_RESETB : out std_logic;
-     TDC_OUT         : in  std_logic_vector (31 downto 0);
-     TDC_RESET       : out std_logic;
-     A_TRIGGER       : out std_logic;
-     A_TRIGGERB      : out std_logic; 
-     B_TRIGGER       : out std_logic;
-     B_TRIGGERB      : out std_logic;
-     C_TRIGGER       : out std_logic;
-     C_TRIGGERB      : out std_logic; 
-     D_TRIGGER       : out std_logic;
-     D_TRIGGERB      : out std_logic;
-     
+    A_TDC_ERROR     : in  std_logic;
+    B_TDC_ERROR     : in  std_logic;
+    C_TDC_ERROR     : in  std_logic;
+    D_TDC_ERROR     : in  std_logic;
+    A_TDC_POWERUP   : out std_logic;    --turn on TDC -should be one ?
+    B_TDC_POWERUP   : out std_logic;
+    C_TDC_POWERUP   : out std_logic;
+    D_TDC_POWERUP   : out std_logic;
+    TOKEN_IN        : in  std_logic;
+    TOKEN_OUT       : out std_logic;
+    C_TOKEN_OUT_TTL : in  std_logic;
+    GET_DATA        : out std_logic;
+    A_DATA_READY    : in  std_logic;
+    B_DATA_READY    : in  std_logic;
+    C_DATA_READY    : in  std_logic;
+    D_DATA_READY    : in  std_logic;
+    REF_TDC_CLK     : in  std_logic;
+    REF_TDC_CLKB    : in  std_logic;
+    --   TDC_BU_RESET    : out std_logic;
+    --   TDC_BU_RESETB   : out std_logic;
+    --   TDC_EV_RESET    : out std_logic;
+    --   TDC_EV_RESETB   : out std_logic;
+    A_TDC_BU_RESET  : out std_logic;
+    A_TDC_BU_RESETB : out std_logic;
+    A_TDC_EV_RESET  : out std_logic;
+    A_TDC_EV_RESETB : out std_logic;
+    B_TDC_BU_RESET  : out std_logic;
+    B_TDC_BU_RESETB : out std_logic;
+    B_TDC_EV_RESET  : out std_logic;
+    B_TDC_EV_RESETB : out std_logic;
+    C_TDC_BU_RESET  : out std_logic;
+    C_TDC_BU_RESETB : out std_logic;
+    C_TDC_EV_RESET  : out std_logic;
+    C_TDC_EV_RESETB : out std_logic;
+    D_TDC_BU_RESET  : out std_logic;
+    D_TDC_BU_RESETB : out std_logic;
+    D_TDC_EV_RESET  : out std_logic;
+    D_TDC_EV_RESETB : out std_logic;
+    TDC_OUT         : in  std_logic_vector (31 downto 0);
+    TDC_RESET       : out std_logic;
+    A_TRIGGER       : out std_logic;
+    A_TRIGGERB      : out std_logic;
+    B_TRIGGER       : out std_logic;
+    B_TRIGGERB      : out std_logic;
+    C_TRIGGER       : out std_logic;
+    C_TRIGGERB      : out std_logic;
+    D_TRIGGER       : out std_logic;
+    D_TRIGGERB      : out std_logic;
+
     -------------------------------------------------------------------------
     -- ETRAX connections
     -------------------------------------------------------------------------
-    FS_PB      : inout std_logic_vector (16 downto 0);
-    FS_PB_17   : in std_logic;--_vector (16 downto 0);
-    FS_PC      : inout std_logic_vector (17 downto 0);
-    ETRAX_IRQ  : out   std_logic;
-    
+    FS_PB     : inout std_logic_vector (16 downto 0);
+    FS_PB_17  : in    std_logic;        --_vector (16 downto 0);
+    FS_PC     : inout std_logic_vector (17 downto 0);
+    ETRAX_IRQ : out   std_logic;
+
     -------------------------------------------------------------------------
     -- SPI 
     -------------------------------------------------------------------------
-      A_SCK  : out std_logic;
-      A_SCKB : out std_logic;
-      A_SDI  : in  std_logic;
-      A_SDIB : in  std_logic;
-      A_SDO  : out std_logic;
-      A_SDOB : out std_logic;
-      A_CSB  : out std_logic;
-      A_CS   : out std_logic;
-
-      B_SCK  : out std_logic; 
-      B_SCKB : out std_logic; 
-      B_SDI  : in  std_logic; 
-      B_SDIB : in  std_logic; 
-      B_SDO  : out std_logic; 
-      B_SDOB : out std_logic; 
-      B_CSB  : out std_logic; 
-      B_CS   : out std_logic; 
-
-      C_SCK  : out std_logic; 
-      C_SCKB : out std_logic; 
-      C_SDI  : in  std_logic; 
-      C_SDIB : in  std_logic; 
-      C_SDO  : out std_logic; 
-      C_SDOB : out std_logic; 
-      C_CSB  : out std_logic; 
-      C_CS   : out std_logic; 
-
-      D_SCK  : out std_logic; 
-      D_SCKB : out std_logic; 
-      D_SDI  : in  std_logic; 
-      D_SDIB : in  std_logic; 
-      D_SDO  : out std_logic; 
-      D_SDOB : out std_logic; 
-      D_CSB  : out std_logic; 
-      D_CS   : out std_logic;
-      
+    A_SCK  : out std_logic;
+    A_SCKB : out std_logic;
+    A_SDI  : in  std_logic;
+    A_SDIB : in  std_logic;
+    A_SDO  : out std_logic;
+    A_SDOB : out std_logic;
+    A_CSB  : out std_logic;
+    A_CS   : out std_logic;
+
+    B_SCK  : out std_logic;
+    B_SCKB : out std_logic;
+    B_SDI  : in  std_logic;
+    B_SDIB : in  std_logic;
+    B_SDO  : out std_logic;
+    B_SDOB : out std_logic;
+    B_CSB  : out std_logic;
+    B_CS   : out std_logic;
+
+    C_SCK  : out std_logic;
+    C_SCKB : out std_logic;
+    C_SDI  : in  std_logic;
+    C_SDIB : in  std_logic;
+    C_SDO  : out std_logic;
+    C_SDOB : out std_logic;
+    C_CSB  : out std_logic;
+    C_CS   : out std_logic;
+
+    D_SCK  : out std_logic;
+    D_SCKB : out std_logic;
+    D_SDI  : in  std_logic;
+    D_SDIB : in  std_logic;
+    D_SDO  : out std_logic;
+    D_SDOB : out std_logic;
+    D_CSB  : out std_logic;
+    D_CS   : out std_logic;
+
     -------------------------------------------------------------------------
     -- RPC TEST SIGNALS - for RPC
     -------------------------------------------------------------------------
-      A_TEST1  : out std_logic;
-      A_TEST1B : out std_logic;
-      A_TEST2  : out std_logic;
-      A_TEST2B : out std_logic;
-      B_TEST1  : out std_logic;
-      B_TEST1B : out std_logic;
-      B_TEST2  : out std_logic;
-      B_TEST2B : out std_logic;
-      C_TEST1  : out std_logic;
-      C_TEST1B : out std_logic;
-      C_TEST2  : out std_logic;
-      C_TEST2B : out std_logic;
-      D_TEST1  : out std_logic;
-      D_TEST1B : out std_logic;
-      D_TEST2  : out std_logic;
-      D_TEST2B : out std_logic;
-      
+    A_TEST1  : out std_logic;
+    A_TEST1B : out std_logic;
+    A_TEST2  : out std_logic;
+    A_TEST2B : out std_logic;
+    B_TEST1  : out std_logic;
+    B_TEST1B : out std_logic;
+    B_TEST2  : out std_logic;
+    B_TEST2B : out std_logic;
+    C_TEST1  : out std_logic;
+    C_TEST1B : out std_logic;
+    C_TEST2  : out std_logic;
+    C_TEST2B : out std_logic;
+    D_TEST1  : out std_logic;
+    D_TEST1B : out std_logic;
+    D_TEST2  : out std_logic;
+    D_TEST2B : out std_logic;
+
     -------------------------------------------------------------------------
     -- TIGER SHARC
     -------------------------------------------------------------------------
-      DSPADDR  : out   std_logic_vector (31 downto 0);
-      DSPDAT   : inout std_logic_vector (31 downto 0);
-      DSP_ACK  : in    std_logic;
-      DSP_BM   : inout std_logic;
-      DSP_BMS  : out   std_logic;        --LOC = AF15;
-      DSP_BOFF : out   std_logic;        --       LOC = AK14;
-      DSP_BRST : inout std_logic;
-      DSP_HBG  : in    std_logic;
-      DSP_HBR  : out   std_logic;
-      DSP_IRQ  : out   std_logic_vector (3 downto 0);
-      --link0
+    DSPADDR       : out   std_logic_vector (31 downto 0);
+    DSPDAT        : inout std_logic_vector (31 downto 0);
+    DSP_ACK       : in    std_logic;
+    DSP_BM        : inout std_logic;
+    DSP_BMS       : out   std_logic;    --LOC = AF15;
+    DSP_BOFF      : out   std_logic;    --       LOC = AK14;
+    DSP_BRST      : inout std_logic;
+    DSP_HBG       : in    std_logic;
+    DSP_HBR       : out   std_logic;
+    DSP_IRQ       : out   std_logic_vector (3 downto 0);
+    --link0
 --       DSP_L0DATIP       : out std_logic_vector (3 downto 0);
 --       DSP_L0DATIN      : out std_logic_vector (3 downto 0);
 --       DSP_L0DATOP       : in std_logic_vector (3 downto 0);
@@ -222,107 +226,109 @@ entity trb_v2b_fpga is
 --       DSP_L1BCMPO     : in std_logic; 
 --       DSP_L1BCMPI      : out std_logic;
 --       DSP_L1ACKI       : out std_logic;
-      --DSP_TMROE        : LOC = AP20;   --link data widt now is 4 bit  --pullup    
-      DSP_RD    : out std_logic;
-      DSP_RESET : out std_logic;
-      DSP_RESET_OUT : in std_logic;
-      DSP_WRH   : out std_logic;
-      DSP_WRL   : out std_logic;
-      --  DSP_MSH   LOC = AL14;
-      --  DSP_IOEN          LOC = AL18;
-      --  DSP_IORD          LOC = AB16;
-      --  DSP_IOWR          LOC = AB17;
-      --  DSP_BUSLOCK       LOC = AC19;
-      --DSP_DMAR         : std_logic_vector (3 downto 0); 
-      --DSP_FLAG         : std_logic_vector (3 downto 0); 
-   
+    --DSP_TMROE        : LOC = AP20;   --link data widt now is 4 bit  --pullup    
+    DSP_RD        : out   std_logic;
+    DSP_RESET     : out   std_logic;
+    DSP_RESET_OUT : in    std_logic;
+    DSP_WRH       : out   std_logic;
+    DSP_WRL       : out   std_logic;
+    --  DSP_MSH   LOC = AL14;
+    --  DSP_IOEN          LOC = AL18;
+    --  DSP_IORD          LOC = AB16;
+    --  DSP_IOWR          LOC = AB17;
+    --  DSP_BUSLOCK       LOC = AC19;
+    --DSP_DMAR         : std_logic_vector (3 downto 0); 
+    --DSP_FLAG         : std_logic_vector (3 downto 0); 
+
     -------------------------------------------------------------------------
     -- SDRAM
     -------------------------------------------------------------------------
-      VSD_A     : out std_logic_vector (12 downto 0);
-      VSD_BA    : out   std_logic_vector (1 downto 0);
-      VSD_CAS   : out std_logic;
-      VSD_CKE   : out std_logic;
-      VSD_CLOCK : out std_logic;
-      VSD_CSEH  : out std_logic;
-      VSD_CSEL  : out std_logic;
-      VSD_D     : inout std_logic_vector (31 downto 0);
-      VSD_DQML  : out  std_logic_vector (3 downto 0);
-      VSD_RAS   : out std_logic;
-      VSD_WE    : out std_logic;
-      
+    VSD_A     : out   std_logic_vector (12 downto 0);
+    VSD_BA    : out   std_logic_vector (1 downto 0);
+    VSD_CAS   : out   std_logic;
+    VSD_CKE   : out   std_logic;
+    VSD_CLOCK : out   std_logic;
+    VSD_CSEH  : out   std_logic;
+    VSD_CSEL  : out   std_logic;
+    VSD_D     : inout std_logic_vector (31 downto 0);
+    VSD_DQML  : out   std_logic_vector (3 downto 0);
+    VSD_RAS   : out   std_logic;
+    VSD_WE    : out   std_logic;
+
     -------------------------------------------------------------------------
     -- TLK
     -------------------------------------------------------------------------
-      
-      TLK_CLK           : in std_logic;
-      TLK_ENABLE        : out std_logic;
-      TLK_LCKREFN       : out std_logic;
-      TLK_LOOPEN        : out std_logic;
-      TLK_PRBSEN        : out std_logic;
-      TLK_RXD           : in std_logic_vector (15 downto 0);
-      TLK_RX_CLK        : in  std_logic;
-      TLK_RX_DV         : in  std_logic;
-      TLK_RX_ER         : in  std_logic;
-      TLK_TXD           : out std_logic_vector (15 downto 0);
-      TLK_TX_EN         : out std_logic;
-      TLK_TX_ER         : out std_logic;
-       
+
+    TLK_CLK     : in  std_logic;
+    TLK_ENABLE  : out std_logic;
+    TLK_LCKREFN : out std_logic;
+    TLK_LOOPEN  : out std_logic;
+    TLK_PRBSEN  : out std_logic;
+    TLK_RXD     : in  std_logic_vector (15 downto 0);
+    TLK_RX_CLK  : in  std_logic;
+    TLK_RX_DV   : in  std_logic;
+    TLK_RX_ER   : in  std_logic;
+    TLK_TXD     : out std_logic_vector (15 downto 0);
+    TLK_TX_EN   : out std_logic;
+    TLK_TX_ER   : out std_logic;
+
     -------------------------------------------------------------------------
     -- SFP
     -------------------------------------------------------------------------
-       SFP_LOS           : in std_logic; 
+    SFP_LOS      : in    std_logic;
     --  SFP_MOD<0>        LOC = R23;
     --  SFP_MOD<1>        LOC = K32;
     --  SFP_MOD<2>        LOC = K33;
     --  SFP_RATE_SEL      : out std_logic;
-      SCL               : inout std_logic;
-      SDA               : inout std_logic;
-      SFP_TX_DIS        : out std_logic;
-      SFP_TX_FAULT      : in std_logic;
-      
+    SFP_MOD_LOW  : out   std_logic;
+    SCL          : inout std_logic;
+    SDA          : inout std_logic;
+    SFP_TX_DIS   : out   std_logic;
+    SFP_TX_FAULT : in    std_logic;
+
     -------------------------------------------------------------------------
     -- ADDON board 
     -------------------------------------------------------------------------
-     ADDON_TO_TRB_CLKINN       : in std_logic;
-     ADDON_TO_TRB_CLKINP       : in std_logic;
-     ADO_LVDS_IN                 : in std_logic_vector(51 downto 0);  --lvds signal
-     ADO_LVDS_OUT                : out std_logic_vector(9 downto 0);  --lvds signal
-     ADO_TTL                   : inout std_logic_vector(46 downto 0);
- --     ADO_TTL                   : inout std_logic_vector(15 downto 0);
+    ADDON_TO_TRB_CLKINN : in    std_logic;
+    ADDON_TO_TRB_CLKINP : in    std_logic;
+    ADO_LVDS_IN         : in    std_logic_vector(51 downto 0);  --lvds signal
+    ADO_LVDS_OUT        : out   std_logic_vector(9 downto 0);   --lvds signal
+    ADO_TTL             : inout std_logic_vector(46 downto 0);
+    --     ADO_TTL                   : inout std_logic_vector(15 downto 0);
 --      ADO_TTL                   : in std_logic;
-     
+
     -------------------------------------------------------------------------------
     --TDC JTAG 
     -------------------------------------------------------------------------------
-    VIRT_TCK                    : out std_logic;
-    VIRT_TDI                    : out std_logic;
-    VIRT_TDO                    : in std_logic;
-    VIRT_TMS                    : out std_logic;        
-    VIRT_TRST                   : out std_logic
+    VIRT_TCK  : out std_logic;
+    VIRT_TDI  : out std_logic;
+    VIRT_TDO  : in  std_logic;
+    VIRT_TMS  : out std_logic;
+    VIRT_TRST : out std_logic
     );
-  
-    end trb_v2b_fpga;
-  
+
+end trb_v2b_fpga;
+
 architecture trb_v2b_fpga of trb_v2b_fpga is
   
   component Sfp_Interface
     generic (
-      device_add       : std_logic_vector(6 downto 0);
-      temp_start_add   : std_logic_vector(7 downto 0);
-      opt_pwr_start_add : std_logic_vector(7 downto 0);
-      I2C_SPEED        : std_logic_vector(7 downto 0));
+      I2C_SPEED : std_logic_vector(15 downto 0));
     port (
-      CLK_IN        : in    std_logic;
-      RST_IN        : in    std_logic;
-      START_PULSE   : in    std_logic;
-      TEMP_DATA_OUT : out   std_logic_vector(15 downto 0);
-      OPT_DATA_OUT  : out   std_logic_vector(15 downto 0);
-      SCL           : inout std_logic;
-      SDA           : inout std_logic;
-      DEBUG         : out   std_logic_vector(31 downto 0));
+      CLK_IN         : in    std_logic;
+      RST_IN         : in    std_logic;
+      START_PULSE    : in    std_logic;
+      DEVICE_ADDRESS : in    std_logic_vector(7 downto 0);
+      DATA_OUT       : out   std_logic_vector(15 downto 0);
+      SCL            : inout std_logic;
+      SDA            : inout std_logic;
+      EN_RESET       : in    std_logic;
+      READ_DONE      : out   std_logic;
+      DEBUG          : out   std_logic_vector(31 downto 0);
+      SFP_ADDRESS    : in    std_logic_vector(31 downto 0));
   end component;
-  
+
+
   component cts
     generic (
       TRBNET_ENABLE : natural);
@@ -422,27 +428,27 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       TRBNET_HEADER_BUILD    : in  std_logic
       );
   end component;
-  
 
- component trb_net_onewire is
+
+  component trb_net_onewire is
     generic(
       USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
-      CLK_PERIOD : integer := 10  --clk period in ns
+      CLK_PERIOD              : integer              := 10  --clk period in ns
       );
     port(
-      CLK      : in std_logic;
-      RESET    : in std_logic;
+      CLK       : in    std_logic;
+      RESET     : in    std_logic;
       --connection to 1-wire interface
-      ONEWIRE  : inout std_logic;
+      ONEWIRE   : inout std_logic;
       --connection to id ram, according to memory map in TrbNetRegIO
-      DATA_OUT : out std_logic_vector(15 downto 0);
-      ADDR_OUT : out std_logic_vector(2 downto 0);
-      WRITE_OUT: out std_logic;
-      TEMP_OUT : out std_logic_vector(11 downto 0);
-      STAT     : out std_logic_vector(31 downto 0)
+      DATA_OUT  : out   std_logic_vector(15 downto 0);
+      ADDR_OUT  : out   std_logic_vector(2 downto 0);
+      WRITE_OUT : out   std_logic;
+      TEMP_OUT  : out   std_logic_vector(11 downto 0);
+      STAT      : out   std_logic_vector(31 downto 0)
       );
   end component;
-  
+
   component vulom_interface
     generic (
       TRBNET_ENABLE : integer range 0 to 1);
@@ -474,50 +480,50 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       LVL1_TRIGGER_CODE   : out std_logic_vector(3 downto 0);
       LVL1_TRIGGER_TAG    : out std_logic_vector(7 downto 0)
       );
-  end component;  
-  
+  end component;
+
   component etrax_interfacev2
     generic (
-      ENABLE_DMA : natural;
-      RW_SYSTEM : natural;
+      ENABLE_DMA          : natural;
+      RW_SYSTEM           : natural;
       RW_REGISTERS_NUMBER : natural;
-      R_REGISTERS_NUMBER : natural;
-      TRBNET_ENABLE : natural
+      R_REGISTERS_NUMBER  : natural;
+      TRBNET_ENABLE       : natural
       );
     port (
-      CLK                     : in    std_logic;
-      RESET                   : in    std_logic;
-      DATA_BUS                : in    std_logic_vector(31 downto 0);
-      ETRAX_DATA_BUS_B        : inout std_logic_vector(16 downto 0);
-      ETRAX_DATA_BUS_B_17     : in std_logic;--_vector(17 downto 0);
-      ETRAX_DATA_BUS_C        : inout std_logic_vector(17 downto 0);
-      ETRAX_DATA_BUS_E        : inout    std_logic_vector(9 downto 8);
-      IPU_READY_IN            : in    std_logic;
-      IPU_DATAREADY_OUT       : out   std_logic;
-      IPU_DATA_OUT            : out   std_logic_vector(31 downto 0);
-      DATA_VALID              : in    std_logic;
-      ETRAX_BUS_BUSY          : in   std_logic;
-      ETRAX_IS_READY_TO_READ  : out   std_logic;
-      TDC_TCK                 : out   std_logic;
-      TDC_TDI                 : out   std_logic;
-      TDC_TMS                 : out   std_logic;
-      TDC_TRST                : out   std_logic;
-      TDC_TDO                 : in    std_logic;
-      TDC_RESET               : out   std_logic;
-      EXTERNAL_ADDRESS        : out   std_logic_vector(31 downto 0);
-      EXTERNAL_DATA_OUT       : out std_logic_vector(31 downto 0);
-      EXTERNAL_DATA_IN        : in std_logic_vector(31 downto 0);
-      EXTERNAL_ACK            : out   std_logic;
-      EXTERNAL_VALID          : in    std_logic;
-      EXTERNAL_MODE           : out   std_logic_vector(15 downto 0);
-      RW_REGISTER             : out   std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
-      R_REGISTER              : in    std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
-      LVL2_VALID              : in    std_logic;
-      TRB_LVL2_BUSY           : in    std_logic
+      CLK                    : in    std_logic;
+      RESET                  : in    std_logic;
+      DATA_BUS               : in    std_logic_vector(31 downto 0);
+      ETRAX_DATA_BUS_B       : inout std_logic_vector(16 downto 0);
+      ETRAX_DATA_BUS_B_17    : in    std_logic;  --_vector(17 downto 0);
+      ETRAX_DATA_BUS_C       : inout std_logic_vector(17 downto 0);
+      ETRAX_DATA_BUS_E       : inout std_logic_vector(9 downto 8);
+      IPU_READY_IN           : in    std_logic;
+      IPU_DATAREADY_OUT      : out   std_logic;
+      IPU_DATA_OUT           : out   std_logic_vector(31 downto 0);
+      DATA_VALID             : in    std_logic;
+      ETRAX_BUS_BUSY         : in    std_logic;
+      ETRAX_IS_READY_TO_READ : out   std_logic;
+      TDC_TCK                : out   std_logic;
+      TDC_TDI                : out   std_logic;
+      TDC_TMS                : out   std_logic;
+      TDC_TRST               : out   std_logic;
+      TDC_TDO                : in    std_logic;
+      TDC_RESET              : out   std_logic;
+      EXTERNAL_ADDRESS       : out   std_logic_vector(31 downto 0);
+      EXTERNAL_DATA_OUT      : out   std_logic_vector(31 downto 0);
+      EXTERNAL_DATA_IN       : in    std_logic_vector(31 downto 0);
+      EXTERNAL_ACK           : out   std_logic;
+      EXTERNAL_VALID         : in    std_logic;
+      EXTERNAL_MODE          : out   std_logic_vector(15 downto 0);
+      RW_REGISTER            : out   std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+      R_REGISTER             : in    std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+      LVL2_VALID             : in    std_logic;
+      TRB_LVL2_BUSY          : in    std_logic
       );
-    end component;
+  end component;
+
 
-  
   component dsp_interface
     port (
       -- signal to/from dsp
@@ -545,8 +551,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       ACKNOWLEDGE        : in    std_logic;
       DEBUGSTATE_MACHINE : out   std_logic_vector(31 downto 0)
       );
-   end component;
-  
+  end component;
+
   component dtu_interface
     port (
       CLK                   : in  std_logic;
@@ -570,7 +576,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       LVL2_TAG              : out std_logic_vector(7 downto 0);
       LVL2_BUSY             : in  std_logic;
       LVL2_TRB_ACK          : in  std_logic;
-      DTU_DEBUG_00          : out std_logic_vector( 31 downto 0));
+      DTU_DEBUG_00          : out std_logic_vector(31 downto 0));
   end component;
 
   component sdram_interface
@@ -598,7 +604,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       DEBUGSTATE_MACHINE : out   std_logic_vector(31 downto 0)
       );
   end component;
-  
+
   component ctu
     port (
       CLK              : in  std_logic;
@@ -620,24 +626,24 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
 
   component optical_dtu
     port (
-      CLK                    : in  std_logic;
-      RX_CLK                 : in  std_logic;
-      TX_CLK                 : in  std_logic;
-      RESET                  : in  std_logic;
-      OPT_DATA_IN            : in  std_logic_vector(15 downto 0);
-      OPT_DATA_OUT           : out std_logic_vector;
-      OPT_DATA_VALID_IN      : in  std_logic;
-      OPT_DATA_ERR           : in  std_logic;
-      OPT_DATA_SEND          : out std_logic;
-      LVL1_TRIGGER           : out std_logic;
-      LVL1_TRIGGER_CODE      : out std_logic_vector(3 downto 0);
-      LVL1_TRIGGER_TAG       : out std_logic_vector(7 downto 0);
-      LVL2_TRIGGER           : out std_logic;
-      LVL2_TRIGGER_CODE      : out std_logic;
-      LVL2_TRIGGER_TAG       : out std_logic_vector(7 downto 0);
-      LVL1_BUSY              : in  std_logic;
-      LVL2_BUSY              : in  std_logic;
-      OPT_DTU_DEBUG_REGISTER_00 :out std_logic_vector(31 downto 0);
+      CLK                       : in  std_logic;
+      RX_CLK                    : in  std_logic;
+      TX_CLK                    : in  std_logic;
+      RESET                     : in  std_logic;
+      OPT_DATA_IN               : in  std_logic_vector(15 downto 0);
+      OPT_DATA_OUT              : out std_logic_vector;
+      OPT_DATA_VALID_IN         : in  std_logic;
+      OPT_DATA_ERR              : in  std_logic;
+      OPT_DATA_SEND             : out std_logic;
+      LVL1_TRIGGER              : out std_logic;
+      LVL1_TRIGGER_CODE         : out std_logic_vector(3 downto 0);
+      LVL1_TRIGGER_TAG          : out std_logic_vector(7 downto 0);
+      LVL2_TRIGGER              : out std_logic;
+      LVL2_TRIGGER_CODE         : out std_logic;
+      LVL2_TRIGGER_TAG          : out std_logic_vector(7 downto 0);
+      LVL1_BUSY                 : in  std_logic;
+      LVL2_BUSY                 : in  std_logic;
+      OPT_DTU_DEBUG_REGISTER_00 : out std_logic_vector(31 downto 0);
       OPT_DTU_DEBUG_REGISTER_01 : out std_logic_vector(31 downto 0));
   end component;
 
@@ -660,11 +666,11 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       LVL2_CODE         : in  std_logic;
       LVL2_TAG          : in  std_logic_vector(7 downto 0);
       LVL2_BUSY         : out std_logic;
-      OPT_CTU_DEBUG_00     : out std_logic_vector(31 downto 0);
-      OPT_CTU_DEBUG_01     : out std_logic_vector(31 downto 0)
+      OPT_CTU_DEBUG_00  : out std_logic_vector(31 downto 0);
+      OPT_CTU_DEBUG_01  : out std_logic_vector(31 downto 0)
       );
   end component;
-  
+
   component simpleupcounter_32bit
     port (
       QOUT : out std_logic_vector(31 downto 0);
@@ -672,7 +678,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       CLK  : in  std_logic;
       CLR  : in  std_logic);
   end component;
-  
+
   component up_down_counter
     generic (
       NUMBER_OF_BITS : positive);
@@ -683,7 +689,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       UP_IN     : in  std_logic;
       DOWN_IN   : in  std_logic);
   end component;
-  
+
   component DCM_100MHz_to_200MHz
     port (
       CLKIN_N_IN        : in  std_logic;
@@ -735,257 +741,257 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
 -------------------------------------------------------------------------------
 -- components for trbnet - cts
 -------------------------------------------------------------------------------
-   component trb_net16_endpoint_hades_cts
-     generic (
-       USE_CHANNEL               : channel_config_t;
-       IBUF_DEPTH                : channel_config_t;
-       FIFO_TO_INT_DEPTH         : channel_config_t;
-       FIFO_TO_APL_DEPTH         : channel_config_t;
-       INIT_CAN_SEND_DATA        : channel_config_t;
-       REPLY_CAN_SEND_DATA       : channel_config_t;
-       REPLY_CAN_RECEIVE_DATA    : channel_config_t;
-       USE_CHECKSUM              : channel_config_t;
-       APL_WRITE_ALL_WORDS       : channel_config_t;
-       BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
-       REGIO_NUM_STAT_REGS       : integer range 0 to 6;
-       REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
-       REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
-       REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
-       REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
-       REGIO_USE_DAT_PORT        : integer range 0 to 1;
-       REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
-       REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
-       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
-       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
-       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
-       REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
-       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
-       REGIO_USE_1WIRE_INTERFACE : integer;
-       CLOCK_FREQUENCY           : integer range 1 to 200);
-     port (
-       CLK                       : in    std_logic;
-       RESET                     : in    std_logic;
-       CLK_EN                    : in    std_logic;
-       MED_DATAREADY_OUT         : out   std_logic;
-       MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       MED_READ_IN               : in    std_logic;
-       MED_DATAREADY_IN          : in    std_logic;
-       MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       MED_READ_OUT              : out   std_logic;
-       MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
-       MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
-       TRG_SEND_IN               : in    std_logic;
-       TRG_TYPE_IN               : in    std_logic_vector (3 downto 0);
-       TRG_NUMBER_IN             : in    std_logic_vector (15 downto 0);
-       TRG_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
-       TRG_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
-       TRG_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
-       TRG_BUSY_OUT              : out   std_logic;
-       IPU_SEND_IN               : in    std_logic;
-       IPU_TYPE_IN               : in    std_logic_vector (3 downto 0);
-       IPU_NUMBER_IN             : in    std_logic_vector (15 downto 0);
-       IPU_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
-       IPU_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
-       IPU_DATA_OUT              : out   std_logic_vector (31 downto 0);
-       IPU_DATAREADY_OUT         : out   std_logic;
-       IPU_READ_IN               : in    std_logic;
-       IPU_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
-       IPU_BUSY_OUT              : out   std_logic;
-       REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
-       REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-       REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-       REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-       REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
-       REGIO_READ_ENABLE_OUT     : out   std_logic;
-       REGIO_WRITE_ENABLE_OUT    : out   std_logic;
-       REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
-       REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
-       REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
-       REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
-       REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
-       REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
-       REGIO_TIMEOUT_OUT         : out   std_logic;
-       REGIO_ONEWIRE_INOUT       : inout std_logic;
-       REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
-       REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
-       TRIGGER_MONITOR_IN        : in    std_logic;
-       GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
-       LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
-       TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
-       TIMER_US_TICK_OUT         : out   std_logic;
-       STAT_DEBUG_1              : out   std_logic_vector(31 downto 0);
-       STAT_DEBUG_2              : out   std_logic_vector(31 downto 0));
-   end component;
+  component trb_net16_endpoint_hades_cts
+    generic (
+      USE_CHANNEL               : channel_config_t;
+      IBUF_DEPTH                : channel_config_t;
+      FIFO_TO_INT_DEPTH         : channel_config_t;
+      FIFO_TO_APL_DEPTH         : channel_config_t;
+      INIT_CAN_SEND_DATA        : channel_config_t;
+      REPLY_CAN_SEND_DATA       : channel_config_t;
+      REPLY_CAN_RECEIVE_DATA    : channel_config_t;
+      USE_CHECKSUM              : channel_config_t;
+      APL_WRITE_ALL_WORDS       : channel_config_t;
+      BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
+      REGIO_NUM_STAT_REGS       : integer range 0 to 6;
+      REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
+      REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
+      REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
+      REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
+      REGIO_USE_DAT_PORT        : integer range 0 to 1;
+      REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
+      REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
+      REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
+      REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
+      REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
+      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
+      REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
+      REGIO_USE_1WIRE_INTERFACE : integer;
+      CLOCK_FREQUENCY           : integer range 1 to 200);
+    port (
+      CLK                       : in    std_logic;
+      RESET                     : in    std_logic;
+      CLK_EN                    : in    std_logic;
+      MED_DATAREADY_OUT         : out   std_logic;
+      MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      MED_READ_IN               : in    std_logic;
+      MED_DATAREADY_IN          : in    std_logic;
+      MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      MED_READ_OUT              : out   std_logic;
+      MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
+      MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
+      TRG_SEND_IN               : in    std_logic;
+      TRG_TYPE_IN               : in    std_logic_vector (3 downto 0);
+      TRG_NUMBER_IN             : in    std_logic_vector (15 downto 0);
+      TRG_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
+      TRG_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
+      TRG_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
+      TRG_BUSY_OUT              : out   std_logic;
+      IPU_SEND_IN               : in    std_logic;
+      IPU_TYPE_IN               : in    std_logic_vector (3 downto 0);
+      IPU_NUMBER_IN             : in    std_logic_vector (15 downto 0);
+      IPU_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
+      IPU_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
+      IPU_DATA_OUT              : out   std_logic_vector (31 downto 0);
+      IPU_DATAREADY_OUT         : out   std_logic;
+      IPU_READ_IN               : in    std_logic;
+      IPU_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
+      IPU_BUSY_OUT              : out   std_logic;
+      REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+      REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+      REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+      REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+      REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
+      REGIO_READ_ENABLE_OUT     : out   std_logic;
+      REGIO_WRITE_ENABLE_OUT    : out   std_logic;
+      REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
+      REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
+      REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
+      REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
+      REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
+      REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
+      REGIO_TIMEOUT_OUT         : out   std_logic;
+      REGIO_ONEWIRE_INOUT       : inout std_logic;
+      REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
+      REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
+      TRIGGER_MONITOR_IN        : in    std_logic;
+      GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
+      LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
+      TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
+      TIMER_US_TICK_OUT         : out   std_logic;
+      STAT_DEBUG_1              : out   std_logic_vector(31 downto 0);
+      STAT_DEBUG_2              : out   std_logic_vector(31 downto 0));
+  end component;
 
 --   -----------------------------------------------------------------------------
 --   -- components for trbnet - hades end point
 --   -----------------------------------------------------------------------------
 
-   component trb_net16_endpoint_hades_full
-     generic (
-       USE_CHANNEL               : channel_config_t;
-       IBUF_DEPTH                : channel_config_t;
-       FIFO_TO_INT_DEPTH         : channel_config_t;
-       FIFO_TO_APL_DEPTH         : channel_config_t;
-       IBUF_SECURE_MODE          : channel_config_t;
-       API_SECURE_MODE_TO_APL    : channel_config_t;
-       API_SECURE_MODE_TO_INT    : channel_config_t;
-       OBUF_DATA_COUNT_WIDTH     : integer range 0 to 7;
-       INIT_CAN_SEND_DATA        : channel_config_t;
-       REPLY_CAN_SEND_DATA       : channel_config_t;
-       REPLY_CAN_RECEIVE_DATA    : channel_config_t;
-       USE_CHECKSUM              : channel_config_t;
-       APL_WRITE_ALL_WORDS       : channel_config_t;
-       BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
-       REGIO_NUM_STAT_REGS       : integer range 0 to 6;
-       REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
-       REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
-       REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
-       REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
-       REGIO_USE_DAT_PORT        : integer range 0 to 1;
-       REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
-       REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
-       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
-       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
-       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
-       REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
-       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
-       REGIO_USE_1WIRE_INTERFACE : integer;
-       CLOCK_FREQUENCY           : integer range 1 to 200);
-     port (
-       CLK                       : in    std_logic;
-       RESET                     : in    std_logic;
-       CLK_EN                    : in    std_logic;
-       MED_DATAREADY_OUT         : out   std_logic;
-       MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       MED_READ_IN               : in    std_logic;
-       MED_DATAREADY_IN          : in    std_logic;
-       MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       MED_READ_OUT              : out   std_logic;
-       MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
-       MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
-       LVL1_TRG_TYPE_OUT         : out   std_logic_vector(3 downto 0);
-       LVL1_TRG_RECEIVED_OUT     : out   std_logic;
-       LVL1_TRG_NUMBER_OUT       : out   std_logic_vector(15 downto 0);
-       LVL1_TRG_CODE_OUT         : out   std_logic_vector(7 downto 0);
-       LVL1_TRG_INFORMATION_OUT  : out   std_logic_vector(7 downto 0);
-       LVL1_ERROR_PATTERN_IN     : in    std_logic_vector(31 downto 0)                            := x"00000000";
-       LVL1_TRG_RELEASE_IN       : in    std_logic                                                := '0';
-       IPU_NUMBER_OUT            : out   std_logic_vector (15 downto 0);
-       IPU_INFORMATION_OUT       : out   std_logic_vector (7 downto 0);
-       IPU_START_READOUT_OUT     : out   std_logic;
-       IPU_DATA_IN               : in    std_logic_vector (31 downto 0);
-       IPU_DATAREADY_IN          : in    std_logic;
-       IPU_READOUT_FINISHED_IN   : in    std_logic;
-       IPU_READ_OUT              : out   std_logic;
-       IPU_LENGTH_IN             : in    std_logic_vector (15 downto 0);
-       IPU_ERROR_PATTERN_IN      : in    std_logic_vector (31 downto 0);
-       REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
-       REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-       REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-       REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-       REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
-       REGIO_READ_ENABLE_OUT     : out   std_logic;
-       REGIO_WRITE_ENABLE_OUT    : out   std_logic;
-       REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
-       REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
-       REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
-       REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
-       REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
-       REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
-       REGIO_TIMEOUT_OUT         : out   std_logic;
-       REGIO_IDRAM_DATA_IN       : in    std_logic_vector(15 downto 0)                            := (others => '0');
-       REGIO_IDRAM_DATA_OUT      : out   std_logic_vector(15 downto 0);
-       REGIO_IDRAM_ADDR_IN       : in    std_logic_vector(2 downto 0)                             := "000";
-       REGIO_IDRAM_WR_IN         : in    std_logic                                                := '0';
-       REGIO_ONEWIRE_INOUT       : inout std_logic;
-       REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
-       REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
-       TRIGGER_MONITOR_IN        : in    std_logic;
-       GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
-       LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
-       TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
-       TIMER_US_TICK_OUT         : out   std_logic;
-       STAT_DEBUG_IPU            : out   std_logic_vector (31 downto 0);
-       STAT_DEBUG_1              : out   std_logic_vector (31 downto 0);
-       STAT_DEBUG_2              : out   std_logic_vector (31 downto 0);
-       MED_STAT_OP               : out   std_logic_vector (15 downto 0);
-       CTRL_MPLEX                : in    std_logic_vector (31 downto 0);
-       IOBUF_CTRL_GEN            : in    std_logic_vector (4*32-1 downto 0);
-       STAT_ONEWIRE              : out   std_logic_vector (31 downto 0);
-       STAT_ADDR_DEBUG           : out   std_logic_vector (15 downto 0));
-   end component;
+  component trb_net16_endpoint_hades_full
+    generic (
+      USE_CHANNEL               : channel_config_t;
+      IBUF_DEPTH                : channel_config_t;
+      FIFO_TO_INT_DEPTH         : channel_config_t;
+      FIFO_TO_APL_DEPTH         : channel_config_t;
+      IBUF_SECURE_MODE          : channel_config_t;
+      API_SECURE_MODE_TO_APL    : channel_config_t;
+      API_SECURE_MODE_TO_INT    : channel_config_t;
+      OBUF_DATA_COUNT_WIDTH     : integer range 0 to 7;
+      INIT_CAN_SEND_DATA        : channel_config_t;
+      REPLY_CAN_SEND_DATA       : channel_config_t;
+      REPLY_CAN_RECEIVE_DATA    : channel_config_t;
+      USE_CHECKSUM              : channel_config_t;
+      APL_WRITE_ALL_WORDS       : channel_config_t;
+      BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
+      REGIO_NUM_STAT_REGS       : integer range 0 to 6;
+      REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
+      REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
+      REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
+      REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
+      REGIO_USE_DAT_PORT        : integer range 0 to 1;
+      REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
+      REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
+      REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
+      REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
+      REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
+      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
+      REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
+      REGIO_USE_1WIRE_INTERFACE : integer;
+      CLOCK_FREQUENCY           : integer range 1 to 200);
+    port (
+      CLK                       : in    std_logic;
+      RESET                     : in    std_logic;
+      CLK_EN                    : in    std_logic;
+      MED_DATAREADY_OUT         : out   std_logic;
+      MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      MED_READ_IN               : in    std_logic;
+      MED_DATAREADY_IN          : in    std_logic;
+      MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      MED_READ_OUT              : out   std_logic;
+      MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
+      MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
+      LVL1_TRG_TYPE_OUT         : out   std_logic_vector(3 downto 0);
+      LVL1_TRG_RECEIVED_OUT     : out   std_logic;
+      LVL1_TRG_NUMBER_OUT       : out   std_logic_vector(15 downto 0);
+      LVL1_TRG_CODE_OUT         : out   std_logic_vector(7 downto 0);
+      LVL1_TRG_INFORMATION_OUT  : out   std_logic_vector(7 downto 0);
+      LVL1_ERROR_PATTERN_IN     : in    std_logic_vector(31 downto 0)                            := x"00000000";
+      LVL1_TRG_RELEASE_IN       : in    std_logic                                                := '0';
+      IPU_NUMBER_OUT            : out   std_logic_vector (15 downto 0);
+      IPU_INFORMATION_OUT       : out   std_logic_vector (7 downto 0);
+      IPU_START_READOUT_OUT     : out   std_logic;
+      IPU_DATA_IN               : in    std_logic_vector (31 downto 0);
+      IPU_DATAREADY_IN          : in    std_logic;
+      IPU_READOUT_FINISHED_IN   : in    std_logic;
+      IPU_READ_OUT              : out   std_logic;
+      IPU_LENGTH_IN             : in    std_logic_vector (15 downto 0);
+      IPU_ERROR_PATTERN_IN      : in    std_logic_vector (31 downto 0);
+      REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+      REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+      REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+      REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+      REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
+      REGIO_READ_ENABLE_OUT     : out   std_logic;
+      REGIO_WRITE_ENABLE_OUT    : out   std_logic;
+      REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
+      REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
+      REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
+      REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
+      REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
+      REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
+      REGIO_TIMEOUT_OUT         : out   std_logic;
+      REGIO_IDRAM_DATA_IN       : in    std_logic_vector(15 downto 0)                            := (others => '0');
+      REGIO_IDRAM_DATA_OUT      : out   std_logic_vector(15 downto 0);
+      REGIO_IDRAM_ADDR_IN       : in    std_logic_vector(2 downto 0)                             := "000";
+      REGIO_IDRAM_WR_IN         : in    std_logic                                                := '0';
+      REGIO_ONEWIRE_INOUT       : inout std_logic;
+      REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
+      REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
+      TRIGGER_MONITOR_IN        : in    std_logic;
+      GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
+      LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
+      TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
+      TIMER_US_TICK_OUT         : out   std_logic;
+      STAT_DEBUG_IPU            : out   std_logic_vector (31 downto 0);
+      STAT_DEBUG_1              : out   std_logic_vector (31 downto 0);
+      STAT_DEBUG_2              : out   std_logic_vector (31 downto 0);
+      MED_STAT_OP               : out   std_logic_vector (15 downto 0);
+      CTRL_MPLEX                : in    std_logic_vector (31 downto 0);
+      IOBUF_CTRL_GEN            : in    std_logic_vector (4*32-1 downto 0);
+      STAT_ONEWIRE              : out   std_logic_vector (31 downto 0);
+      STAT_ADDR_DEBUG           : out   std_logic_vector (15 downto 0));
+  end component;
 
 --   -----------------------------------------------------------------------------
 --   -- components from trbnet - media ineterface
 --   -----------------------------------------------------------------------------
-    
-   component trb_net16_med_tlk
-     port (
-       RESET              : in  std_logic;
-       CLK                : in  std_logic;
-       TLK_CLK            : in  std_logic;
-       TLK_ENABLE         : out std_logic;
-       TLK_LCKREFN        : out std_logic;
-       TLK_LOOPEN         : out std_logic;
-       TLK_PRBSEN         : out std_logic;
-       TLK_RXD            : in  std_logic_vector(15 downto 0);
-       TLK_RX_CLK         : in  std_logic;
-       TLK_RX_DV          : in  std_logic;
-       TLK_RX_ER          : in  std_logic;
-       TLK_TXD            : out std_logic_vector(15 downto 0);
-       TLK_TX_EN          : out std_logic;
-       TLK_TX_ER          : out std_logic;
-       SFP_LOS            : in  std_logic;
-       SFP_TX_DIS         : out std_logic;
-       MED_DATAREADY_IN   : in  std_logic;
-       MED_READ_IN        : in  std_logic;
-       MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       MED_DATAREADY_OUT  : out std_logic;
-       MED_READ_OUT       : out std_logic;
-       MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-       MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-       STAT               : out std_logic_vector (63 downto 0);
-       STAT_MONITOR       : out std_logic_vector ( 100 downto 0);
-       STAT_OP            : out std_logic_vector (15 downto 0);
-       CTRL_OP            : in  std_logic_vector (15 downto 0));
-   end component;
-  
+
+  component trb_net16_med_tlk
+    port (
+      RESET              : in  std_logic;
+      CLK                : in  std_logic;
+      TLK_CLK            : in  std_logic;
+      TLK_ENABLE         : out std_logic;
+      TLK_LCKREFN        : out std_logic;
+      TLK_LOOPEN         : out std_logic;
+      TLK_PRBSEN         : out std_logic;
+      TLK_RXD            : in  std_logic_vector(15 downto 0);
+      TLK_RX_CLK         : in  std_logic;
+      TLK_RX_DV          : in  std_logic;
+      TLK_RX_ER          : in  std_logic;
+      TLK_TXD            : out std_logic_vector(15 downto 0);
+      TLK_TX_EN          : out std_logic;
+      TLK_TX_ER          : out std_logic;
+      SFP_LOS            : in  std_logic;
+      SFP_TX_DIS         : out std_logic;
+      MED_DATAREADY_IN   : in  std_logic;
+      MED_READ_IN        : in  std_logic;
+      MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      MED_DATAREADY_OUT  : out std_logic;
+      MED_READ_OUT       : out std_logic;
+      MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+      MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+      STAT               : out std_logic_vector (63 downto 0);
+      STAT_MONITOR       : out std_logic_vector (100 downto 0);
+      STAT_OP            : out std_logic_vector (15 downto 0);
+      CTRL_OP            : in  std_logic_vector (15 downto 0));
+  end component;
+
   -----------------------------------------------------------------------------
   -- SFP optical power and temperature --component !!!
   -----------------------------------------------------------------------------
-  
+
   component edge_to_pulse
     port (
       clock     : in  std_logic;
       en_clk    : in  std_logic;
       signal_in : in  std_logic;
       pulse     : out std_logic);
-    end component;
+  end component;
 -------------------------------------------------------------------------------
 -- SIGNALS
 -------------------------------------------------------------------------------
 --  constant VaaaaaaaaaERSION_NUMBER_TIME : integer := 1245150983;  --interface
-  constant HOW_MANY_CHANNELS   : integer := 1;
-  
+  constant HOW_MANY_CHANNELS : integer := 1;
+
   --clk
-  signal                           clk_lvds   : std_logic;
-  signal                           addon_clk  : std_logic;
-  signal                           clk        : std_logic;
-  signal                           clk50      : std_logic;
-  signal                           clk200     : std_logic;
-  signal                           locked_out : std_logic;
-  attribute period                            : string;
-  attribute period of clk                     : signal is "10 ns";
-  
+  signal clk_lvds         : std_logic;
+  signal addon_clk        : std_logic;
+  signal clk              : std_logic;
+  signal clk50            : std_logic;
+  signal clk200           : std_logic;
+  signal locked_out       : std_logic;
+  attribute period        : string;
+  attribute period of clk : signal is "10 ns";
+
   --reset
   signal global_reset_counter : std_logic_vector(3 downto 0) := x"0";
-  signal reset_i              : std_logic :='0';
+  signal reset_i              : std_logic                    := '0';
 
   --TDC
   signal tdc_clk                      : std_logic;
@@ -1029,18 +1035,18 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal lvl1_finished_i              : std_logic;
   signal lvl2_finished_i              : std_logic;
   signal start_tdc_readout_i          : std_logic;
-  
+
   --common signals for triggers 
-  signal lvl1_busy_i         : std_logic;
-  signal lvl2_busy_i         : std_logic;
-  signal lvl1_trigger_code_i : std_logic_vector(3 downto 0);
-  signal lvl1_trigger_tag_i  : std_logic_vector(15 downto 0);
-  signal lvl2_trigger_i      : std_logic;
-  signal lvl2_trigger_synch  : std_logic;
-  signal lvl1_trigger_i      : std_logic;
-  signal lvl2_trigger_code_i : std_logic_vector(3 downto 0) := x"0";
-  signal lvl2_trigger_tag_i  : std_logic_vector(15 downto 0) := x"0000";
-  signal lvl2_local_busy_i   : std_logic;
+  signal lvl1_busy_i              : std_logic;
+  signal lvl2_busy_i              : std_logic;
+  signal lvl1_trigger_code_i      : std_logic_vector(3 downto 0);
+  signal lvl1_trigger_tag_i       : std_logic_vector(15 downto 0);
+  signal lvl2_trigger_i           : std_logic;
+  signal lvl2_trigger_synch       : std_logic;
+  signal lvl1_trigger_i           : std_logic;
+  signal lvl2_trigger_code_i      : std_logic_vector(3 downto 0)  := x"0";
+  signal lvl2_trigger_tag_i       : std_logic_vector(15 downto 0) := x"0000";
+  signal lvl2_local_busy_i        : std_logic;
   --etrax 
   signal etrax_bus_busy_i         : std_logic;  --should go to busy logic !? 
   signal etrax_is_ready_to_read_i : std_logic;
@@ -1061,28 +1067,31 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal fpga_register_0f_i       : std_logic_vector(31 downto 0);
 --  signal r_register_i             : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
 --  signal rw_register_i            : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
-  type r_register_array is array(0 to R_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
-  signal r_register_i : r_register_array;
-  type rw_register_array is array(0 to RW_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
-  signal rw_register_i : rw_register_array;
-  signal fs_pc_i : std_logic_vector(17 downto 0);
-  signal fs_pb_i : std_logic_vector(16 downto 0);
-  signal fs_pb_17i : std_logic;
+  type   r_register_array is array(0 to R_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+  signal r_register_i             : r_register_array;
+  type   rw_register_array is array(0 to RW_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+  signal rw_register_i            : rw_register_array;
+  signal fs_pc_i                  : std_logic_vector(17 downto 0);
+  signal fs_pb_i                  : std_logic_vector(16 downto 0);
+  signal fs_pb_17i                : std_logic;
   -- tlk
-  signal tlk_rx_clk_r      : std_logic_vector(3 downto 0);
-  signal tlk_clk_r         : std_logic_vector(0 downto 0);
-  signal tlk_register_00_i : std_logic_vector(31 downto 0);
-  signal tlk_register_01_i : std_logic_vector(31 downto 0);
-  signal cv_i              : std_logic_vector(7 downto 0);
-  signal rx_k_i            : std_logic_vector(7 downto 0);
-  signal tx_k_i            : std_logic_vector(7 downto 0);
-  signal media_status_i    : std_logic_vector(15 downto 0);
-  signal media_control_i   : std_logic_vector(15 downto 0);
-  signal link_debug_i      : std_logic_vector(31 downto 0);
-  signal sfp_los_vect      : std_logic_vector(0 downto 0);
-  signal tlk_rxd_i         : std_logic_vector(63 downto 0);
-  signal tlk_txd_i         : std_logic_vector(63 downto 0);
-
+  signal tlk_rx_clk_r             : std_logic_vector(3 downto 0);
+  signal tlk_clk_r                : std_logic_vector(0 downto 0);
+  signal tlk_register_00_i        : std_logic_vector(31 downto 0);
+  signal tlk_register_01_i        : std_logic_vector(31 downto 0);
+  signal cv_i                     : std_logic_vector(7 downto 0);
+  signal rx_k_i                   : std_logic_vector(7 downto 0);
+  signal tx_k_i                   : std_logic_vector(7 downto 0);
+  signal media_status_i           : std_logic_vector(15 downto 0);
+  signal media_control_i          : std_logic_vector(15 downto 0);
+  signal link_debug_i             : std_logic_vector(31 downto 0);
+  signal sfp_los_vect             : std_logic_vector(0 downto 0);
+  signal tlk_rxd_i                : std_logic_vector(63 downto 0);
+  signal tlk_txd_i                : std_logic_vector(63 downto 0);
+
+  --sfp
+  signal sfp_data_out       : std_logic_vector(15 downto 0);
+  signal sfp_external_valid : std_logic;
   
   --rw external interaface
   signal external_address_i  : std_logic_vector(31 downto 0);
@@ -1122,14 +1131,14 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal vsd_cs_i               : std_logic;
 
   --scalers
-  type scaler_counter_arr is array(0 to 7) of std_logic_vector(31 downto 0);
+  type   scaler_counter_arr is array(0 to 7) of std_logic_vector(31 downto 0);
   signal scaler_counter : scaler_counter_arr;
   signal scaler_pulse   : std_logic_vector(7 downto 0);
 
   --ctu
   signal lvl1_ctu_status_i : std_logic_vector(31 downto 0);
   signal lvl2_ctu_status_i : std_logic_vector(31 downto 0);
-  
+
   --dtu
   signal dtu_debug_00_i            : std_logic_vector(31 downto 0);
   signal busy_or_error             : std_logic;
@@ -1137,94 +1146,94 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal optical_tdc_trigger_reg_2 : std_logic;
   signal optical_tdc_trigger_reg_3 : std_logic;
   signal optical_tdc_trigger       : std_logic;
-  
+
   --other
-  signal check_pulse        : std_logic;
-  signal check_counter      : std_logic_vector(16 downto 0);
-  signal lvds_add_on_data   : std_logic_vector(31 downto 0);
-  signal ado_lv_out_i   : std_logic_vector(4 downto 0);
-  
+  signal check_pulse      : std_logic;
+  signal check_counter    : std_logic_vector(16 downto 0);
+  signal lvds_add_on_data : std_logic_vector(31 downto 0);
+  signal ado_lv_out_i     : std_logic_vector(4 downto 0);
+
   signal self_trigg_counter : std_logic_vector(7 downto 0);
-  signal r_register_vector             : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
-  signal rw_register_vector            : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
-  type temp_sens_array is array (3 downto 0) of std_logic_vector(11 downto 0);
-  signal temp_sens_i : temp_sens_array;
-  type temp_sens_status_array is array (3 downto 0) of std_logic_vector(31 downto 0);
+  signal r_register_vector  : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+  signal rw_register_vector : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+  type   temp_sens_array is array (3 downto 0) of std_logic_vector(11 downto 0);
+  signal temp_sens_i        : temp_sens_array;
+  type   temp_sens_status_array is array (3 downto 0) of std_logic_vector(31 downto 0);
   signal temp_sens_status_i : temp_sens_status_array;
-  
- -- media interface
-  signal med_dataready_out_i     : std_logic_vector(0 downto 0);
-  signal med_data_OUT_i          : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal med_packet_num_out_i    : std_logic_vector (HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
-  signal med_read_in_i           : std_logic_vector(0 downto 0);
-  signal med_dataready_in_i      : std_logic_vector(0 downto 0);
-  signal med_data_in_i           : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal med_read_out_i          : std_logic_vector(0 downto 0);
-  signal med_stat_op_in_i           : std_logic_vector (15 downto 0);
-  signal med_ctrl_op_out_i           : std_logic_vector (15 downto 0);
-  signal med_packet_num_in_i        : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
-  
+
+  -- media interface
+  signal med_dataready_out_i  : std_logic_vector(0 downto 0);
+  signal med_data_OUT_i       : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+  signal med_packet_num_out_i : std_logic_vector (HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+  signal med_read_in_i        : std_logic_vector(0 downto 0);
+  signal med_dataready_in_i   : std_logic_vector(0 downto 0);
+  signal med_data_in_i        : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+  signal med_read_out_i       : std_logic_vector(0 downto 0);
+  signal med_stat_op_in_i     : std_logic_vector (15 downto 0);
+  signal med_ctrl_op_out_i    : std_logic_vector (15 downto 0);
+  signal med_packet_num_in_i  : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+
   --trbnet -cts
-  signal not_ipu_dataready_out_i : std_logic;
+  signal not_ipu_dataready_out_i     : std_logic;
   signal ipu_dataready_out_end_pulse : std_logic;
-  signal dummy_lvl1_trigger : std_logic;
-      --lvl1
-   signal trg_send_in_i               : std_logic;
-   signal trg_type_in_i               : std_logic_vector (3 downto 0);
-   signal trg_number_in_i             : std_logic_vector (15 downto 0);
-   signal trg_information_in_i        : std_logic_vector (7 downto 0);
-   signal trg_status_bits_out_i       : std_logic_vector (31 downto 0);
-      --lvl2
-   signal trg_busy_out_i              : std_logic:='0';
-   signal ipu_send_in_i               : std_logic;
-   signal ipu_type_in_i               : std_logic_vector (3 downto 0);
-   signal ipu_number_in_i             : std_logic_vector (15 downto 0);
-   signal ipu_information_in_i        : std_logic_vector (7 downto 0);
-   signal ipu_data_out_i              : std_logic_vector (31 downto 0);
-   signal ipu_dataready_out_i         : std_logic;
-   signal ipu_read_in_i               : std_logic;
-   signal ipu_status_bits_out_i       : std_logic_vector (31 downto 0);
-   signal ipu_busy_out_i              : std_logic:='0';
-
-      --reg io
-   signal regio_common_stat_reg_in_i  : std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
-   signal regio_common_ctrl_reg_out_i : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal dummy_lvl1_trigger          : std_logic;
+  --lvl1
+  signal trg_send_in_i               : std_logic;
+  signal trg_type_in_i               : std_logic_vector (3 downto 0);
+  signal trg_number_in_i             : std_logic_vector (15 downto 0);
+  signal trg_information_in_i        : std_logic_vector (7 downto 0);
+  signal trg_status_bits_out_i       : std_logic_vector (31 downto 0);
+  --lvl2
+  signal trg_busy_out_i              : std_logic := '0';
+  signal ipu_send_in_i               : std_logic;
+  signal ipu_type_in_i               : std_logic_vector (3 downto 0);
+  signal ipu_number_in_i             : std_logic_vector (15 downto 0);
+  signal ipu_information_in_i        : std_logic_vector (7 downto 0);
+  signal ipu_data_out_i              : std_logic_vector (31 downto 0);
+  signal ipu_dataready_out_i         : std_logic;
+  signal ipu_read_in_i               : std_logic;
+  signal ipu_status_bits_out_i       : std_logic_vector (31 downto 0);
+  signal ipu_busy_out_i              : std_logic := '0';
+
+  --reg io
+  signal regio_common_stat_reg_in_i  : std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+  signal regio_common_ctrl_reg_out_i : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
 --   constant REGIO_NUM_STAT_REGS : integer := R_REGISTERS_NUMBER;
 --   constant REGIO_NUM_CTRL_REGS : integer := RW_REGISTERS_NUMBER;
-   signal regio_registers_in_i        : std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-   signal regio_registers_out_i       : std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-   signal regio_addr_out_i            : std_logic_vector(16-1 downto 0);
-   signal regio_read_enable_out_i     : std_logic;
-   signal regio_write_enable_out_i    : std_logic;
-   signal regio_data_out_i            : std_logic_vector(32-1 downto 0);
-   signal regio_data_in_i             : std_logic_vector(32-1 downto 0)                          := (others => '0');
-   signal regio_dataready_in_i        : std_logic                                                := '0';
-   signal regio_no_more_data_in_i     : std_logic                                                := '0';
-   signal regio_write_ack_in_i        : std_logic                                                := '0';
-   signal regio_unknown_addr_in_i     : std_logic                                                := '0';
-   signal regio_timeout_out_i         : std_logic;
-   signal regio_onewire_inout_i       : std_logic;
-   signal regio_onewire_monitor_out_i : std_logic;
-   signal regio_onewire_monitor_in_i  : std_logic;
-   
+  signal regio_registers_in_i        : std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+  signal regio_registers_out_i       : std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+  signal regio_addr_out_i            : std_logic_vector(16-1 downto 0);
+  signal regio_read_enable_out_i     : std_logic;
+  signal regio_write_enable_out_i    : std_logic;
+  signal regio_data_out_i            : std_logic_vector(32-1 downto 0);
+  signal regio_data_in_i             : std_logic_vector(32-1 downto 0)                          := (others => '0');
+  signal regio_dataready_in_i        : std_logic                                                := '0';
+  signal regio_no_more_data_in_i     : std_logic                                                := '0';
+  signal regio_write_ack_in_i        : std_logic                                                := '0';
+  signal regio_unknown_addr_in_i     : std_logic                                                := '0';
+  signal regio_timeout_out_i         : std_logic;
+  signal regio_onewire_inout_i       : std_logic;
+  signal regio_onewire_monitor_out_i : std_logic;
+  signal regio_onewire_monitor_in_i  : std_logic;
+
 --trbnet endpoint
-   signal trigger_monitor_in_i        : std_logic;
-   signal global_time_out_i           : std_logic_vector(31 downto 0);
-   signal local_time_out_i            : std_logic_vector(7 downto 0);
-   signal time_since_last_trg_out_i   : std_logic_vector(31 downto 0);
-   signal timer_us_tick_out_i         : std_logic;
-   signal stat_debug_1_i              : std_logic_vector(31 downto 0);
-   signal stat_debug_2_i              : std_logic_vector(31 downto 0);
-   signal regio_idram_data_in_i       : std_logic_vector(15 downto 0)                            := (others => '0');
-   signal regio_idram_data_out_i      : std_logic_vector(15 downto 0);
-   signal regio_idram_addr_in_i       : std_logic_vector(2 downto 0)                             := "000";
-   signal regio_idram_wr_in_i         : std_logic                                                := '0';
-   signal stat_debug_ipu_i            : std_logic_vector (31 downto 0);
-   signal ipu_read_out_i              : std_logic                                                := '0';
-   signal ipu_dataready_in_i          : std_logic;
-   signal lvl2_trigger_i_pulse        : std_logic;
-   signal cntr_for_dummy_header       : std_logic_vector(1 downto 0) := "00";
-   signal ipu_data_in_i : std_logic_vector(31 downto 0);
+  signal trigger_monitor_in_i      : std_logic;
+  signal global_time_out_i         : std_logic_vector(31 downto 0);
+  signal local_time_out_i          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg_out_i : std_logic_vector(31 downto 0);
+  signal timer_us_tick_out_i       : std_logic;
+  signal stat_debug_1_i            : std_logic_vector(31 downto 0);
+  signal stat_debug_2_i            : std_logic_vector(31 downto 0);
+  signal regio_idram_data_in_i     : std_logic_vector(15 downto 0) := (others => '0');
+  signal regio_idram_data_out_i    : std_logic_vector(15 downto 0);
+  signal regio_idram_addr_in_i     : std_logic_vector(2 downto 0)  := "000";
+  signal regio_idram_wr_in_i       : std_logic                     := '0';
+  signal stat_debug_ipu_i          : std_logic_vector (31 downto 0);
+  signal ipu_read_out_i            : std_logic                     := '0';
+  signal ipu_dataready_in_i        : std_logic;
+  signal lvl2_trigger_i_pulse      : std_logic;
+  signal cntr_for_dummy_header     : std_logic_vector(1 downto 0)  := "00";
+  signal ipu_data_in_i             : std_logic_vector(31 downto 0);
   --vulom
   signal vulom_event               : std_logic_vector(31 downto 0);
   signal vulom_event_valid         : std_logic;
@@ -1234,8 +1243,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal vulom_lvl1_trigger_i      : std_logic;
   signal vulom_lvl1_trigger_code_i : std_logic_vector(3 downto 0);
   signal vulom_lvl1_trigger_tag_i  : std_logic_vector(15 downto 0);
-  signal ext_lvl1_trigger_i        : std_logic                    := '0';
-  signal ext_tag                   : std_logic_vector(7 downto 0) := x"00";
+  signal ext_lvl1_trigger_i        : std_logic                     := '0';
+  signal ext_tag                   : std_logic_vector(7 downto 0)  := x"00";
   signal ext_lvl1_trigger_pulse    : std_logic;
   signal lvl1_vulom_trigger        : std_logic;
 
@@ -1247,29 +1256,29 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal opt_busy_lvl1_or_lvl2 : std_logic;
   signal lvl2_opt_busy_pulse   : std_logic;
   signal not_lvl2_opt_busy     : std_logic;
-  
+
   --spi  
   --a
   signal spi_sck_a : std_logic;
   signal spi_cs_a  : std_logic;
   signal spi_sdi_a : std_logic;
-  signal spi_sdo_a : std_logic;  
+  signal spi_sdo_a : std_logic;
   --b
   signal spi_sck_b : std_logic;
   signal spi_cs_b  : std_logic;
   signal spi_sdi_b : std_logic;
-  signal spi_sdo_b : std_logic;  
+  signal spi_sdo_b : std_logic;
   --c
   signal spi_sck_c : std_logic;
   signal spi_cs_c  : std_logic;
   signal spi_sdi_c : std_logic;
-  signal spi_sdo_c : std_logic;  
+  signal spi_sdo_c : std_logic;
   --d
   signal spi_sck_d : std_logic;
   signal spi_cs_d  : std_logic;
   signal spi_sdi_d : std_logic;
   signal spi_sdo_d : std_logic;
-  
+
   --test signals  
   signal test_a1                 : std_logic;
   signal test_a2                 : std_logic;
@@ -1285,44 +1294,44 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal ref_time_counter        : std_logic_vector(7 downto 0);
 
 
-  signal lvl1_cts_busy_out_i : std_logic;
-  signal lvl2_cts_busy_out_i : std_logic;
+  signal lvl1_cts_busy_out_i   : std_logic;
+  signal lvl2_cts_busy_out_i   : std_logic;
   signal lvl1_rnd_number_out_i : std_logic_vector(7 downto 0);
   signal lvl2_rnd_number_out_i : std_logic_vector(7 downto 0);
 begin
 
-  
+
   ----------------------------------------------------------------------------
   -- Global reset
   ----------------------------------------------------------------------------
-  MAKE_START_RESET: process (CLK)
+  MAKE_START_RESET : process (CLK)
   begin
     if rising_edge(CLK) then
       if global_reset_counter < x"e" then
         global_reset_counter <= global_reset_counter + 1;
-        reset_i <= '1';
+        reset_i              <= '1';
       else
-        global_reset_counter <= global_reset_counter ;
-        reset_i <= '0';
+        global_reset_counter <= global_reset_counter;
+        reset_i              <= '0';
       end if;
     end if;
   end process MAKE_START_RESET;
 
-     -- add reseet from etrax and from trbnet( . . .)
+  -- add reseet from etrax and from trbnet( . . .)
 
   ----------------------------------------------------------------------------
   -- LVDS signals
   ----------------------------------------------------------------------------
-  
+
   -- CLK ----------------------------------------------------------------------
-   IBUFGDS_CLK : IBUFDS                 
-     generic map (
-       DIFF_TERM => TRUE)
-     port map (
-       O => CLK,
-       I => VIRT_CLK,  
-       IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port)
-     );
+  IBUFGDS_CLK : IBUFDS
+    generic map (
+      DIFF_TERM => true)
+    port map (
+      O  => CLK,
+      I  => VIRT_CLK,
+      IB => VIRT_CLKB  -- Diff_n clock buffer input (connect to top-level port)
+      );
 --  here !!!!
 --   DCM_INST: DCM_100MHz_to_200MHz
 -- --     generic map (
@@ -1336,145 +1345,145 @@ begin
 --         CLK0_OUT        => clk,
 --         CLK2X_OUT       => clk200,
 --         LOCKED_OUT      => locked_out);
-  
+
   -- AddOn clk ----------------------------------------------------------------
-  IBUFGDS_ADDCLK : IBUFDS                 
+  IBUFGDS_ADDCLK : IBUFDS
     generic map (
       IOSTANDARD => "LVDS_25_DCI")
     port map (
-      O => addon_clk,--CLK,
-      I => ADDON_TO_TRB_CLKINP,  
-      IB => ADDON_TO_TRB_CLKINN -- Diff_n clock buffer input (connect to top-level port)
+      O  => addon_clk,                  --CLK,
+      I  => ADDON_TO_TRB_CLKINP,
+      IB => ADDON_TO_TRB_CLKINN  -- Diff_n clock buffer input (connect to top-level port)
       );
-  
+
   -- TDC ----------------------------------------------------------------------
-  IBUFGDS_TDC_CLK : IBUFGDS                 
+  IBUFGDS_TDC_CLK : IBUFGDS
     generic map (
-      IOSTANDARD => "LVDS_25_DCI")                              --_DCI
+      IOSTANDARD => "LVDS_25_DCI")      --_DCI
     port map (
-      O => tdc_clk,
-      I => REF_TDC_CLK,  
-      IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port)
-    );
-  IBUFDS_TRIGG_A : OBUFDS  port map (O => A_TRIGGER, OB => A_TRIGGERB, I => a_trigg);
-  IBUFDS_TRIGG_B : OBUFDS  port map (O => B_TRIGGER, OB => B_TRIGGERB, I => b_trigg);
-  IBUFDS_TRIGG_C : OBUFDS  port map (O => C_TRIGGER, OB => C_TRIGGERB, I => c_trigg);
-  IBUFDS_TRIGG_D : OBUFDS  port map (O => D_TRIGGER, OB => D_TRIGGERB, I => d_trigg);
+      O  => tdc_clk,
+      I  => REF_TDC_CLK,
+      IB => REF_TDC_CLKB  -- Diff_n clock buffer input (connect to top-level port)
+      );
+  IBUFDS_TRIGG_A       : OBUFDS port map (O             => A_TRIGGER, OB => A_TRIGGERB, I => a_trigg);
+  IBUFDS_TRIGG_B       : OBUFDS port map (O             => B_TRIGGER, OB => B_TRIGGERB, I => b_trigg);
+  IBUFDS_TRIGG_C       : OBUFDS port map (O             => C_TRIGGER, OB => C_TRIGGERB, I => c_trigg);
+  IBUFDS_TRIGG_D       : OBUFDS port map (O             => D_TRIGGER, OB => D_TRIGGERB, I => d_trigg);
   OBUFDS_BUNCH_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => A_TDC_BU_RESET, OB =>A_TDC_BU_RESETB , I => bunch_reset_i);
+    port map (O => A_TDC_BU_RESET, OB => A_TDC_BU_RESETB , I => bunch_reset_i);
   OBUFDS_EVENT_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => A_TDC_EV_RESET, OB =>A_TDC_EV_RESETB , I => event_reset_i);
+    port map (O => A_TDC_EV_RESET, OB => A_TDC_EV_RESETB , I => event_reset_i);
   OBUFDS_BUNCH_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => B_TDC_BU_RESET, OB =>B_TDC_BU_RESETB, I => bunch_reset_i);
+    port map (O => B_TDC_BU_RESET, OB => B_TDC_BU_RESETB, I => bunch_reset_i);
   OBUFDS_EVENT_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => B_TDC_EV_RESET, OB =>B_TDC_EV_RESETB, I => event_reset_i);
+    port map (O => B_TDC_EV_RESET, OB => B_TDC_EV_RESETB, I => event_reset_i);
   OBUFDS_BUNCH_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => C_TDC_BU_RESET, OB =>C_TDC_BU_RESETB, I => bunch_reset_i);
+    port map (O => C_TDC_BU_RESET, OB => C_TDC_BU_RESETB, I => bunch_reset_i);
   OBUFDS_EVENT_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => C_TDC_EV_RESET, OB =>C_TDC_EV_RESETB, I => event_reset_i);
+    port map (O => C_TDC_EV_RESET, OB => C_TDC_EV_RESETB, I => event_reset_i);
   OBUFDS_BUNCH_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => D_TDC_BU_RESET, OB =>D_TDC_BU_RESETB, I => bunch_reset_i);
+    port map (O => D_TDC_BU_RESET, OB => D_TDC_BU_RESETB, I => bunch_reset_i);
   OBUFDS_EVENT_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => D_TDC_EV_RESET, OB =>D_TDC_EV_RESETB, I => event_reset_i);
-  
+    port map (O => D_TDC_EV_RESET, OB => D_TDC_EV_RESETB, I => event_reset_i);
+
   --fast trigg-----------------------------------------------------------------
-  IBUFDS_FAST_TRIGGER : IBUFDS generic map (DIFF_TERM => TRUE)
+  IBUFDS_FAST_TRIGGER : IBUFDS generic map (DIFF_TERM => true)
     port map (I => VIR_TRIG, IB => VIR_TRIGB, O => fast_ref_trigger);
-  
+
   -- SPI ----------------------------------------------------------------------
-  
-    --A
+
+  --A
   OBUFDS_SCK_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => A_SCK, OB => A_SCKB, I => spi_sck_a);
+    port map (O => A_SCK, OB => A_SCKB, I => spi_sck_a);
   OBUFDS_SDO_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => A_SDO, OB => A_SDOB, I => spi_sdo_a);
+    port map (O => A_SDO, OB => A_SDOB, I => spi_sdo_a);
   OBUFDS_CS_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => A_CS, OB => A_CSB, I => spi_cs_a);
+    port map (O => A_CS, OB => A_CSB, I => spi_cs_a);
   IBUFDS_SDI_A : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
     port map (I => A_SDI, IB => A_SDIB, O => spi_sdi_a);
-  spi_sck_a <= fpga_register_07_i(0);
-  spi_sdo_a <= fpga_register_07_i(1);
-  spi_cs_a <= fpga_register_07_i(2);
+  spi_sck_a             <= fpga_register_07_i(0);
+  spi_sdo_a             <= fpga_register_07_i(1);
+  spi_cs_a              <= fpga_register_07_i(2);
   fpga_register_08_i(0) <= spi_sdi_a;
-  
-    --B
+
+  --B
   OBUFDS_SCK_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => B_SCK, OB => B_SCKB, I => spi_sck_b);
-  OBUFDS_SDO_B : OBUFDS  generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => B_SDO, OB => B_SDOB, I => spi_sdo_b);
+    port map (O => B_SCK, OB => B_SCKB, I => spi_sck_b);
+  OBUFDS_SDO_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => B_SDO, OB => B_SDOB, I => spi_sdo_b);
   OBUFDS_CS_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => B_CS, OB => B_CSB, I => spi_cs_b);
+    port map (O => B_CS, OB => B_CSB, I => spi_cs_b);
   IBUFDS_SDI_B : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map ( I => B_SDI, IB => B_SDIB, O => spi_sdi_b);
-  spi_sck_b <= fpga_register_07_i(3);
-  spi_sdo_b <= fpga_register_07_i(4);
-  spi_cs_b <= fpga_register_07_i(5);
+    port map (I => B_SDI, IB => B_SDIB, O => spi_sdi_b);
+  spi_sck_b             <= fpga_register_07_i(3);
+  spi_sdo_b             <= fpga_register_07_i(4);
+  spi_cs_b              <= fpga_register_07_i(5);
   fpga_register_08_i(1) <= spi_sdi_b;
-  
-    --C
+
+  --C
   OBUFDS_SCK_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => C_SCK,   OB => C_SCKB,  I => spi_sck_c);
+    port map (O => C_SCK, OB => C_SCKB, I => spi_sck_c);
   OBUFDS_SDO_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => C_SDO,   OB => C_SDOB,  I => spi_sdo_c);
+    port map (O => C_SDO, OB => C_SDOB, I => spi_sdo_c);
   OBUFDS_CS_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map ( O => C_CS, OB => C_CSB, I => spi_cs_c);
+    port map (O => C_CS, OB => C_CSB, I => spi_cs_c);
   IBUFDS_SDI_C : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map ( I => C_SDI, IB => C_SDIB, O => spi_sdi_c);
-  spi_sck_c <= fpga_register_07_i(6);
-  spi_sdo_c <= fpga_register_07_i(7);
-  spi_cs_c <= fpga_register_07_i(8);
+    port map (I => C_SDI, IB => C_SDIB, O => spi_sdi_c);
+  spi_sck_c             <= fpga_register_07_i(6);
+  spi_sdo_c             <= fpga_register_07_i(7);
+  spi_cs_c              <= fpga_register_07_i(8);
   fpga_register_08_i(2) <= spi_sdi_c;
-  
-    --D
-  OBUFDS_SCK_D : OBUFDS generic map (IOSTANDARD  => "LVDS_25")
-    port map ( O => D_SCK, OB => D_SCKB, I => spi_sck_d);
-  OBUFDS_SDO_D : OBUFDS generic map (IOSTANDARD  => "LVDS_25")
-    port map ( O => D_SDO, OB => D_SDOB, I => spi_sdo_d );
-  OBUFDS_CS_D  : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => D_CS, OB => D_CSB, I => spi_cs_d );
-  IBUFDS_SDI_D : IBUFDS generic map ( IOSTANDARD => "LVDS_25_DCI" )
-    port map (I => D_SDI, IB => D_SDIB, O => spi_sdi_d );
-  spi_sck_d <= fpga_register_07_i(9);
-  spi_sdo_d <= fpga_register_07_i(10);
-  spi_cs_d <= fpga_register_07_i(11);
+
+  --D
+  OBUFDS_SCK_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => D_SCK, OB => D_SCKB, I => spi_sck_d);
+  OBUFDS_SDO_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => D_SDO, OB => D_SDOB, I => spi_sdo_d);
+  OBUFDS_CS_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => D_CS, OB => D_CSB, I => spi_cs_d);
+  IBUFDS_SDI_D : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
+    port map (I => D_SDI, IB => D_SDIB, O => spi_sdi_d);
+  spi_sck_d             <= fpga_register_07_i(9);
+  spi_sdo_d             <= fpga_register_07_i(10);
+  spi_cs_d              <= fpga_register_07_i(11);
   fpga_register_08_i(3) <= spi_sdi_d;
 
-  
+
   -----------------------------------------------------------------------------
   -- Test signals
   -----------------------------------------------------------------------------
-  OBUFDS_TEST_A1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => A_TEST1, OB => A_TEST1B, I => test_a1 );
-  OBUFDS_TEST_A2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => A_TEST2, OB => A_TEST2B, I => test_a2 );
-  OBUFDS_TEST_B1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => B_TEST1, OB => B_TEST1B, I => test_b1 );
-  OBUFDS_TEST_B2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => B_TEST2, OB => B_TEST2B, I => test_b2 );
-  OBUFDS_TEST_C1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => C_TEST1, OB => C_TEST1B, I => test_c1 );
-  OBUFDS_TEST_C2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => C_TEST2, OB => C_TEST2B, I => test_c2 );
-  OBUFDS_TEST_D1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => D_TEST1, OB => D_TEST1B, I => test_d1 );
-  OBUFDS_TEST_D2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" )
-    port map ( O => D_TEST2, OB => D_TEST2B, I => test_d2 );
-     --i should be able to switch on off 1 or 2
-  COUNTER_FOR_TEST_1: process (CLK, reset_i,test_counter_1)
-  begin 
+  OBUFDS_TEST_A1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => A_TEST1, OB => A_TEST1B, I => test_a1);
+  OBUFDS_TEST_A2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => A_TEST2, OB => A_TEST2B, I => test_a2);
+  OBUFDS_TEST_B1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => B_TEST1, OB => B_TEST1B, I => test_b1);
+  OBUFDS_TEST_B2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => B_TEST2, OB => B_TEST2B, I => test_b2);
+  OBUFDS_TEST_C1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => C_TEST1, OB => C_TEST1B, I => test_c1);
+  OBUFDS_TEST_C2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => C_TEST2, OB => C_TEST2B, I => test_c2);
+  OBUFDS_TEST_D1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => D_TEST1, OB => D_TEST1B, I => test_d1);
+  OBUFDS_TEST_D2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
+    port map (O => D_TEST2, OB => D_TEST2B, I => test_d2);
+  --i should be able to switch on off 1 or 2
+  COUNTER_FOR_TEST_1 : process (CLK, reset_i, test_counter_1)
+  begin
     if rising_edge(CLK) then
-      if reset_i = '1' or test_counter_1 > x"F4240"then  --0.1kHz
+      if reset_i = '1' or test_counter_1 > x"F4240"then   --0.1kHz
 --      if reset_i = '1' or test_counter_1 = x"00140"then  --for sim
-        test_counter_1 <= (others => '0'); 
+        test_counter_1 <= (others => '0');
       else
         test_counter_1 <= test_counter_1 + 1;
       end if;
     end if;
   end process COUNTER_FOR_TEST_1;
-  COUNTER_FOR_TEST_2: process (CLK, reset_i,test_counter_2)  
-  begin 
+  COUNTER_FOR_TEST_2 : process (CLK, reset_i, test_counter_2)
+  begin
     if rising_edge(CLK) then
-      if reset_i = '1' or test_counter_2 = x"F4240" then --0.1kHz
+      if reset_i = '1' or test_counter_2 = x"F4240" then  --0.1kHz
         test_counter_2 <= (others => '0');
       else
         test_counter_2 <= test_counter_2 + 1;
@@ -1483,89 +1492,89 @@ begin
   end process COUNTER_FOR_TEST_2;
   --lenght of signal depend on this condition: test_counter_1 < x". ."
   --frequency in process:. . or test_counter_x > x". ."
-  test_a1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(0)='1')  else '1'; 
-  test_b1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(2)='1')  else '1';
-  test_c1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(4)='1')  else '1';
-  test_d1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(6)='1')  else '1';
-  test_a2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(1)='1')  else '1';
-  test_b2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(3)='1')  else '1';
-  test_c2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(5)='1')  else '1';
-  test_d2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(7)='1')  else '1';
-
-  trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1)='1' or fpga_register_06_i(2) ='1' )) else '0';
+  test_a1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(0) = '1') else '1';
+  test_b1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(2) = '1') else '1';
+  test_c1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(4) = '1') else '1';
+  test_d1 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(6) = '1') else '1';
+  test_a2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(1) = '1') else '1';
+  test_b2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(3) = '1') else '1';
+  test_c2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(5) = '1') else '1';
+  test_d2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(7) = '1') else '1';
+
+  trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1) = '1' or fpga_register_06_i(2) = '1')) else '0';
 -------------------------------------------------------------------------------
 -- rpc temperature
 -------------------------------------------------------------------------------
-  GENERAT_ONE_WIRE_CONNECTION: for i in 0 to 3 generate
+  GENERAT_ONE_WIRE_CONNECTION : for i in 0 to 3 generate
 
     onewire_interface : trb_net_onewire
-    generic map(
-      USE_TEMPERATURE_READOUT => 1,
-      CLK_PERIOD => 10
-      )
-    port map(
-      CLK      => CLK,
-      RESET    => reset_i,
-      --connection to 1-wire interface
-      ONEWIRE  => TEMP_SENS(i),
-      --connection to id ram, according to memory map in TrbNetRegIO
-      DATA_OUT => open,
-      ADDR_OUT => open,
-      WRITE_OUT=> open,
-      TEMP_OUT => temp_sens_i(i),
-      STAT     => temp_sens_status_i(i)
-      );
-    
+      generic map(
+        USE_TEMPERATURE_READOUT => 1,
+        CLK_PERIOD              => 10
+        )
+      port map(
+        CLK       => CLK,
+        RESET     => reset_i,
+        --connection to 1-wire interface
+        ONEWIRE   => TEMP_SENS(i),
+        --connection to id ram, according to memory map in TrbNetRegIO
+        DATA_OUT  => open,
+        ADDR_OUT  => open,
+        WRITE_OUT => open,
+        TEMP_OUT  => temp_sens_i(i),
+        STAT      => temp_sens_status_i(i)
+        );
+
   end generate GENERAT_ONE_WIRE_CONNECTION;
-  r_register_i(15)(11 downto 0)    <= temp_sens_i(0);
+  r_register_i(15)(11 downto 0)  <= temp_sens_i(0);
   r_register_i(15)(23 downto 12) <= temp_sens_i(1);
-  r_register_i(16)(11 downto 0)    <= temp_sens_i(2);
+  r_register_i(16)(11 downto 0)  <= temp_sens_i(2);
   r_register_i(16)(23 downto 12) <= temp_sens_i(3);
-  
+
 -- ADD_LVDS IN------------------------------------------------------------------
-  
-    ADO_LVDS_IN_PROC: for line in 0 to 25 generate  --62 lines in total
-      IBUFDS_LVDS : IBUFDS
-        generic map (
-          DIFF_TERM => TRUE
-          )
-        port map (
-          I => ADO_LVDS_IN(line*2),
-          IB => ADO_LVDS_IN(line*2+1),  
-          O => lvds_add_on_data(line)
-          );
-    end generate ADO_LVDS_IN_PROC;
-  
+
+  ADO_LVDS_IN_PROC : for line in 0 to 25 generate  --62 lines in total
+    IBUFDS_LVDS : IBUFDS
+      generic map (
+        DIFF_TERM => true
+        )
+      port map (
+        I  => ADO_LVDS_IN(line*2),
+        IB => ADO_LVDS_IN(line*2+1),
+        O  => lvds_add_on_data(line)
+        );
+  end generate ADO_LVDS_IN_PROC;
+
 -- ADD_LVDS OUT------------------------------------------------------------------
-  
-  ADO_LVDS_OUT_PROC: for line in 0 to 4 generate
+
+  ADO_LVDS_OUT_PROC : for line in 0 to 4 generate
     OBUFDS_LVDS_LINE : OBUFDS
       generic map (
         IOSTANDARD => "LVDS_25"
         )
       port map (
-        O =>  ADO_LVDS_OUT(line*2),
+        O  => ADO_LVDS_OUT(line*2),
         OB => ADO_LVDS_OUT(line*2+1),
-        I => ado_lv_out_i(line)
+        I  => ado_lv_out_i(line)
         );
   end generate ADO_LVDS_OUT_PROC;
-      
-  
+
+
 -------------------------------------------------------------------------------
 -- tiger sharc dma
 -------------------------------------------------------------------------------
- 
-    
+
+
 -------------------------------------------------------------------------------
 -- TRBnet - cts
 -------------------------------------------------------------------------------
 
-  TRBnet_CTS: if TRBNET_ENABLE=2 generate
+  TRBnet_CTS : if TRBNET_ENABLE = 2 generate
     
     
     THE_TRBNET_CTS : trb_net16_endpoint_hades_cts
       generic map (
-        USE_CHANNEL               =>  (c_YES, c_YES, c_NO, c_YES),
+        USE_CHANNEL               => (c_YES, c_YES, c_NO, c_YES),
         IBUF_DEPTH                => (6, 6, 6, 6),
         FIFO_TO_INT_DEPTH         => (1, 1, 6, 6),
         FIFO_TO_APL_DEPTH         => (1, 6, 6, 6),
@@ -1583,7 +1592,7 @@ begin
         REGIO_USED_CTRL_REGS      => "00000001",
         --set to 0 for each unuse
         REGIO_USED_CTRL_BITMASK   => (others => '1'),
-        REGIO_USE_DAT_PORT        => c_YES,  --internal data port
+        REGIO_USE_DAT_PORT        => c_YES,            --internal data port
         REGIO_INIT_ADDRESS        => x"FFFF",
         REGIO_INIT_UNIQUE_ID      => x"0000_0000_0000_0000",
         REGIO_INIT_BOARD_INFO     => x"0000_0000",
@@ -1591,114 +1600,115 @@ begin
         REGIO_COMPILE_TIME        => x"00000000",
         REGIO_COMPILE_VERSION     => x"0001",
         REGIO_HARDWARE_VERSION    => x"00000000",
-        REGIO_USE_1WIRE_INTERFACE => c_YES,  --c_YES,c_NO,c_MONITOR
+        REGIO_USE_1WIRE_INTERFACE => c_YES,            --c_YES,c_NO,c_MONITOR
         CLOCK_FREQUENCY           => 100
         )
-        port map (
-          CLK                       => CLK,
-          RESET                     => reset_i,
-          CLK_EN                    => '1',
-          MED_DATAREADY_OUT         => med_dataready_in_i(0),
-          MED_DATA_OUT              => med_data_in_i,
-          MED_PACKET_NUM_OUT        => med_packet_num_in_i,
-          MED_READ_IN               => '1',--med_read_out_i(0),
-          MED_DATAREADY_IN          => med_dataready_out_i(0),
-          MED_DATA_IN               => med_data_out_i,
-          MED_PACKET_NUM_IN         => med_packet_num_out_i,
-          MED_READ_OUT              => med_read_in_i(0),
-          MED_STAT_OP_IN            => med_stat_op_in_i,
-          MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
-          TRG_SEND_IN               => lvl1_trigger_i,
-          TRG_TYPE_IN               => lvl1_trigger_code_i,
-          TRG_NUMBER_IN             => lvl1_trigger_tag_i,
-          TRG_INFORMATION_IN        => x"00",
-          TRG_RND_CODE_IN           => lvl1_rnd_number_out_i,
-          TRG_STATUS_BITS_OUT       => trg_status_bits_out_i,
-          TRG_BUSY_OUT              => trg_busy_out_i,
-          IPU_SEND_IN               => lvl2_trigger_i,
-          IPU_TYPE_IN               => lvl2_trigger_code_i,
-          IPU_NUMBER_IN             => lvl2_trigger_tag_i,
-          IPU_INFORMATION_IN        => x"00",
-          IPU_RND_CODE_IN           => lvl2_rnd_number_out_i,
-          IPU_DATA_OUT              => ipu_data_out_i,
-          IPU_DATAREADY_OUT         => ipu_dataready_out_i,
-          IPU_READ_IN               => '1',--ipu_read_in_i,
-          IPU_STATUS_BITS_OUT       => ipu_status_bits_out_i,
-          IPU_BUSY_OUT              => ipu_busy_out_i,
-          REGIO_COMMON_STAT_REG_IN  => (others => '0'),--regio_common_stat_reg_in_i,
-          REGIO_COMMON_CTRL_REG_OUT => open,--regio_common_ctrl_reg_out_i,
-          REGIO_REGISTERS_IN        => regio_registers_in_i,
-          REGIO_REGISTERS_OUT       => regio_registers_out_i,
-          REGIO_ADDR_OUT            => regio_addr_out_i,
-          REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
-          REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
-          REGIO_DATA_OUT            => regio_data_out_i,
-          REGIO_DATA_IN             => regio_data_in_i,
-          REGIO_DATAREADY_IN        => regio_dataready_in_i,
-          REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
-          REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
-          REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
-          REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
-          REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
-          REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
-          REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
-          TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
-          GLOBAL_TIME_OUT           => global_time_out_i,
-          LOCAL_TIME_OUT            => local_time_out_i,
-          TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
-          TIMER_US_TICK_OUT         => open,
-          STAT_DEBUG_1              => stat_debug_1_i,
-          STAT_DEBUG_2              => stat_debug_2_i);
+      port map (
+        CLK                       => CLK,
+        RESET                     => reset_i,
+        CLK_EN                    => '1',
+        MED_DATAREADY_OUT         => med_dataready_in_i(0),
+        MED_DATA_OUT              => med_data_in_i,
+        MED_PACKET_NUM_OUT        => med_packet_num_in_i,
+        MED_READ_IN               => '1',   --med_read_out_i(0),
+        MED_DATAREADY_IN          => med_dataready_out_i(0),
+        MED_DATA_IN               => med_data_out_i,
+        MED_PACKET_NUM_IN         => med_packet_num_out_i,
+        MED_READ_OUT              => med_read_in_i(0),
+        MED_STAT_OP_IN            => med_stat_op_in_i,
+        MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
+        TRG_SEND_IN               => lvl1_trigger_i,
+        TRG_TYPE_IN               => lvl1_trigger_code_i,
+        TRG_NUMBER_IN             => lvl1_trigger_tag_i,
+        TRG_INFORMATION_IN        => x"00",
+        TRG_RND_CODE_IN           => lvl1_rnd_number_out_i,
+        TRG_STATUS_BITS_OUT       => trg_status_bits_out_i,
+        TRG_BUSY_OUT              => trg_busy_out_i,
+        IPU_SEND_IN               => lvl2_trigger_i,
+        IPU_TYPE_IN               => lvl2_trigger_code_i,
+        IPU_NUMBER_IN             => lvl2_trigger_tag_i,
+        IPU_INFORMATION_IN        => x"00",
+        IPU_RND_CODE_IN           => lvl2_rnd_number_out_i,
+        IPU_DATA_OUT              => ipu_data_out_i,
+        IPU_DATAREADY_OUT         => ipu_dataready_out_i,
+        IPU_READ_IN               => '1',   --ipu_read_in_i,
+        IPU_STATUS_BITS_OUT       => ipu_status_bits_out_i,
+        IPU_BUSY_OUT              => ipu_busy_out_i,
+        REGIO_COMMON_STAT_REG_IN  => (others => '0'),  --regio_common_stat_reg_in_i,
+        REGIO_COMMON_CTRL_REG_OUT => open,  --regio_common_ctrl_reg_out_i,
+        REGIO_REGISTERS_IN        => regio_registers_in_i,
+        REGIO_REGISTERS_OUT       => regio_registers_out_i,
+        REGIO_ADDR_OUT            => regio_addr_out_i,
+        REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
+        REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
+        REGIO_DATA_OUT            => regio_data_out_i,
+        REGIO_DATA_IN             => regio_data_in_i,
+        REGIO_DATAREADY_IN        => regio_dataready_in_i,
+        REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
+        REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
+        REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
+        REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
+        REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
+        REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
+        REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
+        TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
+        GLOBAL_TIME_OUT           => global_time_out_i,
+        LOCAL_TIME_OUT            => local_time_out_i,
+        TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
+        TIMER_US_TICK_OUT         => open,
+        STAT_DEBUG_1              => stat_debug_1_i,
+        STAT_DEBUG_2              => stat_debug_2_i);
   end generate TRBnet_CTS;
 
 -------------------------------------------------------------------------------
 -- Vulom interafce
 -------------------------------------------------------------------------------
-  
-  VULOM_EN: if TRBV2_TYPE = 4 generate
-    vulom_busy <= lvl1_busy_i or opt_lvl1_busy_i ;
-     VULOM_INT : vulom_interface
-       generic map (
-         TRBNET_ENABLE => TRBNET_ENABLE
-         )
-       port map (
-         CLK                          => CLK,
-         clk200                       => clk200,
-         DATA_CLK                     => ADO_TTL(46),
-         RESET                        => reset_i,
-         DATA_IN                      => ADO_TTL(42 downto 41),  --lvds_add_on_data (3 downto 0),
-         BUSY                         => open,
-         ACK_TO_VULOM                 => ADO_TTL(34),
-         ERR_TO_VULOM                 => ADO_TTL(33),
-         API_DATA                     => open,
-         API_RUN_OUT                  => vulom_busy,--lvl1_busy_i,  --lvl1_cts_busy or lvl1_system_busy,  --apl_run_out_i,
-         API_SHORT_TRANSFER           => open,
-         API_DTYPE                    => open,
-         API_SEND                     => lvl1_vulom_trigger,
-         API_WRITE_IN                 => open,
-         API_TARGET_ADDRESS           => open,
-         API_SEQNR_OUT                => x"00",
-         VULOM_INT_REG                => fpga_register_09_i,--vulom_int_reg_00,
-         INTERFACE_CONTROL            => fpga_register_06_i(11 downto 8),
-         EVENT_OUT                    => vulom_event,
-         EVENT_VALID                  => vulom_event_valid,--counter_1_i,
-         EVENT_READOUT_START          => vulom_readout_start,
-         EVENT_READOUT_END            => vulom_readout_end,
-         START_READOUT                => vulom_lvl1_trigger_i,
-         LVL1_TRANSFER_BUSY           => lvl1_busy_i, --lvl1_cts_busy  --lvl1_cts_busy or lvl1_system_busy
-         LVL1_TRIGGER_CODE            => vulom_lvl1_trigger_code_i,
-         LVL1_TRIGGER_TAG             => vulom_lvl1_trigger_tag_i(7 downto 0) 
-         );
-     ADO_TTL(42 downto 40) <= (others => 'Z');
+
+  VULOM_EN : if TRBV2_TYPE = 4 generate
+    vulom_busy <= lvl1_busy_i or opt_lvl1_busy_i;
+    VULOM_INT : vulom_interface
+      generic map (
+        TRBNET_ENABLE => TRBNET_ENABLE
+        )
+      port map (
+        CLK                 => CLK,
+        clk200              => clk200,
+        DATA_CLK            => ADO_TTL(46),
+        RESET               => reset_i,
+        DATA_IN             => ADO_TTL(42 downto 41),  --lvds_add_on_data (3 downto 0),
+        BUSY                => open,
+        ACK_TO_VULOM        => ADO_TTL(34),
+        ERR_TO_VULOM        => ADO_TTL(33),
+        API_DATA            => open,
+        API_RUN_OUT         => vulom_busy,  --lvl1_busy_i,  --lvl1_cts_busy or lvl1_system_busy,  --apl_run_out_i,
+        API_SHORT_TRANSFER  => open,
+        API_DTYPE           => open,
+        API_SEND            => lvl1_vulom_trigger,
+        API_WRITE_IN        => open,
+        API_TARGET_ADDRESS  => open,
+        API_SEQNR_OUT       => x"00",
+        VULOM_INT_REG       => fpga_register_09_i,     --vulom_int_reg_00,
+        INTERFACE_CONTROL   => fpga_register_06_i(11 downto 8),
+        EVENT_OUT           => vulom_event,
+        EVENT_VALID         => vulom_event_valid,      --counter_1_i,
+        EVENT_READOUT_START => vulom_readout_start,
+        EVENT_READOUT_END   => vulom_readout_end,
+        START_READOUT       => vulom_lvl1_trigger_i,
+        LVL1_TRANSFER_BUSY  => lvl1_busy_i,  --lvl1_cts_busy  --lvl1_cts_busy or lvl1_system_busy
+        LVL1_TRIGGER_CODE   => vulom_lvl1_trigger_code_i,
+        LVL1_TRIGGER_TAG    => vulom_lvl1_trigger_tag_i(7 downto 0)
+        );
+    ADO_TTL(42 downto 40) <= (others => 'Z');
 --           ADO_TTL(34) <= '1';
     
   end generate VULOM_EN;
 
 
-  
+
 -------------------------------------------------------------------------------
 -- cts
--------------------------------------------------------------------------------  
+-------------------------------------------------------------------------------
+
   CTS_GENERATE : if TRBNET_ENABLE /= 1 generate
     THE_CTS : cts
       generic map (
@@ -1743,31 +1753,33 @@ begin
         CTS_CTRL_IN_0              => rw_register_i(5),
         CTS_CTRL_IN_1              => rw_register_i(6)
         );
-    
+
   end generate CTS_GENERATE;
 
   lvl2_local_busy_i <= lvl1_busy_i or lvl2_busy_i;
-    ado_lv_out_i(2) <= lvl1_cts_busy_out_i;
-    ado_lv_out_i(3) <= lvl2_cts_busy_out_i;
-    ado_lv_out_i(4) <= TDC_CLK;
-    ADO_TTL(0) <= lvl1_trigger_i;
-    ADO_TTL(1) <= lvl1_cts_busy_out_i;
-    ADO_TTL(2) <= trg_busy_out_i;
-    ADO_TTL(3) <= lvl1_trigger_tag_i(0);
-    ADO_TTL(4) <= lvl1_trigger_tag_i(1);
-    ADO_TTL(5) <= a_data_ready_i;
-    ADO_TTL(6) <= token_in_i;
-    ADO_TTL(7) <= lvl1_finished_i;
-    ADO_TTL(8) <= lvl2_trigger_i;
-    ADO_TTL(9) <= lvl2_cts_busy_out_i;
-    ADO_TTL(10) <= ipu_busy_out_i;
-    ADO_TTL(11) <= ipu_dataready_out_i;
-    ADO_TTL(12) <= FS_PB_17;
-    ADO_TTL(13) <= etrax_is_ready_to_read_i;
-    ADO_TTL(14) <= tdc_data_valid_i;
-    ADO_TTL(15) <= lvl2_finished_i;
-  
-  RATE_DIODS_EN: if TRBNET_ENABLE = 1 generate
+  ado_lv_out_i(2)   <= lvl1_cts_busy_out_i;
+  ado_lv_out_i(3)   <= lvl2_cts_busy_out_i;
+  ado_lv_out_i(4)   <= TDC_CLK;
+
+  ENABLE_DEBUG_CTS : if DEBUG_OPTION = 2 generate
+    ADO_TTL(0)           <= lvl1_trigger_i;
+    ADO_TTL(1)           <= lvl1_cts_busy_out_i;
+    ADO_TTL(2)           <= lvl2_local_busy_i;
+    ADO_TTL(3)           <= lvl1_finished_i;
+    ADO_TTL(4)           <= lvl2_trigger_i;
+    ADO_TTL(5)           <= lvl2_finished_i;
+    ADO_TTL(6)           <= ipu_read_in_i;
+    ADO_TTL(7)           <= ipu_dataready_out_i;
+    ADO_TTL(15 downto 8) <= ipu_data_out_i(31 downto 24);
+  end generate ENABLE_DEBUG_CTS;
+--    cts debug
+--  
+--    endpoint debug
+--    ADO_TTL(7) <= ipu_dataready_in_i;
+--    ADO_TTL(15 downto 0) <= ipu_dataready_in_i;
+
+
+  RATE_DIODS_EN : if TRBNET_ENABLE = 1 generate
     
     THE_CTS : cts
       generic map (
@@ -1785,8 +1797,8 @@ begin
         LVL1_VULOM_TRIGGER_IN      => '0',
         LVL1_VULOM_TRIGGER_CODE_IN => (others => '0'),
         LVL1_VULOM_TRIGGER_TAG_IN  => (others => '0'),
-        LVL1_VULOM_BUSY_IN         => '0',   
-        LVL1_LOCAL_BUSY            => dummy_lvl1_trigger,   
+        LVL1_VULOM_BUSY_IN         => '0',
+        LVL1_LOCAL_BUSY            => dummy_lvl1_trigger,
         LVL1_TRBNET_BUSY           => '0',
         LVL1_CTS_BUSY_OUT          => open,
         LVL1_TRIGGER_OUT           => open,
@@ -1812,120 +1824,131 @@ begin
         CTS_CTRL_IN_0              => x"00000400",
         CTS_CTRL_IN_1              => (others => '0')
         );
-    
+
   end generate RATE_DIODS_EN;
 
   TRBnet_END_POINT : if TRBNET_ENABLE = 1 generate
     
-    THE_TRBNET_END_POINT: trb_net16_endpoint_hades_full
+    THE_TRBNET_END_POINT : trb_net16_endpoint_hades_full
       generic map(
-        USE_CHANNEL                  => (c_YES,c_YES,c_NO,c_YES),
-        IBUF_DEPTH                   => (6,6,6,6),
-        FIFO_TO_INT_DEPTH            => (6,6,6,6),
-        FIFO_TO_APL_DEPTH            => (1,1,1,1),
-        IBUF_SECURE_MODE             => (c_YES,c_YES,c_YES,c_YES),
-        API_SECURE_MODE_TO_APL       => (c_YES,c_YES,c_YES,c_YES),
-        API_SECURE_MODE_TO_INT       => (c_YES,c_YES,c_YES,c_YES),
-        OBUF_DATA_COUNT_WIDTH        => std_DATA_COUNT_WIDTH,
-        INIT_CAN_SEND_DATA           => (c_NO,c_NO,c_NO,c_NO),
-        REPLY_CAN_SEND_DATA          => (c_YES,c_YES,c_YES,c_YES),
-        REPLY_CAN_RECEIVE_DATA       => (c_NO,c_NO,c_NO,c_NO),
-        USE_CHECKSUM                 => (c_NO,c_YES,c_YES,c_YES),
-        APL_WRITE_ALL_WORDS          => (c_NO,c_NO,c_NO,c_NO),
-        BROADCAST_BITMASK            => x"FF",
-        REGIO_NUM_STAT_REGS          => 3, --log2 of number of status registers
-        REGIO_NUM_CTRL_REGS          => 3, --log2 of number of ctrl registers
+        USE_CHANNEL               => (c_YES, c_YES, c_NO, c_YES),
+        IBUF_DEPTH                => (6, 6, 6, 6),
+        FIFO_TO_INT_DEPTH         => (6, 6, 6, 6),
+        FIFO_TO_APL_DEPTH         => (1, 1, 1, 1),
+        IBUF_SECURE_MODE          => (c_YES, c_YES, c_YES, c_YES),
+        API_SECURE_MODE_TO_APL    => (c_YES, c_YES, c_YES, c_YES),
+        API_SECURE_MODE_TO_INT    => (c_YES, c_YES, c_YES, c_YES),
+        OBUF_DATA_COUNT_WIDTH     => std_DATA_COUNT_WIDTH,
+        INIT_CAN_SEND_DATA        => (c_NO, c_NO, c_NO, c_NO),
+        REPLY_CAN_SEND_DATA       => (c_YES, c_YES, c_YES, c_YES),
+        REPLY_CAN_RECEIVE_DATA    => (c_NO, c_NO, c_NO, c_NO),
+        USE_CHECKSUM              => (c_NO, c_YES, c_YES, c_YES),
+        APL_WRITE_ALL_WORDS       => (c_NO, c_NO, c_NO, c_NO),
+        BROADCAST_BITMASK         => x"FF",
+        REGIO_NUM_STAT_REGS       => 3,  --log2 of number of status registers
+        REGIO_NUM_CTRL_REGS       => 3,  --log2 of number of ctrl registers
         --standard values for output registers
-        REGIO_INIT_CTRL_REGS         => (others => '0'),
+        REGIO_INIT_CTRL_REGS      => (others => '0'),
         --set to 0 for unused ctrl registers to save resources
-        REGIO_USED_CTRL_REGS         => "00000001",
+        REGIO_USED_CTRL_REGS      => "00000001",
         --set to 0 for each unused bit in a register
-        REGIO_USED_CTRL_BITMASK      => (others => '1'),
-        REGIO_USE_DAT_PORT           => c_YES,  --internal data port
-        REGIO_INIT_ADDRESS           => x"FFFF",
-        REGIO_INIT_UNIQUE_ID         => x"1000_2000_3654_4876",
-        REGIO_INIT_BOARD_INFO        => x"1111_2222",
-        REGIO_INIT_ENDPOINT_ID       => x"0001",
-        REGIO_COMPILE_TIME           => x"00000000",
-        REGIO_COMPILE_VERSION        => x"0001",
-        REGIO_HARDWARE_VERSION       => x"12345678",
-        REGIO_USE_1WIRE_INTERFACE    => c_YES, --c_YES,c_NO,c_MONITOR
-        CLOCK_FREQUENCY              => 100
+        REGIO_USED_CTRL_BITMASK   => (others => '1'),
+        REGIO_USE_DAT_PORT        => c_YES,  --internal data port
+        REGIO_INIT_ADDRESS        => x"FFFF",
+        REGIO_INIT_UNIQUE_ID      => x"1000_2000_3654_4876",
+        REGIO_INIT_BOARD_INFO     => x"1111_2222",
+        REGIO_INIT_ENDPOINT_ID    => x"0001",
+        REGIO_COMPILE_TIME        => x"00000000",
+        REGIO_COMPILE_VERSION     => x"0001",
+        REGIO_HARDWARE_VERSION    => x"12345678",
+        REGIO_USE_1WIRE_INTERFACE => c_YES,  --c_YES,c_NO,c_MONITOR
+        CLOCK_FREQUENCY           => 100
         )
-    port map (
-      CLK                       => CLK,
-      RESET                     => reset_i,
-      CLK_EN                    => '1',
-      MED_DATAREADY_OUT         => med_dataready_in_i(0),
-      MED_DATA_OUT              => med_data_in_i,
-      MED_PACKET_NUM_OUT        => med_packet_num_in_i,
-      MED_READ_IN               => '1',--med_read_out_i(0),
-      MED_DATAREADY_IN          => med_dataready_out_i(0),
-      MED_DATA_IN               => med_data_out_i,
-      MED_PACKET_NUM_IN         => med_packet_num_out_i,
-      MED_READ_OUT              => med_read_in_i(0),
-      MED_STAT_OP_IN            => med_stat_op_in_i,
-      MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
-      LVL1_TRG_TYPE_OUT         => lvl1_trigger_code_i,--open,
-      LVL1_TRG_RECEIVED_OUT     => lvl1_trigger_i,
-      LVL1_TRG_NUMBER_OUT       => lvl1_trigger_tag_i,
-      LVL1_TRG_CODE_OUT         => open,--lvl1_trigger_code_i,
-      LVL1_TRG_INFORMATION_OUT  => open,
-      LVL1_ERROR_PATTERN_IN     => (others => '0'),
-      LVL1_TRG_RELEASE_IN       => lvl1_finished_i,
-      IPU_NUMBER_OUT            => lvl2_trigger_tag_i,
-      IPU_INFORMATION_OUT       => open,
-      IPU_START_READOUT_OUT     => lvl2_trigger_i,
-      IPU_DATA_IN               => ipu_data_in_i,--(others => '0'),
-      IPU_DATAREADY_IN          => ipu_dataready_in_i,--tdc_data_valid_i,
-      IPU_READOUT_FINISHED_IN   => lvl2_finished_i,
-      IPU_READ_OUT              => ipu_read_out_i,
-      IPU_LENGTH_IN             => (others => '0'),
-      IPU_ERROR_PATTERN_IN      => (others => '0'),
-      REGIO_COMMON_STAT_REG_IN  => (others => '0'),
-      REGIO_COMMON_CTRL_REG_OUT => open,
-      REGIO_REGISTERS_IN        => (others => '0'),
-      REGIO_REGISTERS_OUT       => regio_registers_out_i,
-      REGIO_ADDR_OUT            => regio_addr_out_i,
-      REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
-      REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
-      REGIO_DATA_OUT            => regio_data_out_i,
-      REGIO_DATA_IN             => regio_data_in_i,
-      REGIO_DATAREADY_IN        => regio_dataready_in_i,
-      REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
-      REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
-      REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
-      REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
-      REGIO_IDRAM_DATA_IN       => regio_idram_data_in_i,
-      REGIO_IDRAM_DATA_OUT      => regio_idram_data_out_i,
-      REGIO_IDRAM_ADDR_IN       => regio_idram_addr_in_i,
-      REGIO_IDRAM_WR_IN         => regio_idram_wr_in_i,
-      REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
-      REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
-      REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
-      TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
-      GLOBAL_TIME_OUT           => global_time_out_i,
-      LOCAL_TIME_OUT            => local_time_out_i,
-      TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
-      TIMER_US_TICK_OUT         => timer_us_tick_out_i,
-      STAT_DEBUG_IPU            => stat_debug_ipu_i,
-      STAT_DEBUG_1              => stat_debug_1_i,
-      STAT_DEBUG_2              => stat_debug_2_i,
-      MED_STAT_OP               => open,
-      CTRL_MPLEX                => (others => '0'),
-      IOBUF_CTRL_GEN            => (others => '0'),
-      STAT_ONEWIRE              => open,
-      STAT_ADDR_DEBUG           => open);
-    
-    
+      port map (
+        CLK                       => CLK,
+        RESET                     => reset_i,
+        CLK_EN                    => '1',
+        MED_DATAREADY_OUT         => med_dataready_in_i(0),
+        MED_DATA_OUT              => med_data_in_i,
+        MED_PACKET_NUM_OUT        => med_packet_num_in_i,
+        MED_READ_IN               => '1',    --med_read_out_i(0),
+        MED_DATAREADY_IN          => med_dataready_out_i(0),
+        MED_DATA_IN               => med_data_out_i,
+        MED_PACKET_NUM_IN         => med_packet_num_out_i,
+        MED_READ_OUT              => med_read_in_i(0),
+        MED_STAT_OP_IN            => med_stat_op_in_i,
+        MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
+        LVL1_TRG_TYPE_OUT         => lvl1_trigger_code_i,  --open,
+        LVL1_TRG_RECEIVED_OUT     => lvl1_trigger_i,
+        LVL1_TRG_NUMBER_OUT       => lvl1_trigger_tag_i,
+        LVL1_TRG_CODE_OUT         => open,   --lvl1_trigger_code_i,
+        LVL1_TRG_INFORMATION_OUT  => open,
+        LVL1_ERROR_PATTERN_IN     => (others => '0'),
+        LVL1_TRG_RELEASE_IN       => lvl1_finished_i,
+        IPU_NUMBER_OUT            => lvl2_trigger_tag_i,
+        IPU_INFORMATION_OUT       => open,
+        IPU_START_READOUT_OUT     => lvl2_trigger_i,
+        IPU_DATA_IN               => ipu_data_in_i,        --(others => '0'),
+        IPU_DATAREADY_IN          => ipu_dataready_in_i,   --tdc_data_valid_i,
+        IPU_READOUT_FINISHED_IN   => lvl2_finished_i,
+        IPU_READ_OUT              => ipu_read_out_i,
+        IPU_LENGTH_IN             => (others => '0'),
+        IPU_ERROR_PATTERN_IN      => (others => '0'),
+        REGIO_COMMON_STAT_REG_IN  => (others => '0'),
+        REGIO_COMMON_CTRL_REG_OUT => open,
+        REGIO_REGISTERS_IN        => (others => '0'),
+        REGIO_REGISTERS_OUT       => regio_registers_out_i,
+        REGIO_ADDR_OUT            => regio_addr_out_i,
+        REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
+        REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
+        REGIO_DATA_OUT            => regio_data_out_i,
+        REGIO_DATA_IN             => regio_data_in_i,
+        REGIO_DATAREADY_IN        => regio_dataready_in_i,
+        REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
+        REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
+        REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
+        REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
+        REGIO_IDRAM_DATA_IN       => regio_idram_data_in_i,
+        REGIO_IDRAM_DATA_OUT      => regio_idram_data_out_i,
+        REGIO_IDRAM_ADDR_IN       => regio_idram_addr_in_i,
+        REGIO_IDRAM_WR_IN         => regio_idram_wr_in_i,
+        REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
+        REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
+        REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
+        TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
+        GLOBAL_TIME_OUT           => global_time_out_i,
+        LOCAL_TIME_OUT            => local_time_out_i,
+        TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
+        TIMER_US_TICK_OUT         => timer_us_tick_out_i,
+        STAT_DEBUG_IPU            => stat_debug_ipu_i,
+        STAT_DEBUG_1              => stat_debug_1_i,
+        STAT_DEBUG_2              => stat_debug_2_i,
+        MED_STAT_OP               => open,
+        CTRL_MPLEX                => (others => '0'),
+        IOBUF_CTRL_GEN            => (others => '0'),
+        STAT_ONEWIRE              => open,
+        STAT_ADDR_DEBUG           => open);
+
+    ENABLE_DEBUG_ENDPOINT : if DEBUG_OPTION = 1 generate
+      ADO_TTL(0)           <= lvl1_trigger_i;
+      ADO_TTL(1)           <= lvl1_cts_busy_out_i;
+      ADO_TTL(2)           <= trg_busy_out_i;
+      ADO_TTL(3)           <= lvl1_finished_i;
+      ADO_TTL(4)           <= lvl2_trigger_i;
+      ADO_TTL(5)           <= CLK;
+      ADO_TTL(6)           <= ipu_read_out_i;
+      ADO_TTL(7)           <= ipu_dataready_in_i;
+      ADO_TTL(15 downto 8) <= ipu_data_in_i(31 downto 24);
+    end generate ENABLE_DEBUG_ENDPOINT;
+
     EXT_LVL2_PULSER : edge_to_pulse
       port map (
-        clock  => CLK,
-        en_clk => '1',
+        clock     => CLK,
+        en_clk    => '1',
         signal_in => lvl2_trigger_i,
-        pulse  => lvl2_trigger_i_pulse);
-    
-    
+        pulse     => lvl2_trigger_i_pulse);
+
+
 --    MAKE_DUMMY_DATA_IN : process (CLK, reset_i)
 --    begin
 --      if rising_edge(CLK) then
@@ -1943,92 +1966,92 @@ begin
 --    end process MAKE_DUMMY_DATA_IN;
 ----    ipu_data_in_i <= x"0" & x"4" & x"83" & x"0000" when cntr_for_dummy_header < 2 else x"00000000";
     
-   end generate TRBnet_END_POINT;
+  end generate TRBnet_END_POINT;
 
 --   -----------------------------------------------------------------------------
 --   -- media to api, api to media
 --   -----------------------------------------------------------------------------
-    
-      TLK_RX_CLK_BUFR : BUFR
-        port map(
-          CE => '1',
-          CLR => '0',
-          I => TLK_RX_CLK,
-          O => tlk_rx_clk_r(0)
-          );
-    
-      TLK_CLK_BUFR: BUFR
-        port map(
-          CE => '1',
-          CLR => '0',
-          I => TLK_CLK,
-          O => tlk_clk_r(0)
-          );
-    
-      TLK_API_INT: trb_net16_med_tlk
-        port map (
-          RESET              => reset_i,
-          CLK                => CLK,
-          TLK_CLK            => tlk_clk_r(0),
-          TLK_ENABLE         => TLK_ENABLE,
-          TLK_LCKREFN        => TLK_LCKREFN,
-          TLK_LOOPEN         => TLK_LOOPEN,
-          TLK_PRBSEN         => TLK_PRBSEN,
-          TLK_RXD            => TLK_RXD,
-          TLK_RX_CLK         => tlk_rx_clk_r(0),
-          TLK_RX_DV          => TLK_RX_DV,
-          TLK_RX_ER          => TLK_RX_ER,
-          TLK_TXD            => TLK_TXD,
-          TLK_TX_EN          => TLK_TX_EN,
-          TLK_TX_ER          => TLK_TX_ER,
-          SFP_LOS            => SFP_LOS,
-          SFP_TX_DIS         => SFP_TX_DIS,
-          MED_DATAREADY_IN   => med_dataready_in_i(0),
-          MED_READ_IN        => med_read_in_i(0),
-          MED_DATA_IN        => med_data_in_i,
-          MED_PACKET_NUM_IN  => med_packet_num_in_i,
-          MED_DATAREADY_OUT  => med_dataready_out_i(0),
-          MED_READ_OUT       => med_read_out_i(0),
-          MED_DATA_OUT       => med_data_out_i,
-          MED_PACKET_NUM_OUT => med_packet_num_out_i,
-          STAT               => open,
-          STAT_MONITOR       => open,
-          STAT_OP            => med_stat_op_in_i,
-          CTRL_OP            => x"0000");
-    DGOOD <= not med_stat_op_in_i(9);
-  
+
+  TLK_RX_CLK_BUFR : BUFR
+    port map(
+      CE  => '1',
+      CLR => '0',
+      I   => TLK_RX_CLK,
+      O   => tlk_rx_clk_r(0)
+      );
+
+  TLK_CLK_BUFR : BUFR
+    port map(
+      CE  => '1',
+      CLR => '0',
+      I   => TLK_CLK,
+      O   => tlk_clk_r(0)
+      );
+
+  TLK_API_INT : trb_net16_med_tlk
+    port map (
+      RESET              => reset_i,
+      CLK                => CLK,
+      TLK_CLK            => tlk_clk_r(0),
+      TLK_ENABLE         => TLK_ENABLE,
+      TLK_LCKREFN        => TLK_LCKREFN,
+      TLK_LOOPEN         => TLK_LOOPEN,
+      TLK_PRBSEN         => TLK_PRBSEN,
+      TLK_RXD            => TLK_RXD,
+      TLK_RX_CLK         => tlk_rx_clk_r(0),
+      TLK_RX_DV          => TLK_RX_DV,
+      TLK_RX_ER          => TLK_RX_ER,
+      TLK_TXD            => TLK_TXD,
+      TLK_TX_EN          => TLK_TX_EN,
+      TLK_TX_ER          => TLK_TX_ER,
+      SFP_LOS            => SFP_LOS,
+      SFP_TX_DIS         => SFP_TX_DIS,
+      MED_DATAREADY_IN   => med_dataready_in_i(0),
+      MED_READ_IN        => med_read_in_i(0),
+      MED_DATA_IN        => med_data_in_i,
+      MED_PACKET_NUM_IN  => med_packet_num_in_i,
+      MED_DATAREADY_OUT  => med_dataready_out_i(0),
+      MED_READ_OUT       => med_read_out_i(0),
+      MED_DATA_OUT       => med_data_out_i,
+      MED_PACKET_NUM_OUT => med_packet_num_out_i,
+      STAT               => open,
+      STAT_MONITOR       => open,
+      STAT_OP            => med_stat_op_in_i,
+      CTRL_OP            => x"0000");
+  DGOOD <= not med_stat_op_in_i(9);
+
   DINT <= lvds_add_on_data(0) and
-                          lvds_add_on_data(1) and
-                          lvds_add_on_data(2) and
-                          lvds_add_on_data(3) and
-                          lvds_add_on_data(4) and
-                          lvds_add_on_data(5) and
-                          lvds_add_on_data(6) and
-                          lvds_add_on_data(7) and
-                          lvds_add_on_data(8) and
-                          lvds_add_on_data(9) and
-                          lvds_add_on_data(10) and
-                          lvds_add_on_data(11) and
-                          lvds_add_on_data(12) and
-                          lvds_add_on_data(13) and
-                          lvds_add_on_data(14) and
-                          lvds_add_on_data(15) and
-                          lvds_add_on_data(16) and
-                          lvds_add_on_data(17) and
-                          lvds_add_on_data(18) and
-                          lvds_add_on_data(19) and
-                          lvds_add_on_data(20) and
-                          lvds_add_on_data(21) and
-                          lvds_add_on_data(22) and
-                          lvds_add_on_data(23) and
-                          lvds_add_on_data(24) and
-                          lvds_add_on_data(25);
+          lvds_add_on_data(1) and
+          lvds_add_on_data(2) and
+          lvds_add_on_data(3) and
+          lvds_add_on_data(4) and
+          lvds_add_on_data(5) and
+          lvds_add_on_data(6) and
+          lvds_add_on_data(7) and
+          lvds_add_on_data(8) and
+          lvds_add_on_data(9) and
+          lvds_add_on_data(10) and
+          lvds_add_on_data(11) and
+          lvds_add_on_data(12) and
+          lvds_add_on_data(13) and
+          lvds_add_on_data(14) and
+          lvds_add_on_data(15) and
+          lvds_add_on_data(16) and
+          lvds_add_on_data(17) and
+          lvds_add_on_data(18) and
+          lvds_add_on_data(19) and
+          lvds_add_on_data(20) and
+          lvds_add_on_data(21) and
+          lvds_add_on_data(22) and
+          lvds_add_on_data(23) and
+          lvds_add_on_data(24) and
+          lvds_add_on_data(25);
 
 --------------------------------------------------------------------------- 
 -- tdc interface 
 ---------------------------------------------------------------------------
   --debug
-  
+
 --    ADO_TTL(0) <= not_hades_trigger;
 --    ADO_TTL(1) <= trigger_to_tdc_i;
 --    ADO_TTL(2) <= lvl1_busy_i;
@@ -2042,38 +2065,38 @@ begin
 --    ADO_TTL(10) <= bunch_reset_i;
 --    ADO_TTL(11) <= event_reset_i;
 --    ADO_TTL(12) <= TDC_CLK;
-   --end debug
-  VIRT_TRST <= not fpga_register_06_i(5);--'1';
-  TDC_RESET <= '0';--fpga_register_06_i(5);--'0';
+  --end debug
+  VIRT_TRST <= not fpga_register_06_i(5);  --'1';
+  TDC_RESET <= '0';  --fpga_register_06_i(5);--'0';
 
   --TDC TRB
-  TDC_INT_FOR_DIFF_PLATFORMSa: if TRBV2_TYPE = 0 generate
+  TDC_INT_FOR_DIFF_PLATFORMSa : if TRBV2_TYPE = 0 generate
     start_tdc_readout_i <= lvl1_trigger_i;
-    tdc_clk_i <= TDC_CLK;
-    tdc_data_in_i <= TDC_OUT;
-    a_data_ready_i <= A_DATA_READY;
-    b_data_ready_i <= B_DATA_READY;
-    c_data_ready_i <= C_DATA_READY;
-    d_data_ready_i <= D_DATA_READY;
-    token_in_i <= TOKEN_IN;
-    TOKEN_OUT <= token_out_i;
+    tdc_clk_i           <= TDC_CLK;
+    tdc_data_in_i       <= TDC_OUT;
+    a_data_ready_i      <= A_DATA_READY;
+    b_data_ready_i      <= B_DATA_READY;
+    c_data_ready_i      <= C_DATA_READY;
+    d_data_ready_i      <= D_DATA_READY;
+    token_in_i          <= TOKEN_IN;
+    TOKEN_OUT           <= token_out_i;
   end generate TDC_INT_FOR_DIFF_PLATFORMSa;
 
   --Shower or MDC
-  TDC_INT_FOR_DIFF_PLATFORMSb: if TRBV2_TYPE = 1 or TRBV2_TYPE = 2 generate
+  TDC_INT_FOR_DIFF_PLATFORMSb : if TRBV2_TYPE = 1 or TRBV2_TYPE = 2 generate
     start_tdc_readout_i <= lvl1_trigger_i;
-    tdc_clk_i <= addon_clk;
-    tdc_data_in_i <= ADO_TTL(38 downto 7);
-    a_data_ready_i <= ADO_TTL(3);
-    b_data_ready_i <= ADO_TTL(3);
-    c_data_ready_i <= ADO_TTL(3);
-    d_data_ready_i <= ADO_TTL(3);
-    token_in_i <= ADO_TTL(2);
-    ADO_TTL(1) <= token_out_long_b;          --longer token !?
-    TOKEN_OUT <= '0';
-    
-    MAKE_LONGER: process (CLK, reset_i)
-    begin 
+    tdc_clk_i           <= addon_clk;
+    tdc_data_in_i       <= ADO_TTL(38 downto 7);
+    a_data_ready_i      <= ADO_TTL(3);
+    b_data_ready_i      <= ADO_TTL(3);
+    c_data_ready_i      <= ADO_TTL(3);
+    d_data_ready_i      <= ADO_TTL(3);
+    token_in_i          <= ADO_TTL(2);
+    ADO_TTL(1)          <= token_out_long_b;  --longer token !?
+    TOKEN_OUT           <= '0';
+
+    MAKE_LONGER : process (CLK, reset_i)
+    begin
       if rising_edge(CLK) then
         if reset_i = '1' then
           token_out_long_a <= '0';
@@ -2088,47 +2111,47 @@ begin
   end generate TDC_INT_FOR_DIFF_PLATFORMSb;
 
   --CTS plus Vulom
-   TDC_INT_FOR_DIFF_PLATFORMSc: if TRBV2_TYPE = 4 generate
-     start_tdc_readout_i <= lvl1_trigger_i;
-     tdc_clk_i <= CLK;
-     tdc_data_in_i <= vulom_event;
-     a_data_ready_i <= vulom_event_valid;--start_readout_i;
-     b_data_ready_i <= vulom_event_valid;--start_readout_i;
-     c_data_ready_i <= vulom_event_valid;--start_readout_i;
-     d_data_ready_i <= vulom_event_valid;--start_readout_i;
-     token_in_i <= vulom_readout_end;
-     vulom_readout_start <= token_out_i;          --longer token !?
-     TOKEN_OUT <= '0';
-   end generate TDC_INT_FOR_DIFF_PLATFORMSc;
+  TDC_INT_FOR_DIFF_PLATFORMSc : if TRBV2_TYPE = 4 generate
+    start_tdc_readout_i <= lvl1_trigger_i;
+    tdc_clk_i           <= CLK;
+    tdc_data_in_i       <= vulom_event;
+    a_data_ready_i      <= vulom_event_valid;  --start_readout_i;
+    b_data_ready_i      <= vulom_event_valid;  --start_readout_i;
+    c_data_ready_i      <= vulom_event_valid;  --start_readout_i;
+    d_data_ready_i      <= vulom_event_valid;  --start_readout_i;
+    token_in_i          <= vulom_readout_end;
+    vulom_readout_start <= token_out_i;        --longer token !?
+    TOKEN_OUT           <= '0';
+  end generate TDC_INT_FOR_DIFF_PLATFORMSc;
 
   --Only CTS plus IPU readout
-  TDC_INT_FOR_DIFF_PLATFORMSd: if TRBV2_TYPE = 5 generate
-    start_tdc_readout_i <= lvl2_trigger_i;
-    not_ipu_dataready_out_i <=  not ipu_busy_out_i;
-    
+  TDC_INT_FOR_DIFF_PLATFORMSd : if TRBV2_TYPE = 5 generate
+    start_tdc_readout_i     <= lvl2_trigger_i;
+    not_ipu_dataready_out_i <= not ipu_busy_out_i;
+
     EXT_TRIGGER_1 : edge_to_pulse
       port map (
-        clock  => CLK,
-        en_clk => '1',
+        clock     => CLK,
+        en_clk    => '1',
         signal_in => not_ipu_dataready_out_i,
-        pulse  => ipu_dataready_out_end_pulse);
-    
-     tdc_clk_i <= CLK;
-     tdc_data_in_i <= ipu_data_out_i;
-     a_data_ready_i <= ipu_dataready_out_i;
-     b_data_ready_i <= ipu_dataready_out_i;
-     c_data_ready_i <= ipu_dataready_out_i;
-     d_data_ready_i <= ipu_dataready_out_i;
-     token_in_i <= ipu_dataready_out_end_pulse ;
-     TOKEN_OUT <= '0';
+        pulse     => ipu_dataready_out_end_pulse);
+
+    tdc_clk_i      <= CLK;
+    tdc_data_in_i  <= ipu_data_out_i;
+    a_data_ready_i <= ipu_dataready_out_i;
+    b_data_ready_i <= ipu_dataready_out_i;
+    c_data_ready_i <= ipu_dataready_out_i;
+    d_data_ready_i <= ipu_dataready_out_i;
+    token_in_i     <= ipu_dataready_out_end_pulse;
+    TOKEN_OUT      <= '0';
     
-   end generate TDC_INT_FOR_DIFF_PLATFORMSd;
+  end generate TDC_INT_FOR_DIFF_PLATFORMSd;
+
 
- 
   TDC_INT : tdc_interfacev2
     generic map (
-      ENABLE_DMA => ENABLE_DMA,
-      NUMBER_OFF_ADD_DATA =>  NUMBER_OFF_ADD_DATA,
+      ENABLE_DMA          => ENABLE_DMA,
+      NUMBER_OFF_ADD_DATA => NUMBER_OFF_ADD_DATA,
       TRBV2_TYPE          => TRBV2_TYPE
       )
     port map (
@@ -2136,7 +2159,7 @@ begin
       TDC_CLK                => tdc_clk_i,
       RESET                  => reset_i,
       TDC_DATA_IN            => tdc_data_in_i,
-      START_TDC_READOUT      => start_tdc_readout_i,--lvl1_trigger_i,
+      START_TDC_READOUT      => start_tdc_readout_i,  --lvl1_trigger_i,
       A_TDC_ERROR            => A_TDC_ERROR,
       B_TDC_ERROR            => B_TDC_ERROR,
       C_TDC_ERROR            => C_TDC_ERROR,
@@ -2144,18 +2167,18 @@ begin
       A_TDC_READY            => a_data_ready_i,
       B_TDC_READY            => b_data_ready_i,
       C_TDC_READY            => c_data_ready_i,
-      D_TDC_READY            => d_data_ready_i, 
-      SEND_TDC_TOKEN         => token_out_i,  
-      RECEIVED_TDC_TOKEN     => token_in_i, 
+      D_TDC_READY            => d_data_ready_i,
+      SEND_TDC_TOKEN         => token_out_i,
+      RECEIVED_TDC_TOKEN     => token_in_i,
       GET_TDC_DATA           => GET_DATA,
       LVL2_READOUT_COMPLETED => lvl2_readout_completed_i,
       LVL1_TAG               => lvl1_trigger_tag_i,  --apl_seqnr_out_i,  --tdc_tag_i,
       LVL1_RND_CODE          => lvl1_rnd_number_out_i,  --apl_seqnr_out_i,  --tdc_tag_i,
       LVL1_CODE              => lvl1_trigger_code_i,  --apl_data_out_i(3 downto 0),  --tdc_code_i,
       LVL2_TAG               => lvl2_trigger_tag_i(7 downto 0),  --apl_seqnr_out_i,  --tdc_tag_i,
-      HOW_MANY_ADD_DATA      => fpga_register_06_i(23 downto 16), 
+      HOW_MANY_ADD_DATA      => fpga_register_06_i(23 downto 16),
       ADDITIONAL_DATA        => additional_data_i,
-      LVL2_TRIGGER           => lvl2_trigger_i, 
+      LVL2_TRIGGER           => lvl2_trigger_i,
       TDC_DATA_OUT           => tdc_data_out_i,
       TDC_DATA_VALID         => tdc_data_valid_i,
       ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
@@ -2187,19 +2210,19 @@ begin
   
   
   
-  OMIT_PROBLEM_WITH_MISS_REF: process (CLK, reset_i)
-  begin  
+  OMIT_PROBLEM_WITH_MISS_REF : process (CLK, reset_i)
+  begin
     if rising_edge(CLK) then
       if reset_i = '1' then
         optical_tdc_trigger_reg_1 <= '0';
         optical_tdc_trigger_reg_2 <= '0';
         optical_tdc_trigger_reg_2 <= '0';
-        optical_tdc_trigger <= '0';
+        optical_tdc_trigger       <= '0';
       else
         optical_tdc_trigger_reg_1 <= lvl1_trigger_i;
         optical_tdc_trigger_reg_2 <= optical_tdc_trigger_reg_1;
         optical_tdc_trigger_reg_3 <= optical_tdc_trigger_reg_2;
-        optical_tdc_trigger <= optical_tdc_trigger_reg_1 or optical_tdc_trigger_reg_2 or optical_tdc_trigger_reg_3;
+        optical_tdc_trigger       <= optical_tdc_trigger_reg_1 or optical_tdc_trigger_reg_2 or optical_tdc_trigger_reg_3;
       end if;
     end if;
   end process OMIT_PROBLEM_WITH_MISS_REF;
@@ -2207,140 +2230,166 @@ begin
 
   EXT_TRIGGER_1 : edge_to_pulse
     port map (
-      clock  => TDC_CLK,
-      en_clk => '1',
-      signal_in => optical_tdc_trigger,--fast_ref_trigger_synch,
-      pulse  => fast_ref_trigger_pulse);
+      clock     => TDC_CLK,
+      en_clk    => '1',
+      signal_in => optical_tdc_trigger,  --fast_ref_trigger_synch,
+      pulse     => fast_ref_trigger_pulse);
 
-  SYNCH_WITHC_TDC_CLK: process (TDC_CLK, reset_i)
+  SYNCH_WITHC_TDC_CLK : process (TDC_CLK, reset_i)
   begin  -- process SYNCH_WITHC_TDC_CLK
     if rising_edge(TDC_CLK) then
-      if reset_i = '1' then               -- asynchronous reset (active low)
+      if reset_i = '1' then             -- asynchronous reset (active low)
         fast_ref_trigger_pulse_synch <= '0';
       else
         fast_ref_trigger_pulse_synch <= fast_ref_trigger_pulse;
       end if;
     end if;
   end process SYNCH_WITHC_TDC_CLK;
-  
-  a_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
-  b_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
-  c_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
-  d_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
+
+  a_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
+  b_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
+  c_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
+  d_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
+
+
 
 
-  
-  
   BLINK_TDC_DIODS_ON_TRBv2c : process (CLK, reset_i)
-  begin  
+  begin
     if rising_edge(CLK) then
       if reset_i = '1' then
-        A_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod in trbv2b real!!!
-        B_TDC_POWERUP  <=  '1';       -- -//-
-        C_TDC_POWERUP  <=  '1';       -- -//-
-        D_TDC_POWERUP  <=  '1';       -- -//-
-      elsif rw_register_i(3)(8) = '0'  then  --trbv2b deafoult '0'
-        A_TDC_POWERUP  <=  '1';      
-        B_TDC_POWERUP  <=  '1';      
-        C_TDC_POWERUP  <=  '1';      
-        D_TDC_POWERUP  <=  '1';      
+        A_TDC_POWERUP <= '1';  --in trbv2c this is a diod in trbv2b real!!!
+        B_TDC_POWERUP <= '1';           -- -//-
+        C_TDC_POWERUP <= '1';           -- -//-
+        D_TDC_POWERUP <= '1';           -- -//-
+      elsif rw_register_i(3)(8) = '0' then  --trbv2b deafoult '0'
+        A_TDC_POWERUP <= '1';
+        B_TDC_POWERUP <= '1';
+        C_TDC_POWERUP <= '1';
+        D_TDC_POWERUP <= '1';
       else
-        A_TDC_POWERUP  <=  not r_register_i(19)(22);       
-        B_TDC_POWERUP  <=  not r_register_i(19)(23);      
-        C_TDC_POWERUP  <=  not r_register_i(19)(24);      
-        D_TDC_POWERUP  <=  not r_register_i(19)(25);       
+        A_TDC_POWERUP <= not r_register_i(18)(22);
+        B_TDC_POWERUP <= not r_register_i(18)(23);
+        C_TDC_POWERUP <= not r_register_i(18)(24);
+        D_TDC_POWERUP <= not r_register_i(18)(25);
       end if;
     end if;
   end process BLINK_TDC_DIODS_ON_TRBv2c;
-  
-  DBAD         <= lvl1_busy_i;
+
+  DBAD  <= lvl1_busy_i;
 --  DINT         <= TDC_CLK;--tdc_data_valid_i;
-  DWAIT        <= addon_clk;
- -- DGOOD        <= lvl2_busy_i;
-  
-  LVL1_TAG_COUNT: up_down_counter
-      generic map (
-        NUMBER_OF_BITS => 8)
-      port map (
-        CLK       => TDC_CLK,
-        RESET     => reset_i,
-        COUNT_OUT => ref_time_counter,
-        UP_IN     => fast_ref_trigger_pulse,
-        DOWN_IN   => '0');
-  
-  CHECK_REF_AND_DIGITAL_TRIGGER: process (CLK, reset_i,lvl1_trigger_i,ref_time_counter,lvl1_trigger_tag_i)
+  DWAIT <= addon_clk;
+  -- DGOOD        <= lvl2_busy_i;
+
+  LVL1_TAG_COUNT : up_down_counter
+    generic map (
+      NUMBER_OF_BITS => 8)
+    port map (
+      CLK       => TDC_CLK,
+      RESET     => reset_i,
+      COUNT_OUT => ref_time_counter,
+      UP_IN     => fast_ref_trigger_pulse,
+      DOWN_IN   => '0');
+
+  CHECK_REF_AND_DIGITAL_TRIGGER : process (CLK, reset_i, lvl1_trigger_i, ref_time_counter, lvl1_trigger_tag_i)
   begin
     if rising_edge(CLK) then
-      if reset_i = '1' then            
+      if reset_i = '1' then
         trigger_miss_match <= '0';
-      elsif lvl1_trigger_i  = '1' and (ref_time_counter /= lvl1_trigger_tag_i(7 downto 0)) then
+      elsif lvl1_trigger_i = '1' and (ref_time_counter /= lvl1_trigger_tag_i(7 downto 0)) then
         trigger_miss_match <= '1';
       elsif fast_ref_trigger_pulse = '1' and (ref_time_counter /= lvl1_trigger_tag_i(7 downto 0)) then
-        trigger_miss_match <= '0'; --trigger_miss_match;
+        trigger_miss_match <= '0';      --trigger_miss_match;
       end if;
     end if;
   end process CHECK_REF_AND_DIGITAL_TRIGGER;
-  
+
   fpga_register_0a_i(15 downto 0) <= ref_time_counter & lvl1_trigger_tag_i(7 downto 0);
-  fpga_register_0a_i(30) <= not_hades_trigger;
-  fpga_register_0a_i(31) <= fast_ref_trigger;
+  fpga_register_0a_i(30)          <= not_hades_trigger;
+  fpga_register_0a_i(31)          <= fast_ref_trigger;
 -----------------------------------------------------------------------------
 -- MULTIPLEX_DATA_TO_ETRAX
 -----------------------------------------------------------------------------
 
-    MULTIPLEX_DATA_TO_ETRAX: process(CLK,reset_i,external_mode_i)
-    begin 
-      if rising_edge(CLK) then
-        if reset_i = '1' then
-          external_data_in_i <= (others => '0');
-        elsif external_mode_i(7 downto 0) = x"01" then
-          external_data_in_i <= dsp_data_out_i;
-        elsif external_mode_i(7 downto 0) = x"02" then
-          external_data_in_i <= sdram_data_out_i;
-        else
-          external_data_in_i <= x"0000"&external_mode_i;
-        end if;
+  MULTIPLEX_DATA_TO_ETRAX : process(CLK, reset_i, external_mode_i)
+  begin
+    if rising_edge(CLK) then
+      if reset_i = '1' then
+        external_data_in_i <= (others => '0');
+      elsif external_mode_i(7 downto 0) = x"01" then
+        external_data_in_i <= dsp_data_out_i;
+      elsif external_mode_i(7 downto 0) = x"02" then
+        external_data_in_i <= sdram_data_out_i;
+      elsif external_mode_i(7 downto 0) = x"06" then
+         external_data_in_i <= x"0000" & sfp_data_out;
+      else
+        external_data_in_i <= x"0000"&external_mode_i;
       end if;
+    end if;
   end process MULTIPLEX_DATA_TO_ETRAX;
 --       dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
   --\@@##$$%%^^&&**(((  put dsp_strobe to the dsp interface (extarnal mode has
   -- to be there)
 --       sdram_strobe_i <= '1' when external_mode_i(7 downto 0) = x"02" and external_ack_i = '1' else '0';  
---       external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or ADO_TTL(12);
+       external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or sfp_external_valid;
 -------------------------------------------------------------------------------
 -- sfp interface
 -------------------------------------------------------------------------------
   Sfp_Interface_1: Sfp_Interface
     generic map (
-      device_add       => "1010001",
-      temp_start_add   => "01100000",
-      opt_pwr_start_add => "01101000",
-      I2C_SPEED        => "11111101")
+      I2C_SPEED => X"0200")
     port map (
-      CLK_IN        => CLK,
-      RST_IN        => reset_i,
-      START_PULSE   => external_ack_i,
-      TEMP_DATA_OUT => r_register_i(20)(15 downto 0),
-      OPT_DATA_OUT  => r_register_i(20)(31 downto 16),
-      SCL           => SCL,
-      SDA           => SDA,
-      DEBUG         => r_register_i(21)
-      );
---  ADO_TTL(4 downto 0) <= r_register_i(21)(4 downto 0);
---  ADO_TTL(15 downto 8) <= r_register_i(21)(15 downto 8);
+      CLK_IN         => CLK,
+      RST_IN         => reset_i,
+      START_PULSE    => external_ack_i,
+      DEVICE_ADDRESS => external_mode_i(7 downto 0),
+      DATA_OUT       => sfp_data_out,--external_data_in_i(15 downto 0),--r_register_i(20)(15 downto 0),
+      SCL            => SCL,
+      SDA            => SDA,
+      EN_RESET       => external_address_i(15),
+      READ_DONE      => sfp_external_valid,           --external_valid_i
+      DEBUG          => r_register_i(21),
+      SFP_ADDRESS    => external_address_i);
+  
+--  Sfp_Interface_1 : Sfp_Interface
+--    generic map (
+--      device_add        => "1010001",
+--      temp_start_add    => "01100000",
+--      opt_pwr_start_add => "01101000",
+--      I2C_SPEED         => "11111101")
+--    port map (
+--      CLK_IN        => CLK,
+--      RST_IN        => reset_i,
+--      START_PULSE   => external_ack_i,
+--      TEMP_DATA_OUT => r_register_i(20)(15 downto 0),
+--      OPT_DATA_OUT  => r_register_i(20)(31 downto 16),
+--      SCL           => SDA,--SCL,
+--      SDA           => SCL,--SDA,
+--      EN_RESET      => external_address_i(15),
+--      DEBUG         => r_register_i(21),
+--      SFP_ADDRESS   => external_address_i
+-- --     DEVICE_ADDRESS => external_mode_i(7 downto 0)
+--      );
+--  SFP_MOD_LOW <= '0';
+
+--  ENABLE_SFP_DEBUG : if DEBUG_OPTION = 3 generate
+--    ADO_TTL(4 downto 0)  <= r_register_i(21)(4 downto 0);
+--    ADO_TTL(15 downto 8) <= r_register_i(21)(15 downto 8);
+--  end generate ENABLE_SFP_DEBUG;
+
 -------------------------------------------------------------------------------
 -- etrax interface
 -------------------------------------------------------------------------------
-  ETRAX_IRQ    <= '1';
+  ETRAX_IRQ <= '1';
+
 
-  
   ETRAX_INTERFACE_LOGIC : etrax_interfacev2
     generic map (
-      ENABLE_DMA => ENABLE_DMA,
-      RW_SYSTEM => RW_SYSTEM,
+      ENABLE_DMA          => ENABLE_DMA,
+      RW_SYSTEM           => RW_SYSTEM,
       RW_REGISTERS_NUMBER => RW_REGISTERS_NUMBER,
-      R_REGISTERS_NUMBER => R_REGISTERS_NUMBER,
-      TRBNET_ENABLE => TRBNET_ENABLE
+      R_REGISTERS_NUMBER  => R_REGISTERS_NUMBER,
+      TRBNET_ENABLE       => TRBNET_ENABLE
       )
     port map (
       CLK                    => CLK,
@@ -2374,89 +2423,89 @@ begin
       TRB_LVL2_BUSY          => lvl2_busy_i
       );
 
-  REWRITE_R_REGISTER: for i in 1 to R_REGISTERS_NUMBER generate
+  REWRITE_R_REGISTER : for i in 1 to R_REGISTERS_NUMBER generate
     r_register_vector(32*i-1 downto 32*(i-1)) <= r_register_i(i-1);
   end generate REWRITE_R_REGISTER;
 
-  REWRITE_RW_REGISTER: for i in 1 to RW_REGISTERS_NUMBER generate
+  REWRITE_RW_REGISTER : for i in 1 to RW_REGISTERS_NUMBER generate
     rw_register_i(i-1) <= rw_register_vector(32*i-1 downto 32*(i-1));
   end generate REWRITE_RW_REGISTER;
-  
+
   fpga_register_01_i <= tdc_register_00_i;
   fpga_register_02_i <= tdc_register_01_i;
   fpga_register_03_i <= tdc_register_02_i;
   fpga_register_04_i <= tdc_register_03_i;
   fpga_register_05_i <= tdc_register_04_i;
-  
+
 --  fpga_register_09_i <= x"000" & "00" & TLK_RX_ER & TLK_RX_DV & TLK_RXD;--tlk_register_00_i;
 --  fpga_register_0a_i <= tdc_data_out_i;--tlk_register_01_i;
 --  fpga_register_0b_i <= FS_PB_17&lvl2_trigger_code_i(3)& tdc_data_valid_i& '0' & lvl1_trigger_code_i & lvl1_trigger_tag_i & x"00" & lvl1_trigger_tag_i;
   fpga_register_0c_i <= trigger_miss_match & opt_busy_lvl1_or_lvl2 & TLK_RX_DV & TLK_RX_ER & x"000"& TLK_RXD;
 --  fpga_register_0d_i <= dtu_debug_00_i;--stat_init_buffer_i;
-  r_register_i(0) <= x"aaaabbbb";
-  r_register_i(1) <= tdc_register_00_i;
-  r_register_i(2) <= tdc_register_01_i;
-  r_register_i(3) <= tdc_register_02_i;
-  r_register_i(4) <= tdc_register_03_i;
-  r_register_i(5) <= fpga_register_05_i;
-  r_register_i(6) <= conv_std_logic_vector(VERSION_NUMBER_TIME,32);
-  r_register_i(7) <= x"abcd0001";--fpga_register_07_i;
-  r_register_i(8) <= fpga_register_08_i;
-  r_register_i(9) <= fpga_register_09_i;
-  r_register_i(10) <= fpga_register_0a_i;
-  r_register_i(11) <= fpga_register_0b_i;
-  r_register_i(12) <= fpga_register_0c_i;
-  r_register_i(13) <= fpga_register_0d_i;
+  r_register_i(0)    <= x"aaaabbbb";
+  r_register_i(1)    <= tdc_register_00_i;
+  r_register_i(2)    <= tdc_register_01_i;
+  r_register_i(3)    <= tdc_register_02_i;
+  r_register_i(4)    <= tdc_register_03_i;
+  r_register_i(5)    <= fpga_register_05_i;
+  r_register_i(6)    <= conv_std_logic_vector(VERSION_NUMBER_TIME, 32);
+  r_register_i(7)    <= x"abcd0001";    --fpga_register_07_i;
+  r_register_i(8)    <= fpga_register_08_i;
+  r_register_i(9)    <= fpga_register_09_i;
+  r_register_i(10)   <= fpga_register_0a_i;
+  r_register_i(11)   <= fpga_register_0b_i;
+  r_register_i(12)   <= fpga_register_0c_i;
+  r_register_i(13)   <= fpga_register_0d_i;
 --  r_register_i((14+1)*32-1 downto 14*32) <= x"abcd0002";
   fpga_register_06_i <= rw_register_i(0);
   fpga_register_07_i <= rw_register_i(1);
   fpga_register_0e_i <= rw_register_i(2);
 
 
-  
+
 -------------------------------------------------------------------------------
 -- dsp -- remember about offset for 
 -- adressing internal registers (0x10000000). DSP is foreseen
 -- for multiprocessor environment  
 -------------------------------------------------------------------------------
-  
-  DSP_EN: if DSP_INT_ENABLE = 1 generate
-    DSP_DATA_REGISTER: process (CLK, reset_i)
+
+  DSP_EN : if DSP_INT_ENABLE = 1 generate
+    DSP_DATA_REGISTER : process (CLK, reset_i)
     begin  -- process DSP_DATA_REGISTER
-      if CLK'event and CLK = '1' then 
+      if CLK'event and CLK = '1' then
         if reset_i = '1' then
-          dsp_data_reg_in_i <= x"00000000";
+          dsp_data_reg_in_i  <= x"00000000";
           dsp_data_reg_out_i <= x"00000000";
-          dsp_bm_reg <= '0';
+          dsp_bm_reg         <= '0';
         else
-          dsp_bm_reg <= DSP_BM;
-          dsp_data_reg_in_i <= DSPDAT;
+          dsp_bm_reg         <= DSP_BM;
+          dsp_data_reg_in_i  <= DSPDAT;
           dsp_data_reg_out_i <= dspdat_out_i;
         end if;
       end if;
     end process DSP_DATA_REGISTER;
 
-    DSP_HBR <= '1';
-    DSP_RESET <= fpga_register_06_i(4);
-    DSP_HBR <= dsp_hbr_i;
-    DSPDAT  <= dspdat_out_i;
+    DSP_HBR     <= '1';
+    DSP_RESET   <= fpga_register_06_i(4);
+    DSP_HBR     <= dsp_hbr_i;
+    DSPDAT      <= dspdat_out_i;
     dspdat_in_i <= DSPDAT;
-    DSP_WRL <= DSP_WRL_i;
-    DSP_RD <= DSP_RD_i;
-    DSPADDR <= dspaddr_i;
-    DSP_BOFF <= fpga_register_06_i(5);
-    DSP_IRQ <= x"1";
-    DSP_BMS <= '1' when fpga_register_06_i(3) = '0' else 'Z';
-    DSP_BM <= '0' when fpga_register_06_i(3) = '0' else 'Z';
-
-    DSP_INTERFACE_LOGIC: dsp_interface
+    DSP_WRL     <= DSP_WRL_i;
+    DSP_RD      <= DSP_RD_i;
+    DSPADDR     <= dspaddr_i;
+    DSP_BOFF    <= fpga_register_06_i(5);
+    DSP_IRQ     <= x"1";
+    DSP_BMS     <= '1' when fpga_register_06_i(3) = '0' else 'Z';
+    DSP_BM      <= '0' when fpga_register_06_i(3) = '0' else 'Z';
+
+    DSP_INTERFACE_LOGIC : dsp_interface
       port map (
         HBR_OUT            => dsp_hbr_i,
         HBG_IN             => DSP_HBG,
         RD_OUT             => DSP_RD_i,
-        DSP_DATA_OUT       => dspdat_out_i,--DSPDAT to DSP,
-        DSP_DATA_IN        => dspdat_in_i,--DSPDAT to FPGA,
-        ADDRESS_DSP        => dspaddr_i,--DSPADDR,
+        DSP_DATA_OUT       => dspdat_out_i,    --DSPDAT to DSP,
+        DSP_DATA_IN        => dspdat_in_i,     --DSPDAT to FPGA,
+        ADDRESS_DSP        => dspaddr_i,       --DSPADDR,
         WRL                => DSP_WRL_i,
         WRH                => DSP_WRH,
         BM_IN              => DSP_BM,
@@ -2468,231 +2517,231 @@ begin
         R_W_ENABLE         => external_mode_i(15),
         TRIGGER            => dsp_strobe_i,
         INTERNAL_DATA_IN   => external_data_out_i,
-        INTERNAL_DATA_OUT  => dsp_data_out_i,--external_data_in_i,
+        INTERNAL_DATA_OUT  => dsp_data_out_i,  --external_data_in_i,
         INTERNAL_ADDRESS   => external_address_i,
         VALID_DATA_SENT    => dsp_external_valid_i,
         ACKNOWLEDGE        => dsp_strobe_i,
-        DEBUGSTATE_MACHINE =>  dsp_register_00_i);
+        DEBUGSTATE_MACHINE => dsp_register_00_i);
   end generate DSP_EN;
 
-    
+
 -------------------------------------------------------------------------------
 -- sdram interface
 -------------------------------------------------------------------------------
-  
-    SDRAM_EN: if SDRAM_INT_ENABLE = 1 generate
-      SDRAM_INTERFACE_LOGIC: sdram_interface
-        port map (
-            CLK_SDRAM          => VSD_CLOCK,
-            CKE                => VSD_CKE,
-            CS                 => vsd_cs_i,
-            RAS                => VSD_RAS,
-            CAS                => VSD_CAS,
-            WE                 => VSD_WE,
-            DQM                => VSD_DQML,
-            BA                 => VSD_BA,
-            A                  => VSD_A,
-            DQ                 => VSD_D,
-            CLK                => CLK,
-            RESET              => reset_i,
-            TRIGGER            => external_ack_i,
-            INTERNAL_DATA_IN   => external_data_out_i,
-            INTERNAL_DATA_OUT  => sdram_data_out_i,
-            INTERNAL_ADDRESS   => external_address_i,
-            INTERNAL_MODE      => external_mode_i,
-            VALID_DATA_SENT    => sdram_external_valid_i,
-            DEBUGSTATE_MACHINE => sdram_register_00_i);
-      
-     VSD_CSEH <= vsd_cs_i;
-     VSD_CSEL <= vsd_cs_i;
+
+  SDRAM_EN : if SDRAM_INT_ENABLE = 1 generate
+    SDRAM_INTERFACE_LOGIC : sdram_interface
+      port map (
+        CLK_SDRAM          => VSD_CLOCK,
+        CKE                => VSD_CKE,
+        CS                 => vsd_cs_i,
+        RAS                => VSD_RAS,
+        CAS                => VSD_CAS,
+        WE                 => VSD_WE,
+        DQM                => VSD_DQML,
+        BA                 => VSD_BA,
+        A                  => VSD_A,
+        DQ                 => VSD_D,
+        CLK                => CLK,
+        RESET              => reset_i,
+        TRIGGER            => external_ack_i,
+        INTERNAL_DATA_IN   => external_data_out_i,
+        INTERNAL_DATA_OUT  => sdram_data_out_i,
+        INTERNAL_ADDRESS   => external_address_i,
+        INTERNAL_MODE      => external_mode_i,
+        VALID_DATA_SENT    => sdram_external_valid_i,
+        DEBUGSTATE_MACHINE => sdram_register_00_i);
+
+    VSD_CSEH <= vsd_cs_i;
+    VSD_CSEL <= vsd_cs_i;
 --     ADO_TTL(18) <= '1';
 --     ADO_TTL(15 downto 0) <= (others => 'Z');
-    end generate SDRAM_EN;
+  end generate SDRAM_EN;
+
 
-  
 -------------------------------------------------------------------------------
 -- opt dtu
 -------------------------------------------------------------------------------
-  
-  CTU_DTU_OPT_EN: if DTU_ENABLE = 2 generate
 
-    TLK_TX_ER  <= '0';
-    SFP_TX_DIS  <= '0';--fpga_register_06_i(15);
+  CTU_DTU_OPT_EN : if DTU_ENABLE = 2 generate
+
+    TLK_TX_ER   <= '0';
+    SFP_TX_DIS  <= '0';                 --fpga_register_06_i(15);
     TLK_LOOPEN  <= '0';
     TLK_LCKREFN <= '1';
     TLK_ENABLE  <= '1';
     TLK_PRBSEN  <= '0';
 
-    TLK_RX_CLK_BUFR: BUFR
+    TLK_RX_CLK_BUFR : BUFR
       port map(
-        CE => '1',
+        CE  => '1',
         CLR => '0',
-        I => TLK_RX_CLK,
-        O => tlk_rx_clk_r(0)
+        I   => TLK_RX_CLK,
+        O   => tlk_rx_clk_r(0)
         );
 
-    TLK_CLK_BUFR: BUFR
+    TLK_CLK_BUFR : BUFR
       port map(
-        CE => '1',
+        CE  => '1',
         CLR => '0',
-        I => TLK_CLK,
-        O => tlk_clk_r(0)
+        I   => TLK_CLK,
+        O   => tlk_clk_r(0)
         );
-    
-    DTU_EN: if TRBV2_TYPE < 4    generate
-      DTU_OPT_INST: optical_dtu
+
+    DTU_EN : if TRBV2_TYPE < 4 generate
+      DTU_OPT_INST : optical_dtu
         port map (
-          CLK                    => CLK,
-          RX_CLK                 => tlk_rx_clk_r(0),
-          TX_CLK                 => tlk_clk_r(0),
-          RESET                  => reset_i,
-          OPT_DATA_IN            => TLK_RXD,
-          OPT_DATA_OUT           => TLK_TXD,
-          OPT_DATA_VALID_IN      => TLK_RX_DV,
-          OPT_DATA_ERR           => TLK_RX_ER,
-          OPT_DATA_SEND          => TLK_TX_EN,
-          LVL1_TRIGGER           => lvl1_trigger_i,
-          LVL1_TRIGGER_CODE      => lvl1_trigger_code_i,
-          LVL1_TRIGGER_TAG       => lvl1_trigger_tag_i(7 downto 0),
-          LVL2_TRIGGER           => lvl2_trigger_i,
-          LVL2_TRIGGER_CODE      => lvl2_trigger_code_i(3),
-          LVL2_TRIGGER_TAG       => lvl2_trigger_tag_i(7 downto 0),
-          LVL1_BUSY              => busy_or_error,
-          LVL2_BUSY              => lvl2_busy_i,
+          CLK                       => CLK,
+          RX_CLK                    => tlk_rx_clk_r(0),
+          TX_CLK                    => tlk_clk_r(0),
+          RESET                     => reset_i,
+          OPT_DATA_IN               => TLK_RXD,
+          OPT_DATA_OUT              => TLK_TXD,
+          OPT_DATA_VALID_IN         => TLK_RX_DV,
+          OPT_DATA_ERR              => TLK_RX_ER,
+          OPT_DATA_SEND             => TLK_TX_EN,
+          LVL1_TRIGGER              => lvl1_trigger_i,
+          LVL1_TRIGGER_CODE         => lvl1_trigger_code_i,
+          LVL1_TRIGGER_TAG          => lvl1_trigger_tag_i(7 downto 0),
+          LVL2_TRIGGER              => lvl2_trigger_i,
+          LVL2_TRIGGER_CODE         => lvl2_trigger_code_i(3),
+          LVL2_TRIGGER_TAG          => lvl2_trigger_tag_i(7 downto 0),
+          LVL1_BUSY                 => busy_or_error,
+          LVL2_BUSY                 => lvl2_busy_i,
           OPT_DTU_DEBUG_REGISTER_00 => fpga_register_0d_i,
           OPT_DTU_DEBUG_REGISTER_01 => fpga_register_0b_i
           );
 --    busy_or_error <= trigger_miss_match or lvl1_busy_i;
-          busy_or_error <= lvl1_busy_i;
-    ADO_TTL(0) <= TLK_RX_ER;
-    ADO_TTL(1) <= TLK_RX_DV;
-    ADO_TTL(5 downto 2) <= TLK_RXD(15 downto 12);
-    ADO_TTL(6) <= lvl1_trigger_i;
-    ADO_TTL(7) <= lvl1_busy_i;
-    ADO_TTL(8) <= lvl2_trigger_i;
-    ADO_TTL(9) <= lvl2_busy_i;
-    ADO_TTL(10) <= FS_PB_17;
-    ADO_TTL(11) <= tdc_data_valid_i;
-    ADO_TTL(12) <= lvl2_trigger_code_i(3);
+      busy_or_error       <= lvl1_busy_i;
+      ADO_TTL(0)          <= TLK_RX_ER;
+      ADO_TTL(1)          <= TLK_RX_DV;
+      ADO_TTL(5 downto 2) <= TLK_RXD(15 downto 12);
+      ADO_TTL(6)          <= lvl1_trigger_i;
+      ADO_TTL(7)          <= lvl1_busy_i;
+      ADO_TTL(8)          <= lvl2_trigger_i;
+      ADO_TTL(9)          <= lvl2_busy_i;
+      ADO_TTL(10)         <= FS_PB_17;
+      ADO_TTL(11)         <= tdc_data_valid_i;
+      ADO_TTL(12)         <= lvl2_trigger_code_i(3);
 
     end generate DTU_EN;
-    
+
 ---------------------------------------------------------------------------
 -- optical ctu 
 ---------------------------------------------------------------------------
-    
-    CTU_EN: if (TRBV2_TYPE =4 or TRBV2_TYPE =5) and TRBNET_ENABLE = 0 generate
-      CTU_OPT_INST: optical_ctu
+
+    CTU_EN : if (TRBV2_TYPE = 4 or TRBV2_TYPE = 5) and TRBNET_ENABLE = 0 generate
+      CTU_OPT_INST : optical_ctu
         port map (
-            CLK               => CLK,
-            RESET             => reset_i,
-            RX_CLK            => tlk_rx_clk_r(0),
-            TX_CLK            => tlk_clk_r(0),
-            OPT_DATA_IN       => TLK_RXD,
-            OPT_DATA_OUT      => TLK_TXD,
-            OPT_DATA_VALID_IN => TLK_RX_DV,
-            OPT_DATA_ERR      => TLK_RX_ER,
-            OPT_DATA_SEND     => TLK_TX_EN,
-            LVL1_TRIGGER      => lvl1_trigger_i,
-            LVL1_CODE         => lvl1_trigger_code_i,
-            LVL1_TAG          => lvl1_trigger_tag_i(7 downto 0),
-            LVL1_BUSY         => opt_lvl1_busy_i,
-            LVL2_TRIGGER      => lvl2_trigger_i,
-            LVL2_CODE         => lvl2_trigger_code_i(3),
-            LVL2_TAG          => lvl2_trigger_tag_i(7 downto 0),
-            LVL2_BUSY         => opt_lvl2_busy_i,
-            OPT_CTU_DEBUG_00     => fpga_register_0d_i,
-            OPT_CTU_DEBUG_01     => fpga_register_0b_i
-            );
-      
-    ADO_TTL(0) <= TLK_RX_ER;
-    ADO_TTL(1) <= TLK_RX_DV;
-    ADO_TTL(5 downto 2) <= TLK_RXD(15 downto 12);
-    ADO_TTL(6) <= lvl1_trigger_i;
-    ADO_TTL(7) <= opt_lvl1_busy_i;
-    ADO_TTL(8) <= lvl2_trigger_i;
-    ADO_TTL(9) <= opt_lvl2_busy_i;
-    ADO_TTL(10) <= opt_busy_lvl1_or_lvl2;
-    ADO_TTL(11) <= fast_ref_trigger;
-    ADO_TTL(12) <= lvl2_trigger_code_i(3);
-    ADO_TTL(39 downto 32) <= (others => 'Z');
+          CLK               => CLK,
+          RESET             => reset_i,
+          RX_CLK            => tlk_rx_clk_r(0),
+          TX_CLK            => tlk_clk_r(0),
+          OPT_DATA_IN       => TLK_RXD,
+          OPT_DATA_OUT      => TLK_TXD,
+          OPT_DATA_VALID_IN => TLK_RX_DV,
+          OPT_DATA_ERR      => TLK_RX_ER,
+          OPT_DATA_SEND     => TLK_TX_EN,
+          LVL1_TRIGGER      => lvl1_trigger_i,
+          LVL1_CODE         => lvl1_trigger_code_i,
+          LVL1_TAG          => lvl1_trigger_tag_i(7 downto 0),
+          LVL1_BUSY         => opt_lvl1_busy_i,
+          LVL2_TRIGGER      => lvl2_trigger_i,
+          LVL2_CODE         => lvl2_trigger_code_i(3),
+          LVL2_TAG          => lvl2_trigger_tag_i(7 downto 0),
+          LVL2_BUSY         => opt_lvl2_busy_i,
+          OPT_CTU_DEBUG_00  => fpga_register_0d_i,
+          OPT_CTU_DEBUG_01  => fpga_register_0b_i
+          );
+
+      ADO_TTL(0)            <= TLK_RX_ER;
+      ADO_TTL(1)            <= TLK_RX_DV;
+      ADO_TTL(5 downto 2)   <= TLK_RXD(15 downto 12);
+      ADO_TTL(6)            <= lvl1_trigger_i;
+      ADO_TTL(7)            <= opt_lvl1_busy_i;
+      ADO_TTL(8)            <= lvl2_trigger_i;
+      ADO_TTL(9)            <= opt_lvl2_busy_i;
+      ADO_TTL(10)           <= opt_busy_lvl1_or_lvl2;
+      ADO_TTL(11)           <= fast_ref_trigger;
+      ADO_TTL(12)           <= lvl2_trigger_code_i(3);
+      ADO_TTL(39 downto 32) <= (others => 'Z');
     end generate CTU_EN;
-  
-    BUSY_SELECT: if TRBV2_TYPE=4 generate
-      not_lvl1_busy_opt  <= opt_lvl1_busy_i or vulom_busy;        
+
+    BUSY_SELECT : if TRBV2_TYPE = 4 generate
+      not_lvl1_busy_opt <= opt_lvl1_busy_i or vulom_busy;
     end generate BUSY_SELECT;
-    SUB_SYSTEM_SELECT: if TRBV2_TYPE = 5 generate
+    SUB_SYSTEM_SELECT : if TRBV2_TYPE = 5 generate
       
-      not_lvl1_busy_opt  <= not opt_lvl1_busy_i;
+      not_lvl1_busy_opt <= not opt_lvl1_busy_i;
 
-      SYNCH_SIGNALS: process (CLK, reset_i)
+      SYNCH_SIGNALS : process (CLK, reset_i)
       begin  -- process SYNCH_SIGNALS
         if rising_edge(CLK) then
-          if reset_i = '1' then           -- asynchronous reset (active low)
-            ext_lvl1_trigger_i <= '0';
-            lvl1_trigger_i <= '0';
-            lvl1_trigger_code_i <= x"1";
+          if reset_i = '1' then         -- asynchronous reset (active low)
+            ext_lvl1_trigger_i             <= '0';
+            lvl1_trigger_i                 <= '0';
+            lvl1_trigger_code_i            <= x"1";
             lvl1_trigger_tag_i(7 downto 0) <= x"00";
 
           else
-            ext_lvl1_trigger_i <= (not_hades_trigger and fpga_register_06_i(7) and (not(opt_busy_lvl1_or_lvl2))) or fpga_register_0e_i(0);
-            lvl1_trigger_i <= ext_lvl1_trigger_pulse;
-            lvl1_trigger_code_i <= x"1";
+            ext_lvl1_trigger_i             <= (not_hades_trigger and fpga_register_06_i(7) and (not(opt_busy_lvl1_or_lvl2))) or fpga_register_0e_i(0);
+            lvl1_trigger_i                 <= ext_lvl1_trigger_pulse;
+            lvl1_trigger_code_i            <= x"1";
             lvl1_trigger_tag_i(7 downto 0) <= ext_tag;
 
           end if;
         end if;
       end process SYNCH_SIGNALS;
-    OPT_LVL1_BUSY: process (CLK, reset_i,lvl2_opt_busy_pulse,ext_lvl1_trigger_pulse)
-    begin 
-      if rising_edge(CLK) then  
-        if reset_i = '1' or lvl2_opt_busy_pulse = '1' then
-          opt_busy_lvl1_or_lvl2 <= '0';
-        elsif  (ext_lvl1_trigger_i and fpga_register_06_i(7) and (not(opt_busy_lvl1_or_lvl2))) = '1' then
-          opt_busy_lvl1_or_lvl2 <= '1';
+      OPT_LVL1_BUSY : process (CLK, reset_i, lvl2_opt_busy_pulse, ext_lvl1_trigger_pulse)
+      begin
+        if rising_edge(CLK) then
+          if reset_i = '1' or lvl2_opt_busy_pulse = '1' then
+            opt_busy_lvl1_or_lvl2 <= '0';
+          elsif (ext_lvl1_trigger_i and fpga_register_06_i(7) and (not(opt_busy_lvl1_or_lvl2))) = '1' then
+            opt_busy_lvl1_or_lvl2 <= '1';
+          end if;
         end if;
-      end if;
-    end process OPT_LVL1_BUSY;
-    
-    EXT_LVL1_PULSER : edge_to_pulse
-      port map (
-        clock  => CLK,
-        en_clk => '1',
-        signal_in => ext_lvl1_trigger_i,
-        pulse  => ext_lvl1_trigger_pulse);
+      end process OPT_LVL1_BUSY;
 
-    not_lvl2_opt_busy <= not opt_lvl2_busy_i;
-      
-    EXT_LVL2_PULSER : edge_to_pulse
-      port map (
-        clock  => CLK,
-        en_clk => '1',
-        signal_in => not_lvl2_opt_busy,
-        pulse  => lvl2_opt_busy_pulse);
-    
-    LVL1_TAG_COUNT: up_down_counter
-      generic map (
-        NUMBER_OF_BITS => 8)
-      port map (
-        CLK       => CLK,
-        RESET     => reset_i,
-        COUNT_OUT => ext_tag,
-        UP_IN     => ext_lvl1_trigger_pulse,
-        DOWN_IN   => '0');
+      EXT_LVL1_PULSER : edge_to_pulse
+        port map (
+          clock     => CLK,
+          en_clk    => '1',
+          signal_in => ext_lvl1_trigger_i,
+          pulse     => ext_lvl1_trigger_pulse);
+
+      not_lvl2_opt_busy <= not opt_lvl2_busy_i;
 
-      fpga_register_09_i(7 downto 0) <= ext_tag;
-      fpga_register_09_i(31) <= opt_lvl1_busy_i;
+      EXT_LVL2_PULSER : edge_to_pulse
+        port map (
+          clock     => CLK,
+          en_clk    => '1',
+          signal_in => not_lvl2_opt_busy,
+          pulse     => lvl2_opt_busy_pulse);
+
+      LVL1_TAG_COUNT : up_down_counter
+        generic map (
+          NUMBER_OF_BITS => 8)
+        port map (
+          CLK       => CLK,
+          RESET     => reset_i,
+          COUNT_OUT => ext_tag,
+          UP_IN     => ext_lvl1_trigger_pulse,
+          DOWN_IN   => '0');
+
+      fpga_register_09_i(7 downto 0)  <= ext_tag;
+      fpga_register_09_i(31)          <= opt_lvl1_busy_i;
       fpga_register_09_i(15 downto 8) <= lvl2_trigger_tag_i(7 downto 0);
-                                         
-        
-    AUTO_LVL2 : edge_to_pulse
+
+
+      AUTO_LVL2 : edge_to_pulse
         port map (
-          clock  => CLK,
-          en_clk => '1',
+          clock     => CLK,
+          en_clk    => '1',
           signal_in => not_lvl1_busy_opt,
-          pulse  => lvl2_trigger_i);
-        
-    LVL2_TAG_COUNT: up_down_counter
+          pulse     => lvl2_trigger_i);
+
+      LVL2_TAG_COUNT : up_down_counter
         generic map (
           NUMBER_OF_BITS => 8)
         port map (
@@ -2701,167 +2750,167 @@ begin
           COUNT_OUT => lvl2_trigger_tag_i(7 downto 0),
           UP_IN     => lvl2_trigger_i,
           DOWN_IN   => '0');
-      
+
       lvl2_trigger_code_i(3) <= '0';
       
-      end generate SUB_SYSTEM_SELECT;
+    end generate SUB_SYSTEM_SELECT;
 
   end generate CTU_DTU_OPT_EN;
 
 -----------------------------------------------------------------------------
 -- tlk interface
 -----------------------------------------------------------------------------
-  
-  TLK_ISE: if DTU_ENABLE=0 and TRBV2_TYPE < 4 and TRBNET_ENABLE = 0 generate
-    TLK_TX_ER  <= '0';
-    SFP_TX_DIS   <= '0';--fpga_register_06_i(15);
-    TLK_LOOPEN  <= '0';
-    TLK_LCKREFN <= '1';
-    TLK_ENABLE  <= '1';
-    TLK_PRBSEN  <= '0';
-    cv_i <= x"f" & "110" &  TLK_RX_ER;
-    TLK_TX_EN <= tx_k_i(0);
-  --  TLK_TX_EN <= ;
+
+  TLK_ISE : if DTU_ENABLE = 0 and TRBV2_TYPE < 4 and TRBNET_ENABLE = 0 generate
+    TLK_TX_ER       <= '0';
+    SFP_TX_DIS      <= '0';             --fpga_register_06_i(15);
+    TLK_LOOPEN      <= '0';
+    TLK_LCKREFN     <= '1';
+    TLK_ENABLE      <= '1';
+    TLK_PRBSEN      <= '0';
+    cv_i            <= x"f" & "110" & TLK_RX_ER;
+    TLK_TX_EN       <= tx_k_i(0);
+    --  TLK_TX_EN <= ;
     sfp_los_vect(0) <= SFP_LOS;
-    rx_k_i <= x"0" & "000" & TLK_RX_DV;
-    tlk_rxd_i <= x"000000000000" &  TLK_RXD;
-    TLK_TXD <= tlk_txd_i(15 downto 0);
-    
-    TLK_RX_CLK_BUFR: BUFR
+    rx_k_i          <= x"0" & "000" & TLK_RX_DV;
+    tlk_rxd_i       <= x"000000000000" & TLK_RXD;
+    TLK_TXD         <= tlk_txd_i(15 downto 0);
+
+    TLK_RX_CLK_BUFR : BUFR
       port map(
-        CE => '1',
+        CE  => '1',
         CLR => '0',
-        I => TLK_RX_CLK,
-        O => tlk_rx_clk_r(0)
+        I   => TLK_RX_CLK,
+        O   => tlk_rx_clk_r(0)
         );
 
-    TLK_CLK_BUFR: BUFR
+    TLK_CLK_BUFR : BUFR
       port map(
-        CE => '1',
+        CE  => '1',
         CLR => '0',
-        I => TLK_CLK,
-        O => tlk_clk_r(0)
+        I   => TLK_CLK,
+        O   => tlk_clk_r(0)
         );
-    
-    TLK_INTERFACE_INST: media_interface
+
+    TLK_INTERFACE_INST : media_interface
       generic map (
-          HOW_MANY_CHANNELS => HOW_MANY_CHANNELS,
-          SYSTEM            => 6
-          )
+        HOW_MANY_CHANNELS => HOW_MANY_CHANNELS,
+        SYSTEM            => 6
+        )
       port map (
-          RESET              => reset_i,
-          SYSTEM_CLK         => CLK,
-          TX_CLK             => tlk_clk_r,
-          RX_CLK             => tlk_rx_clk_r,
-          RXD                => tlk_rxd_i,
-          RX_K               => rx_k_i,
-          RX_RST             => open,
-          CV                 => cv_i,
-          TXD                => tlk_txd_i,
-          TX_K               => tx_k_i,
-          MEDIA_STATUS       => media_status_i,
-          MEDIA_CONTROL      => media_control_i,
-          MED_DATAREADY_IN   => med_dataready_in_i,
-          MED_DATA_IN        => x"0000",--med_data_in_i,
-          MED_READ_OUT       => open,--med_read_out_i,
-          MED_DATA_OUT       => open,--med_data_out_i,
-          MED_DATAREADY_OUT  => open,--med_dataready_out_i,
-          MED_READ_IN        => med_read_in_i,
-          MED_PACKET_NUM_IN  => med_packet_num_in_i,
-          MED_PACKET_NUM_OUT => med_packet_num_out_i,
-          MED_STAT_OP        => med_stat_op_in_i,
-          MED_CTRL_OP        => med_ctrl_op_out_i,
-          LINK_DEBUG         => link_debug_i,
-          TX_DIS             => open,
-          SFP_INP_N          => x"00",
-          SFP_INP_P          => x"00",
-          SFP_OUT_N          => open,
-          SFP_OUT_P          => open
-          );
-    
-    DGOOD <= med_stat_op_in_i(9);
-    media_status_i(0) <= sfp_los_vect(0);
+        RESET              => reset_i,
+        SYSTEM_CLK         => CLK,
+        TX_CLK             => tlk_clk_r,
+        RX_CLK             => tlk_rx_clk_r,
+        RXD                => tlk_rxd_i,
+        RX_K               => rx_k_i,
+        RX_RST             => open,
+        CV                 => cv_i,
+        TXD                => tlk_txd_i,
+        TX_K               => tx_k_i,
+        MEDIA_STATUS       => media_status_i,
+        MEDIA_CONTROL      => media_control_i,
+        MED_DATAREADY_IN   => med_dataready_in_i,
+        MED_DATA_IN        => x"0000",  --med_data_in_i,
+        MED_READ_OUT       => open,     --med_read_out_i,
+        MED_DATA_OUT       => open,     --med_data_out_i,
+        MED_DATAREADY_OUT  => open,     --med_dataready_out_i,
+        MED_READ_IN        => med_read_in_i,
+        MED_PACKET_NUM_IN  => med_packet_num_in_i,
+        MED_PACKET_NUM_OUT => med_packet_num_out_i,
+        MED_STAT_OP        => med_stat_op_in_i,
+        MED_CTRL_OP        => med_ctrl_op_out_i,
+        LINK_DEBUG         => link_debug_i,
+        TX_DIS             => open,
+        SFP_INP_N          => x"00",
+        SFP_INP_P          => x"00",
+        SFP_OUT_N          => open,
+        SFP_OUT_P          => open
+        );
+
+    DGOOD                           <= med_stat_op_in_i(9);
+    media_status_i(0)               <= sfp_los_vect(0);
     fpga_register_0b_i(15 downto 0) <= media_status_i;
-    fpga_register_0d_i <= link_debug_i;
+    fpga_register_0d_i              <= link_debug_i;
   end generate TLK_ISE;
 
-  
+
 -------------------------------------------------------------------------------
 -- dtu - there has to be an GP-AddOn with correct configuration see GP_AddOn
 -- directory (not available now). Old HADES bus saved for any case.
 -------------------------------------------------------------------------------
-    DTU_INT_ENABLE: if DTU_ENABLE = 1 generate
-      DTU_INT: dtu_interface
-          port map (
-              CLK                   => CLK,
-              RESET                 => reset_i,
-              LVL1_TRIGGER_BUS      => ADO_TTL(0),
-              LVL1_DATA_TRIGGER_BUS => ADO_TTL(1),
-              LVL1_DATA_BUS         => ADO_TTL(5 downto 2),
-              LVL1_ERROR_BUS        => open,
-              LVL1_BUSY_BUS         => ADO_TTL(7),
-              LVL1_TRIGGER          => lvl1_trigger_i,
-              LVL1_CODE             => lvl1_trigger_code_i,
-              LVL1_TAG              => lvl1_trigger_tag_i(7 downto 0),
-              LVL1_BUSY             => lvl1_busy_i,--'0',
-              LVL2_TRIGGER_BUS      => ADO_TTL(8),
-              LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
-              LVL2_DATA_BUS         => ADO_TTL(13 downto 10),
-              LVL2_ERROR_BUS        => open,
-              LVL2_BUSY_BUS         => ADO_TTL(15),
-              LVL2_TRIGGER          => lvl2_trigger_i,
-              LVL2_CODE             => lvl2_trigger_code_i,
-              LVL2_TAG              => lvl2_trigger_tag_i(7 downto 0),
-              LVL2_BUSY             => lvl2_busy_i,
-              LVL2_TRB_ACK          => lvl2_readout_completed_i,--lvl2_trb_ack_i,
-              DTU_DEBUG_00          => dtu_debug_00_i);
+  DTU_INT_ENABLE : if DTU_ENABLE = 1 generate
+    DTU_INT : dtu_interface
+      port map (
+        CLK                   => CLK,
+        RESET                 => reset_i,
+        LVL1_TRIGGER_BUS      => ADO_TTL(0),
+        LVL1_DATA_TRIGGER_BUS => ADO_TTL(1),
+        LVL1_DATA_BUS         => ADO_TTL(5 downto 2),
+        LVL1_ERROR_BUS        => open,
+        LVL1_BUSY_BUS         => ADO_TTL(7),
+        LVL1_TRIGGER          => lvl1_trigger_i,
+        LVL1_CODE             => lvl1_trigger_code_i,
+        LVL1_TAG              => lvl1_trigger_tag_i(7 downto 0),
+        LVL1_BUSY             => lvl1_busy_i,               --'0',
+        LVL2_TRIGGER_BUS      => ADO_TTL(8),
+        LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
+        LVL2_DATA_BUS         => ADO_TTL(13 downto 10),
+        LVL2_ERROR_BUS        => open,
+        LVL2_BUSY_BUS         => ADO_TTL(15),
+        LVL2_TRIGGER          => lvl2_trigger_i,
+        LVL2_CODE             => lvl2_trigger_code_i,
+        LVL2_TAG              => lvl2_trigger_tag_i(7 downto 0),
+        LVL2_BUSY             => lvl2_busy_i,
+        LVL2_TRB_ACK          => lvl2_readout_completed_i,  --lvl2_trb_ack_i,
+        DTU_DEBUG_00          => dtu_debug_00_i);
     --   ADO_TTL(7) <= lvl1_busy_i;
-    ADO_TTL(5 downto 0) <= (others => 'Z');
+    ADO_TTL(5 downto 0)  <= (others => 'Z');
     ADO_TTL(13 downto 8) <= (others => 'Z');
-    ADO_TTL(34) <= '1';
-    ADO_TTL(33) <= '0';
-    end generate DTU_INT_ENABLE;
+    ADO_TTL(34)          <= '1';
+    ADO_TTL(33)          <= '0';
+  end generate DTU_INT_ENABLE;
 
 -------------------------------------------------------------------------------
 -- ctu - there has to be an GP-AddOn with correct configuration see GP_AddOn
 -- directory (not available now). Old HADES bus Saved for any case.
 -------------------------------------------------------------------------------
-    CTU_INT_ENABLE: if CTU_ENABLE = 1 generate
-      lvl2_trigger_code_i(3) <= '0';
-      ADO_TTL(15 downto 0) <= (others => 'Z');
+  CTU_INT_ENABLE : if CTU_ENABLE = 1 generate
+    lvl2_trigger_code_i(3) <= '0';
+    ADO_TTL(15 downto 0)   <= (others => 'Z');
+
+    CTU_INT : ctu
+      port map (
+        CLK              => CLK,
+        RESET            => reset_i,
+        LVL1_TRIGG       => ADO_TTL(7 downto 0),
+        LVL1_START       => lvl1_trigger_i,
+        LVL1_TAG         => lvl1_trigger_tag_i(7 downto 0),
+        LVL1_CODE        => lvl1_trigger_code_i,
+        LVL1_BUSY        => lvl1_busy_i,
+        LVL2_TRIGG       => "00",       --MU
+        LVL2_START       => open,       --lvl2_trigger_i, chang to one bit ?
+        LVL2_TAG         => open,
+        LVL2_BUSY        => lvl2_busy_i,
+        LVL2_DOWNSCALING => fpga_register_06_i(15 downto 8),
+        CTU_CONTROL      => x"00000000",  --x"0000" & fpga_register_06_i(15 downto 0),  --26
+        LVL1_CTU_STATUS  => lvl1_ctu_status_i,
+        LVL2_CTU_STATUS  => lvl2_ctu_status_i);
+  end generate CTU_INT_ENABLE;
 
-      CTU_INT: ctu
-        port map (
-            CLK              => CLK,
-            RESET            => reset_i,
-            LVL1_TRIGG       => ADO_TTL(7 downto 0),
-            LVL1_START       => lvl1_trigger_i,
-            LVL1_TAG         => lvl1_trigger_tag_i(7 downto 0),
-            LVL1_CODE        => lvl1_trigger_code_i,
-            LVL1_BUSY        => lvl1_busy_i,
-            LVL2_TRIGG       => "00",     --MU
-            LVL2_START       => open,--lvl2_trigger_i, chang to one bit ?
-            LVL2_TAG         => open,
-            LVL2_BUSY        => lvl2_busy_i,
-            LVL2_DOWNSCALING => fpga_register_06_i(15 downto 8),
-            CTU_CONTROL      => x"00000000",--x"0000" & fpga_register_06_i(15 downto 0),  --26
-            LVL1_CTU_STATUS  => lvl1_ctu_status_i,
-            LVL2_CTU_STATUS  => lvl2_ctu_status_i);
-    end generate CTU_INT_ENABLE;
 
-  
 --------------------------------------------------------------------------
 -- scalers - there has to be an GP-AddOn with correct configuration see GP_AddOn
 -- directory (not available now).
 -------------------------------------------------------------------------
-  SCALERS_ON_TTL_ENABLE: if SCALERS_ENABLE = 1 generate
-    SCALER: for ttl_line in 0 to 7 generate
+  SCALERS_ON_TTL_ENABLE : if SCALERS_ENABLE = 1 generate
+    SCALER : for ttl_line in 0 to 7 generate
       PULSE_TO_EDGE : edge_to_pulse
         port map (
-          clock  => CLK,
-          en_clk => '1',
+          clock     => CLK,
+          en_clk    => '1',
           signal_in => ADO_TTL(ttl_line),
-          pulse  => scaler_pulse(ttl_line));
+          pulse     => scaler_pulse(ttl_line));
       SCALER : simpleupcounter_32bit
         port map (
           QOUT => scaler_counter(ttl_line),
@@ -2869,18 +2918,18 @@ begin
           CLK  => CLK,
           CLR  => reset_i);
     end generate SCALER;
-    ADO_TTL(7 downto 0) <=  (others => 'Z');
+    ADO_TTL(7 downto 0) <= (others => 'Z');
   end generate SCALERS_ON_TTL_ENABLE;
 
-  
+
 --------------------------------------------------------------------------
 -- others --simple test for clock quality (osciloscope)
 --------------------------------------------------------------------------
 
-  COUNTER_FOR_CLOCK_CHECK: process (CLK, reset_i)
-  begin 
-    if rising_edge(CLK) then  
-      if reset_i = '1' then              
+  COUNTER_FOR_CLOCK_CHECK : process (CLK, reset_i)
+  begin
+    if rising_edge(CLK) then
+      if reset_i = '1' then
         check_counter <= (others => '0');
       else
         check_counter <= check_counter + 1;

diff --git a/trb_v2b_fpga_syn.prj b/trb_v2b_fpga_syn.prj
index b20bb6a3a10c63288190684712085bb309d7fc28..919adb1b12cfe06ce22b0194824b6dff148e3b9a 100644 (file)
--- a/trb_v2b_fpga_syn.prj
+++ b/trb_v2b_fpga_syn.prj
@@ -6,10 +6,8 @@
 #$$$$$$$$$$$$$$$$$$$$$$$$$$$$sfp temp and opt power$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#
 
 
+#add_file -vhdl -lib work "sfp_interface.vhd"
 add_file -vhdl -lib work "sfp_interface.vhd"
-#add_file -vhdl -lib work "bit_controller.vhd" 
-#add_file -vhdl -lib work "byte_ctrl.vhd"
-#add_file -vhdl -lib work "cahit_divider.vhd"
 
 #$$$$$$$$$$$$$$$$$$$$$$$$$$$$trb$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#