use warnings;
use strict;
use Term::ANSIColor;
-
+use File::stat;
+use POSIX;
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64';
-#my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
-#my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
-#my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
-my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
+my $BasePath = "../base/"; #path to "base" directory
+my $CbmNetPath = "../../cbmnet";
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-
-
+my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64';
+my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/';
+###################################################################################
+system("./compile_constraints.pl");
+symlink($CbmNetPath, '../cbmnet/cbmnet') unless (-e '../cbmnet/cbmnet');
use FileHandle;
$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
my $FAMILYNAME="LatticeECP3";
my $DEVICENAME="LFE3-150EA";
my $PACKAGE="FPBGA1156";
my $SPEEDGRADE="8";
-system("./compile_constraints.pl");
-
-system("ln -f -s config_default.vhd config.vhd");
-
-if(defined $ENV{'LPF_ONLY'} and $ENV{'LPF_ONLY'} == 1) {exit;}
+#create full lpf file
#set -e
#set -o errexit
#generate timestamp
-my $t=sprintf "%08x", time;
+my $t=time;
my $fh = new FileHandle(">version.vhd");
die "could not open file" if (! defined $fh);
print $fh <<EOF;
package version is
- constant VERSION_NUMBER_TIME : integer := 16#$t#;
-
+ constant VERSION_NUMBER_TIME : integer := $t;
+
end package version;
EOF
$fh->close;
my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
$r=execute($c, "do_not_exit" );
-
chdir "workdir";
+
$fh = new FileHandle("<$TOPNAME".".srr");
my @a = <$fh>;
$fh -> close;
{
if(/\@E:/)
{
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
+ print "\n";
+ $c="cat $TOPNAME.srr | grep \"\@E\"";
+ system($c);
print "\n\n";
- exit 129;
+ exit 129;
}
}
$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
execute($c);
$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+$c=qq'$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd" | grep -v -e "^WARNING.*has no load"';
execute($c);
my $tpmap = $TOPNAME . "_map" ;
-system("mv $TOPNAME.ncd guidefile.ncd");
-# $c=qq|$lattice_path/ispfpga/bin/lin/map -g guidefile.ncd -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
execute($c);
+system("rm $TOPNAME.ncd");
-# $c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|;
$c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
execute($c);
# IOR IO Timing Report
$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#execute($c);
+execute($c);
# TWR Timing Report
$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
chdir "..";
-exit;
sub execute {
my ($c, $op) = @_;
print color 'reset';
$r=system($c);
if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
+ print "$!";
+ if($op ne "do_not_exit") {
+ wait;
+ }
}
return $r;
}
+
chdir($workdir);
system ("$back/../../base/linkdesignfiles.sh '$back'");
+symlink "$back/../../base/cores/cbmnet_sfp1.txt", 'cbmnet_sfp1.txt';
chdir($script_dir);
system ("ln -sfT $back/../tdc_release/Adder_304.ngo $workdir/Adder_304.ngo");
system("cp ../base/trb3_central_cts.lpf $workdir/$TOPNAME.lpf");
-system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf");
+# system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf");
system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf");
system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' $workdir/$TOPNAME.lpf");
------------------------------------------------------------------------------
constant INCLUDE_CTS : integer range c_NO to c_YES := c_YES;
- constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_NO;
+ constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_YES;
--include TDC for all four trigger input lines
constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET);
- constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
+ constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_CBMNET;
------------------------------------------------------------------------------
--End of configuration
------------------------------------------------------------------------------
--Hub configuration
------------------------------------------------------------------------------
- type hub_mii_t is array(0 to 1) of integer;
+
+
+ type hub_mii_t is array(0 to 2) of integer;
type hub_ct is array(0 to 16) of integer;
- type hub_cfg_t is array(0 to 1) of hub_ct;
- type hw_info_t is array(0 to 1) of std_logic_vector(31 downto 0);
+ type hub_cfg_t is array(0 to 2) of hub_ct;
+ type hw_info_t is array(0 to 2) of std_logic_vector(31 downto 0);
--this is used to select the proper configuration in the main code
constant CFG_MODE : integer;
--first entry is normal CTS with one optical output, second one is with four optical outputs
--slow-control is accepted on SFP1 only, triggers are sent to all used SFP
- constant INTERNAL_NUM_ARR : hub_mii_t := (5,5);
- constant INTERFACE_NUM_ARR : hub_mii_t := (5,8);
+ constant INTERNAL_NUM_ARR : hub_mii_t := (5,5,5);
+ constant INTERFACE_NUM_ARR : hub_mii_t := (5,8,5);
constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0));
+ (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0),
+ (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0));
constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
- (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0));
+ (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0),
+ (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0));
constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0));
- constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0",x"9000CEE2");
+ (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0));
+ constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0", x"9000CEE2", x"9000CEE0"); -- TODO: Adopt for CBMNet
constant INTERNAL_NUM : integer;
constant INTERFACE_NUM : integer;
package body config is
--compute correct configuration mode
- constant CFG_MODE : integer := USE_4_SFP;
+ constant CFG_MODE : integer := 2*INCLUDE_CBMNET+USE_4_SFP;
constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC;
constant HARDWARE_INFO : std_logic_vector (31 downto 0) := HARDWARE_INFO_ARR(INCLUDE_TDC);
- constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE);
+ constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE); -- TODO: what's that ?
constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
-end package body;
+end package body;
\ No newline at end of file
entity cbmnet_dlm_etm is
- generic (
- DLM_NUM : integer range 1 to 15 := 10
- );
-
port(
CLK : in std_logic; -- e.g. 100 MHz
RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state
CONTROL_REG_IN : in std_logic_vector(31 downto 0);
STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
HEADER_REG_OUT : out std_logic_vector(1 downto 0);
- DEBUG : out std_logic_vector(31 downto 0)
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end entity;
signal cbm_dlm_counter_i : unsigned(31 downto 0);
signal cbm_filtered_dlm_counter_i : unsigned(31 downto 0);
signal cbm_ignore_resets_threshold_i : unsigned(31 downto 0);
+ signal cbm_listing_dlm_num_i : std_logic_vector(3 downto 0);
signal trb_fine_grain_counter_i : unsigned(31 downto 0);
signal trb_dlm_counter_i : unsigned(31 downto 0);
signal rdo_index_i : integer range 0 to 3;
signal rdo_disable_i : std_logic;
+
begin
-- TrbNet sync
trb_fine_grain_counter_i <= cbm_fine_grain_counter_i when rising_edge(CLK);
trb_dlm_counter_i <= cbm_dlm_counter_i when rising_edge(CLK);
trb_ignore_resets_threshold_i <= UNSIGNED(x"00" & CONTROL_REG_IN(23 downto 0)) when rising_edge(CLK);
- STATUS_REG_OUT <= x"00" & trb_fine_grain_counter_i(31 downto 24) & trb_filtered_dlm_counter_i(15 downto 0) when rising_edge(CLK);
+ STATUS_REG_OUT <= x"00" & STD_LOGIC_VECTOR(trb_fine_grain_counter_i(31 downto 24)) & STD_LOGIC_VECTOR(trb_filtered_dlm_counter_i(15 downto 0)) when rising_edge(CLK);
+ TRG_SYNC_OUT <= '1' when trb_fine_grain_counter_i < 4 else '0';
+
-- TrbNet readout
rdo_disable_i <= CONTROL_REG_IN(0);
HEADER_REG_OUT <= "10"; -- send four data words (3 not supported w/o header)
- DATA_OUT <= rdo_buffer_i(rdo_index_i);
+-- DATA_OUT <= rdo_buffer_i(rdo_index_i);
PROC_RDO: process is
begin
begin
wait until rising_edge(CBMNET_CLK_IN);
- if CBMNET_DLM_REC_IN = STD_LOGIC_VECTOR(TO_UNSIGNED(DLM_NUM, 4)) and CBMNET_DLM_REC_VALID_IN = '1' then
+ if CBMNET_DLM_REC_IN = cbm_listing_dlm_num_i and CBMNET_DLM_REC_VALID_IN = '1' then
if cbm_fine_grain_counter_i >= cbm_ignore_resets_threshold_i then
cbm_fine_grain_counter_i <= (others => '0');
cbm_filtered_dlm_counter_i <= cbm_filtered_dlm_counter_i + 1;
cbm_dlm_counter_i <= cbm_dlm_counter_i + 1;
end if;
end process;
+
+ cbm_listing_dlm_num_i <= CONTROL_REG_IN(7 downto 4) when rising_edge(CBMNET_CLK_IN);
end architecture;
set_option -top_module "trb3_central"
set_option -resource_sharing true
+
+
+# Lattice XP
+set_option -maxfan 100
+set_option -fix_gated_and_generated_clocks 1
+#set_option -RWCheckOnRam 1
+#set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+
+
# map options
set_option -frequency 200
set_option -fanout_limit 100
set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
set_option -force_gsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -write_vhdl 1
# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
+set_option -write_apr_constraint 1
# set result format/file last
project -result_format "edif"
####################
+add_file -fpga_constraint "./trb3_central_syn.fdc"
+
#add_file options
add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v"
add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v"
- add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd"
- add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_rx_gear.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_tx_gear.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3.vhd"
-
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_fifo.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_tx_fsm.vhd"
- add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout.vhd"
+add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd"
+add_file -vhdl -lib work "../cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_rx_gear.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_tx_gear.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_trbnet_decoder.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_event_packer.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_fifo.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_tx_fsm.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout.vhd"
}
signal cbm_rdo_regio_dataready_i : std_logic;
signal cbm_rdo_regio_write_ack_i : std_logic;
signal cbm_rdo_regio_unknown_addr_i : std_logic;
+
+ signal cbm_phy_regio_addr_i : std_logic_vector(15 downto 0);
+ signal cbm_phy_regio_data_status_i : std_logic_vector(31 downto 0);
+ signal cbm_phy_regio_read_enable_i : std_logic;
+ signal cbm_phy_regio_write_enable_i : std_logic;
+ signal cbm_phy_regio_data_ctrl_i : std_logic_vector(31 downto 0);
+ signal cbm_phy_regio_dataready_i : std_logic;
+ signal cbm_phy_regio_write_ack_i : std_logic;
+ signal cbm_phy_regio_unknown_addr_i : std_logic;
+
+ signal reset_fifo_i : std_logic_vector(3 downto 0) := (others => '0');
+
+ signal cbm_phy_debug : std_logic_vector(511 downto 0);
+
begin
+ assert not(USE_4_SFP = c_YES and INCLUDE_CBMNET = c_YES) report "CBMNET uses SFPs 1-4 and hence does not support USE_4_SFP" severity failure;
+ assert not(INCLUDE_CBMNET = c_YES and INCLUDE_CTS = c_NO) report "CBMNET is supported only with CTS included" severity failure;
+
+
-- MBS Module
gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_CTS = c_YES generate
THE_MBS: entity work.mbs_vulom_recv
end generate;
-- CBMNet ETM
- gen_cbmnet_etm: if (ETM_CHOICE_CBMNET = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) generate
- assert(INCLUDE_CBMNET = c_YES) report "CBMNET DLM ETM requires the CBMNET stack (INCLUDE_CBMNET = c_YES)" severity failure;
+ gen_cbmnet_etm: if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) generate
+ --assert(INCLUDE_CBMNET = c_YES or not( ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES)) report "CBMNET DLM ETM requires the CBMNET stack (INCLUDE_CBMNET = c_YES)" severity failure;
THE_CBMNET_ETM: entity work.cbmnet_dlm_etm
- generic map (DLM_NUM => 10)
+-- generic map (DLM_NUM => 10)
port map (
CLK => clk_100_i,
RESET_IN => reset_i,
--Registers / Debug
CONTROL_REG_IN => cts_ext_control,
STATUS_REG_OUT => cts_ext_status,
- HEADER_REG_OUT => cts_ext_header,
+ HEADER_REG_OUT => cts_ext_header
- DEBUG => cts_ext_debug
+-- DEBUG => cts_ext_debug
);
end generate;
& FPGA1_COMM(10 downto 6);
JOUT1 <= cts_output_multiplexers_i(3 downto 0);
- JOUT2 <= cts_output_multiplexers_i(7 downto 4);
+ --JOUT2 <= cts_output_multiplexers_i(7 downto 4);
JOUTLVDS <= cts_output_multiplexers_i(7 downto 0);
--LED_BANK <= cts_output_multiplexers_i(7 downto 0);
end generate;
-- Status and control port
STAT_OP => open,
CTRL_OP => open,
- DEBUG_OUT => open
+ DEBUG_OUT => cbm_phy_debug
);
+ proc_debug_regio: process is
+ variable addr : integer range 0 to 15;
+ begin
+ wait until rising_edge(clk_100_i);
+ addr := to_integer(unsigned(cbm_phy_regio_addr_i(3 downto 0)));
+ cbm_phy_regio_data_status_i <= cbm_phy_debug(addr*32+31 downto addr*32);
+ cbm_phy_regio_dataready_i <= cbm_phy_regio_read_enable_i;
+ cbm_phy_regio_unknown_addr_i <= '0';
+ cbm_phy_regio_write_ack_i <= '0';
+ end process;
+
THE_CBM_ENDPOINT: lp_top
generic map (
NUM_LANES => 1,
dlm2send_va => cbm_dlm2send_va_i,
dlm2send => cbm_dlm2send_i,
- dlm_rec_type => cbm_dlm_rec_type_i,
- dlm_rec_va => cbm_dlm_rec_va_i,
+ dlm_rec_type => cbm_dlm_ref_rec_type_i,
+ dlm_rec_va => cbm_dlm_ref_rec_va_i,
data_rec => cbm_data_rec_i,
data_rec_start => cbm_data_rec_start_i,
cbm_crc_error_cntr_clr_i <= cbm_reset_i;
cbm_retrans_cntr_clr_i <= cbm_reset_i;
cbm_retrans_error_cntr_clr_i <= cbm_reset_i;
-
THE_DLM_REFLECT: dlm_reflect
port map (
dlm2send => cbm_dlm2send_i -- out std_logic_vector(3 downto 0)
);
+ -- TODO: just borrowed from CTS ... !
+ JOUT2 <= "0" & clk_100_i & cbm_dlm2send_va_i & cbm_clk_i;
+
THE_CBMNET_READOUT: cbmnet_readout
port map(
-- TrbNet
CBMNET_DATA2SEND_END_OUT => cbm_data2send_end_i(0), -- out std_logic;
CBMNET_DATA2SEND_DATA_OUT => cbm_data2send_i -- out std_logic_vector(15 downto 0)
);
+
+ trb_reset_in <= reset_via_gbe; -- or MED_STAT_OP(4*16+13); --_delayed(2)
+ LED_TRIGGER_GREEN <= not cbm_link_active_i;
+ LED_TRIGGER_RED <= not cbm_dlm_rec_va_i;
+
+ --Internal Connection
+ med_read_in(4) <= '0';
+ med_data_in(79 downto 64) <= (others => '0');
+ med_packet_num_in(14 downto 12) <= (others => '0');
+ med_dataready_in(4) <= '0';
+ med_stat_op(79 downto 64) <= (others => '0');
+ med_stat_debug(4*64+63 downto 4*64) <= (others => '0');
+
+ SFP_TXDIS(7 downto 2) <= (others => '1');
end generate;
GEN_NO_CBMNET: if INCLUDE_CBMNET = c_NO generate
hub_cts_status_bits <= gbe_cts_status_bits;
hub_cts_readout_finished <= gbe_cts_readout_finished;
hub_fee_read <= gbe_fee_read;
+
+ trb_reset_in <= reset_via_gbe or MED_STAT_OP(4*16+13); --_delayed(2)
+ LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
+ LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
end generate;
DEBUG_OUT => open
);
-trb_reset_in <= reset_via_gbe or MED_STAT_OP(4*16+13); --_delayed(2)
-reset_i <= reset_i_temp; -- or trb_reset_in;
+
+reset_fifo_i <= reset_i_temp & reset_fifo_i(reset_fifo_i'high downto 1) when rising_edge(clk_100_i);
+reset_i <= reset_fifo_i(0) when rising_edge(clk_100_i);
+-- reset_i <= reset_i_temp; -- or trb_reset_in;
process begin
wait until rising_edge(clk_100_i);
STAT_DEBUG => open,
CTRL_DEBUG => (others => '0')
);
-
---------------------------------------------------------------------
-- The GbE machine for blasting out data from TRBnet
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 11,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300", 10 => x"c800", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 0, 6 => 7, 7 => 5, 8 => 7, 9 => 7, 10 => 3, others => 0)
+ PORT_NUMBER => 13,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300", 10 => x"c800", 11 => x"a800", 12 => x"a880", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 11, 5 => 0, 6 => 7, 7 => 5, 8 => 7, 9 => 7, 10 => 3, 11 => 7, 12 => 7, others => 0)
)
port map(
CLK => clk_100_i,
BUS_WRITE_ACK_IN(0) => spictrl_ack,
BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
BUS_UNKNOWN_ADDR_IN(0) => '0',
+
--Bus Handler (SPI Memory)
BUS_READ_ENABLE_OUT(1) => spimem_read_en,
BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
BUS_WRITE_ACK_IN(10) => tdc_ctrl_write,
BUS_NO_MORE_DATA_IN(10) => '0',
BUS_UNKNOWN_ADDR_IN(10) => '0',
-
+
+ --CBMNet (read-out)
+ BUS_READ_ENABLE_OUT(11) => cbm_rdo_regio_read_enable_i,
+ BUS_WRITE_ENABLE_OUT(11) => cbm_rdo_regio_write_enable_i,
+ BUS_DATA_OUT(11*32+31 downto 11*32) => cbm_rdo_regio_data_ctrl_i,
+ BUS_ADDR_OUT(11*16+15 downto 11*16) => cbm_rdo_regio_addr_i,
+ BUS_TIMEOUT_OUT(11) => open,
+ BUS_DATA_IN(11*32+31 downto 11*32) => cbm_rdo_regio_data_status_i,
+ BUS_DATAREADY_IN(11) => cbm_rdo_regio_dataready_i,
+ BUS_WRITE_ACK_IN(11) => cbm_rdo_regio_write_ack_i,
+ BUS_NO_MORE_DATA_IN(11) => '0',
+ BUS_UNKNOWN_ADDR_IN(11) => cbm_rdo_regio_unknown_addr_i,
+
+ --CBMNet (phy)
+ BUS_READ_ENABLE_OUT(12) => cbm_phy_regio_read_enable_i,
+ BUS_WRITE_ENABLE_OUT(12) => cbm_phy_regio_write_enable_i,
+ BUS_DATA_OUT(12*32+31 downto 12*32) => cbm_phy_regio_data_ctrl_i,
+ BUS_ADDR_OUT(12*16+15 downto 12*16) => cbm_phy_regio_addr_i,
+ BUS_TIMEOUT_OUT(12) => open,
+ BUS_DATA_IN(12*32+31 downto 12*32) => cbm_phy_regio_data_status_i,
+ BUS_DATAREADY_IN(12) => cbm_phy_regio_dataready_i,
+ BUS_WRITE_ACK_IN(12) => cbm_phy_regio_write_ack_i,
+ BUS_NO_MORE_DATA_IN(12) => '0',
+ BUS_UNKNOWN_ADDR_IN(12) => cbm_phy_regio_unknown_addr_i,
+
STAT_DEBUG => open
);
-PROC_TDC_CTRL_REG : process
- variable pos : integer;
-begin
- wait until rising_edge(clk_100_i);
- pos := to_integer(unsigned(tdc_ctrl_addr))*32;
- tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
- last_tdc_ctrl_read <= tdc_ctrl_read;
- if tdc_ctrl_write = '1' then
- tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
- end if;
-end process;
+
---------------------------------------------------------------------------
-- SPI / Flash
LOGIC_ANALYSER_OUT => tdc_debug,
CONTROL_REG_IN => tdc_ctrl_reg
);
+
+ PROC_TDC_CTRL_REG : process
+ variable pos : integer;
+ begin
+ wait until rising_edge(clk_100_i);
+ pos := to_integer(unsigned(tdc_ctrl_addr))*32;
+ tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
+ last_tdc_ctrl_read <= tdc_ctrl_read;
+ if tdc_ctrl_write = '1' then
+ tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
+ end if;
+ end process;
end generate;
gen_no_TDC : if INCLUDE_TDC = c_NO generate
-- LED_YELLOW <= not med_stat_op(10);
-- LED_ORANGE <= not med_stat_op(11);
-- LED_RED <= '1';
- LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
- LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
LED_GREEN <= debug(0);
-- TEST_LINE(31 downto 0) <= cts_ext_debug;
-end architecture;
+end architecture;
\ No newline at end of file
#################################################################
# Basic Settings
#################################################################
-
- SYSCONFIG MCCLK_FREQ = 20;
-
- FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
- FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz;
- FREQUENCY PORT CLK_GPLL_LEFT 200 MHz;
+SYSCONFIG MCCLK_FREQ=20 ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ;
+FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ;
# FREQUENCY PORT CLK_EXT_3 10 MHz;
# FREQUENCY PORT CLK_EXT_4 10 MHz;
-
+
+
+FREQUENCY NET "GEN_CTS.THE_CTS/cts_trigger_out" 100.0 MHz;
+FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz;
+FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz;
+
#################################################################
# Reset Nets
#################################################################
-GSR_NET NET "GSR_N";
-
+GSR_NET NET "GSR_N";
#################################################################
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ;
-LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ;
-
-MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset_*" 30 ns;
-MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30 ns;
-
-
-REGION "MEDIA_UPLINK" "R92C90" 22 76;
-LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE COMP "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSD_INST" SITE "PCSB" ;
+#LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSC" ;
+LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125.THE_SERDES/PCSD_INST" SITE "PCSC" ;
+MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset_*" 30.000000 ns ;
+MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ;
+REGION "MEDIA_UPLINK" "R92C90" 22 76 DEVSIZE;
+LOCATE UGROUP "gen_four_sfp.THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "gen_single_sfp.THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ;
-
#REGION "MEDIA_ONBOARD" "R90C122" 20 40;
-
-MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
#SPI Interface
REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE;
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-#REGION "REGION_CTS" "R42C2D" 37 57 DEVSIZE;
-# UGROUP "cts_group"
-# BLKNAME THE_CTS;
-# LOCATE UGROUP "cts_group" REGION "REGION_CTS";
-MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20 ns;
-MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20 ns;
-
-# CBMNet
-FREQUENCY NET "gen_cbmnet_THE_CBM_PHY/clk_tx_full_i" 250 MHz ;
-FREQUENCY NET "gen_cbmnet_THE_CBM_PHY/THE_RX_GEAR/clk_125_i_i" 125 MHz ;
-FREQUENCY NET "cbm_clk_i" 125 MHz ;
-
-DEFINE BUS "cbm_rx_data" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[8]";
-DEFINE BUS "cbm_tx_data" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[8]";
-
-PRIORITIZE BUS "cbm_rx_data" 91;
-PRIORITIZE BUS "cbm_tx_data" 90;
+MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20.000000 ns ;
+MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20.000000 ns ;
#TrbNet Hub
REGION "REGION_IOBUF" "R40C40D" 55 75 DEVSIZE;
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
-
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
-
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes.0.MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes.1.MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes.2.MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes.3.MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes.4.MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic.1.gen_logic.gen_select_logic2.HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic.0.gen_logic.gen_select_logic1.HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic.3.gen_logic.gen_select_logic1.HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF2_gen.INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF2_gen.INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
+LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF2_gen.INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ;
#GbE Part
-
#GbE Part
-
-FREQUENCY NET "GBE/serdes_clk_125" 125.000000 MHz ;
-FREQUENCY NET "GBE/CLK_125_OUT_inferred_clock" 125.00 MHz ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_txfullclk" 125.000000 MHz ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ;
-
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/refclkcore" 125.000000 MHz ;
-
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ;
-
-FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz;
-FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz;
-
-
+FREQUENCY NET "GBE/serdes_clk_125" 125.000000 MHz ;
+FREQUENCY NET "GBE/CLK_125_OUT_inferred_clock" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/ff_txfullclk" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/ff_rxfullclk" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/sd_tx_clock" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/sd_rx_clock" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/refclkcore" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ;
+FREQUENCY PORT "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz ;
+FREQUENCY PORT "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz ;
UGROUP "tsmac"
- BLKNAME GBE/imp_gen_MAC
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SGMII_GBE_PCS
- BLKNAME GBE/FRAME_RECEIVER
- BLKNAME GBE/FRAME_TRANSMITTER;
+ BLKNAME GBE/imp_gen.MAC
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS
+ BLKNAME GBE/FRAME_RECEIVER
+ BLKNAME GBE/FRAME_TRANSMITTER;
UGROUP "controllers"
- BLKNAME GBE/MAIN_CONTROL
- BLKNAME GBE/RECEIVE_CONTROLLER
- BLKNAME GBE/TRANSMIT_CONTROLLER;
+ BLKNAME GBE/MAIN_CONTROL
+ BLKNAME GBE/RECEIVE_CONTROLLER
+ BLKNAME GBE/TRANSMIT_CONTROLLER;
UGROUP "gbe_rx_tx"
- BLKNAME GBE/FRAME_CONSTRUCTOR
- BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
- BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR
-# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/PACKET_CONSTRUCTOR
-# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IPU_INTERFACE
- BLKNAME GBE/setup_imp_gen_SETUP;
-
-
-#REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE;
-#REGION "MED0" "R81C30D" 34 40 DEVSIZE;
-#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;
+ BLKNAME GBE/FRAME_CONSTRUCTOR
+ BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
+ BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData.THE_IP_CONFIGURATOR
+ BLKNAME GBE/setup_imp_gen.SETUP;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;
FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ;
-#REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE;
-
-#LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
-#LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;
-
-
-
REGION "MED0" "R69C4D" 35 40 DEVSIZE;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;
FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ;
-#LOCATE UGROUP "tsmac" REGION "MED0" ;
BLOCK JTAGPATHS ;
UGROUP "sd_tx_to_pcs"
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
UGROUP "sd_rx_to_pcs"
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
- BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
+ BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
UGROUP "pcs_tx_to_mac"
- BLKNAME GBE/pcs_tx_en_q
- BLKNAME GBE/pcs_tx_en_qq
- BLKNAME GBE/pcs_tx_er_q
- BLKNAME GBE/pcs_tx_er_qq
- BLKNAME GBE/pcs_txd_q_0
- BLKNAME GBE/pcs_txd_q_1
- BLKNAME GBE/pcs_txd_q_2
- BLKNAME GBE/pcs_txd_q_3
- BLKNAME GBE/pcs_txd_q_4
- BLKNAME GBE/pcs_txd_q_5
- BLKNAME GBE/pcs_txd_q_6
- BLKNAME GBE/pcs_txd_q_7
- BLKNAME GBE/pcs_txd_qq_0
- BLKNAME GBE/pcs_txd_qq_1
- BLKNAME GBE/pcs_txd_qq_2
- BLKNAME GBE/pcs_txd_qq_3
- BLKNAME GBE/pcs_txd_qq_4
- BLKNAME GBE/pcs_txd_qq_5
- BLKNAME GBE/pcs_txd_qq_6
- BLKNAME GBE/pcs_txd_qq_7;
+ BLKNAME GBE/pcs_tx_en_q
+ BLKNAME GBE/pcs_tx_en_qq
+ BLKNAME GBE/pcs_tx_er_q
+ BLKNAME GBE/pcs_tx_er_qq
+ BLKNAME GBE/pcs_txd_q[0]
+ BLKNAME GBE/pcs_txd_q[1]
+ BLKNAME GBE/pcs_txd_q[2]
+ BLKNAME GBE/pcs_txd_q[3]
+ BLKNAME GBE/pcs_txd_q[4]
+ BLKNAME GBE/pcs_txd_q[5]
+ BLKNAME GBE/pcs_txd_q[6]
+ BLKNAME GBE/pcs_txd_q[7]
+ BLKNAME GBE/pcs_txd_qq[0]
+ BLKNAME GBE/pcs_txd_qq[1]
+ BLKNAME GBE/pcs_txd_qq[2]
+ BLKNAME GBE/pcs_txd_qq[3]
+ BLKNAME GBE/pcs_txd_qq[4]
+ BLKNAME GBE/pcs_txd_qq[5]
+ BLKNAME GBE/pcs_txd_qq[6]
+ BLKNAME GBE/pcs_txd_qq[7];
UGROUP "pcs_rx_to_mac"
- BLKNAME GBE/pcs_rx_en_q
- BLKNAME GBE/pcs_rx_en_qq
- BLKNAME GBE/pcs_rx_er_q
- BLKNAME GBE/pcs_rx_er_qq
- BLKNAME GBE/pcs_rxd_q_0
- BLKNAME GBE/pcs_rxd_q_1
- BLKNAME GBE/pcs_rxd_q_2
- BLKNAME GBE/pcs_rxd_q_3
- BLKNAME GBE/pcs_rxd_q_4
- BLKNAME GBE/pcs_rxd_q_5
- BLKNAME GBE/pcs_rxd_q_6
- BLKNAME GBE/pcs_rxd_q_7
- BLKNAME GBE/pcs_rxd_qq_0
- BLKNAME GBE/pcs_rxd_qq_1
- BLKNAME GBE/pcs_rxd_qq_2
- BLKNAME GBE/pcs_rxd_qq_3
- BLKNAME GBE/pcs_rxd_qq_4
- BLKNAME GBE/pcs_rxd_qq_5
- BLKNAME GBE/pcs_rxd_qq_6
- BLKNAME GBE/pcs_rxd_qq_7;
+ BLKNAME GBE/pcs_rx_en_q
+ BLKNAME GBE/pcs_rx_en_qq
+ BLKNAME GBE/pcs_rx_er_q
+ BLKNAME GBE/pcs_rx_er_qq
+ BLKNAME GBE/pcs_rxd_q[0]
+ BLKNAME GBE/pcs_rxd_q[1]
+ BLKNAME GBE/pcs_rxd_q[2]
+ BLKNAME GBE/pcs_rxd_q[3]
+ BLKNAME GBE/pcs_rxd_q[4]
+ BLKNAME GBE/pcs_rxd_q[5]
+ BLKNAME GBE/pcs_rxd_q[6]
+ BLKNAME GBE/pcs_rxd_q[7]
+ BLKNAME GBE/pcs_rxd_qq[0]
+ BLKNAME GBE/pcs_rxd_qq[1]
+ BLKNAME GBE/pcs_rxd_qq[2]
+ BLKNAME GBE/pcs_rxd_qq[3]
+ BLKNAME GBE/pcs_rxd_qq[4]
+ BLKNAME GBE/pcs_rxd_qq[5]
+ BLKNAME GBE/pcs_rxd_qq[6]
+ BLKNAME GBE/pcs_rxd_qq[7];
USE PRIMARY NET "CLK_GPLL_RIGHT_c" ;
FREQUENCY NET "GBE/serdes_rx_clk_c" 125.000000 MHz PAR_ADJ 25.000000 ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ;
-FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ;
+FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ;
+MAXDELAY NET "GBE/pcs_rx_en_q" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rx_er_q" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[0]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[1]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[2]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[3]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[4]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[5]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[6]" 1.500000 nS ;
+MAXDELAY NET "GBE/pcs_rxd_q[7]" 1.500000 nS ;
+DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
+"GBE/pcs_rx_er_q"
+"GBE/pcs_rxd_q_*" ;
+INPUT_SETUP GROUP "RX_GRP"3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;
+PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ;
+PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ;
+PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
+PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ;
+BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;
+BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;
+USE PRIMARY NET "cbm_clk_i" ;
-MAXDELAY NET "GBE/pcs_rx_en_q" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rx_er_q" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_0" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_1" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_2" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_3" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_4" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_5" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_6" 1.5 ns;
-MAXDELAY NET "GBE/pcs_rxd_q_7" 1.5 ns;
+BLOCK PATH FROM CLKNET "CLK_GPLL_RIGHT" TO CLKNET "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c";
+BLOCK PATH FROM CLKNET "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" TO CLKNET "CLK_GPLL_RIGHT";
-DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
- "GBE/pcs_rx_er_q"
- "GBE/pcs_rxd_q_*";
-INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;
-PRIORITIZE NET "GBE/pcs_rx_en_q" 100;
-PRIORITIZE NET "GBE/pcs_rx_er_q" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_0" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_1" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_2" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_3" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_4" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_5" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_6" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_7" 100;
-PRIORITIZE NET "GBE/pcs_rxd_q_0" 100;
-PRIORITIZE NET "GBE/serdes_rx_clk_c" 80;
-BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;
-BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;
+
+# CBMNet
+FREQUENCY NET "cbm_clk_i" 125.000000 MHz ;
+FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUT" 250.0 MHz;
+FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz;
+FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz;
+
+REGION "CBM_PHY" "R102C83D" 13 25 DEVSIZE;
+LOCATE UGROUP "GEN_CBMNET.THE_CBM_PHY/cbmnet_phy_group" REGION "CBM_PHY" ;
+#REGION "CBM_PHY_RX_GEAR" "R102C83D" 13 25 DEVSIZE;
+#LOCATE UGROUP "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/cbmnet_phy_rx_gear" REGION "CBM_PHY_RX_GEAR" ;
+#REGION "CBM_PHY_TX_GEAR" "R102C83D" 13 25 DEVSIZE;
+#LOCATE UGROUP "GEN_CBMNET.THE_CBM_PHY/THE_TX_GEAR/cbmnet_phy_tx_gear" REGION "CBM_PHY_TX_GEAR" ;
+
+LOCATE COMP "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+DEFINE BUS cbm_rx_data
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[0]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[1]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[2]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[3]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[4]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[5]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[6]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[7]"
+ NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[8]";
+DEFINE BUS cbm_tx_data
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[0]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[1]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[2]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[3]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[4]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[5]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[6]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[7]"
+ NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[8]";
+PRIORITIZE BUS "cbm_rx_data" 91 ;
+PRIORITIZE BUS "cbm_tx_data" 90 ;
+
+BLOCK PATH TO CELL "cbm_phy_debug*";
\ No newline at end of file
--- /dev/null
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /d/jspc29/mpenschuck/trb3/cts/trb3_central_syn.fdc
+# Written on Sun Jul 27 13:52:03 2014
+# by Synplify Premier, I-2013.09-SP1 FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8}
+create_clock {n:THE_MAIN_PLL.CLKOP} -period {10}
+create_clock {n:THE_MAIN_PLL.CLKOK} -period {5}
+create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_SERDES.rx_full_clk_ch0} -period {4}
+create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_SERDES.tx_full_clk_ch0} -period {4}
+create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch0} -period {10}
+create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch1} -period {10}
+create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch2} -period {10}
+create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch3} -period {10}
+create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_tx_ch} -period {10}
+create_clock {n:GEN_CTS\.THE_CTS.TIME_REFERENCE_OUT} -period {10}
+create_clock {n:GBE.imp_gen\.serdes_intclk_gen\.PCS_SERDES.clk_int\.SERDES_GBE.rx_full_clk_ch3} -period {4}
+create_clock {p:CLK_GPLL_RIGHT} -period {8}
+
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
+###==== END Registers
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+###==== END "Compile Points"
+
+
+
jspc29 / trb3.git / commitdiff