Update registers in ADC AddOn

diff --git a/tools/adc.pl b/tools/adc.pl
index 1efe4647bec2c0e35b2f66f3a38711c4ae0ae383..5fcca1a269e3339a7e7334d79ca25a07c4a14edf 100755 (executable)
--- a/tools/adc.pl
+++ b/tools/adc.pl
@@ -492,7 +492,7 @@ sub set_optimal_phases {
       print ">>>>>>>>>>>> Warning: No optimal phase found for ADC $adc, guessing 0\n";
       $opt_phase=0;
     }
-    #print "Opt phase: $opt_phase Max length $max_length\n";
+    print "Opt phase: $opt_phase Max length $max_length\n";
 
     # now set them for each ADC
     @adcs = ($adc);             # used by adc_phase

diff --git a/xml-db/database/ADC.xml b/xml-db/database/ADC.xml
index 7228b0a9f63c8d6c77e3e2392c9db14bf585d2af..bd6977b6cb80d07a15d90a3ab1393d9bacaa3cbc 100644 (file)
--- a/xml-db/database/ADC.xml
+++ b/xml-db/database/ADC.xml
@@ -26,7 +26,7 @@
 </group>
   
 <group name="BufferConfig"
-           address="0010"  size="16"  purpose="config" mode="rw" continuous="true">
+           address="0010"  size="16"  purpose="config" mode="rw" continuous="false">
       <description>Configuration of buffer handling</description>
       <register name="BufferDepth" address="0000" >
         <description>Number of samples to be stored in the buffer</description>
@@ -45,11 +45,11 @@
       
       <register name="TriggerSetting" address="0003" >
         <description>Settings of trigger signal generation</description>
-        <field  name="TriggerOffset" start="0"   bits="10"  format="signed" noflag="true" >
+        <field  name="TriggerOffset" start="0"   bits="16"  format="signed" noflag="true" >
           <description>Offset from the calculated baseline that must be reached to generate a trigger signal for the CTS</description>
         </field>
         <field name="TriggerInvert" start="16" bits="1" format="bitmask" noflag="true">
-          <description>Selects positive (unset) or negative (set) signal inputs. If negative is selected, a trigger is generated if the input signal is below the baseline minus the set threshold</description>
+          <description>Selects positive (unset) or negative (set) signal inputs. If negative is selected, a trigger is generated if the input signal is below the baseline plus the set (negative) threshold</description>
         </field>
       </register>
 
@@ -107,6 +107,17 @@
         <field  name="CFDWindow" start="0"   bits="8"  format="unsigned" noflag="true" />
         <field  name="CFDDelay" start="8"   bits="4"  format="unsigned" noflag="true" />
       </register>
+      <register name="BaselineFix" address="000e">
+        <description>Sets a defined reset value of the baseline. If not active, baseline is resetted to 0 or MAX depending on polarity selection of trigger generation.
+          To fix the baseline at this value, BaselineReset</description>
+        <field  name="BaselineFixed" start="31"   bits="1"  format="bitmask" noflag="true" >
+          <description>Do not do baseline calculations, always fix to the reset value.</description>
+        </field>
+        <field  name="BaselineEn" start="30"   bits="1"  format="bitmask" noflag="true" >
+          <description>Enable user supplied reset value for baseline, do not calculate automatically</description>
+        </field>
+        <field  name="BaselineValue" start="0"   bits="29"  format="unsigned" noflag="true" />
+      </register>
 </group>  
 
 <group name="ProcessorConfig" address="0020"  size="12"  purpose="config" mode="rw" continuous="true">