-const char trbnet_version[] = "$Revision: 2.57 $";
+const char trbnet_version[] = "$Revision: 2.58 $";
-#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
#include <unistd.h>
unsigned int trb_debug = 0;
unsigned int trb_lazy = 0;
unsigned int trb_dma = 0;
+FILE* trb_stderr = NULL;
/* Declaration of a TRB-Package */
{
switch ((pkg->H0 & MASK_HEADER_TYPE) >> SHIFT_HEADER_TYPE) {
case HEADER_DAT:
- fprintf(stderr, "H0: 0x%04x --> DATA channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> DATA channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> data0\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> data1\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> data2\n", pkg->F2);
- fprintf(stderr, "F3: 0x%04x --> data3\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> data0\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> data1\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> data2\n", pkg->F2);
+ fprintf(trb_stderr, "F3: 0x%04x --> data3\n", pkg->F3);
break;
case HEADER_HDR:
- fprintf(stderr, "H0: 0x%04x --> HEADER channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> HEADER channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> source address\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> target address\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> length\n", pkg->F2);
- fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n",
+ fprintf(trb_stderr, "F0: 0x%04x --> source address\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> target address\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> length\n", pkg->F2);
+ fprintf(trb_stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n",
pkg->F3,
(pkg->F3 & MASK_SEQNR) >> SHIFT_SEQNR,
(pkg->F3 & MASK_DATATYPE) >> SHIFT_DATATYPE);
break;
case HEADER_EOB:
- fprintf(stderr, "H0: 0x%04x --> EOB channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> EOB channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> checksum\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> reseved\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> data count\n", pkg->F2);
- fprintf(stderr, "F3: 0x%04x --> buffer number\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> checksum\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> reseved\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> data count\n", pkg->F2);
+ fprintf(trb_stderr, "F3: 0x%04x --> buffer number\n", pkg->F3);
break;
case HEADER_TRM:
- fprintf(stderr, "H0: 0x%04x --> TERM channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> TERM channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> checksum\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> statusbits channel\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> statusbits common\n", pkg->F2);
- fprintf(stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n",
+ fprintf(trb_stderr, "F0: 0x%04x --> checksum\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> statusbits channel\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> statusbits common\n", pkg->F2);
+ fprintf(trb_stderr, "F3: 0x%04x --> sequence: 0x%02x datatype: 0x%01x\n",
pkg->F3,
(pkg->F3 & MASK_SEQNR) >> SHIFT_SEQNR,
(pkg->F3 & MASK_DATATYPE) >> SHIFT_DATATYPE);
break;
case HEADER_EXT:
- fprintf(stderr, "H0: 0x%04x --> EXT channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> EXT channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> reserved\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
- fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> reserved\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
+ fprintf(trb_stderr, "F2: 0x%04x --> reserved\n", pkg->F3);
break;
case HEADER_ACK:
- fprintf(stderr, "H0: 0x%04x --> ACK channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> ACK channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> lenght of buffer\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
- fprintf(stderr, "F2: 0x%04x --> buffer number\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> lenght of buffer\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
+ fprintf(trb_stderr, "F2: 0x%04x --> buffer number\n", pkg->F3);
break;
case HEADER_SIG:
- fprintf(stderr, "H0: 0x%04x --> SIGNAL channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> SIGNAL channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> reserved\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
- fprintf(stderr, "F2: 0x%04x --> reserved\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> reserved\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> reserved\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> reserved\n", pkg->F2);
+ fprintf(trb_stderr, "F2: 0x%04x --> reserved\n", pkg->F3);
break;
case HEADER_ILL:
- fprintf(stderr, "H0: 0x%04x --> ILLEGAL channel: %01d reply: %01d\n",
+ fprintf(trb_stderr, "H0: 0x%04x --> ILLEGAL channel: %01d reply: %01d\n",
pkg->H0,
(pkg->H0 & MASK_HEADER_CHANNEL) >> SHIFT_HEADER_CHANNEL,
(pkg->H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY);
- fprintf(stderr, "F0: 0x%04x --> ignore\n", pkg->F0);
- fprintf(stderr, "F1: 0x%04x --> ignore\n", pkg->F1);
- fprintf(stderr, "F2: 0x%04x --> ignore\n", pkg->F2);
- fprintf(stderr, "F2: 0x%04x --> ignore\n", pkg->F3);
+ fprintf(trb_stderr, "F0: 0x%04x --> ignore\n", pkg->F0);
+ fprintf(trb_stderr, "F1: 0x%04x --> ignore\n", pkg->F1);
+ fprintf(trb_stderr, "F2: 0x%04x --> ignore\n", pkg->F2);
+ fprintf(trb_stderr, "F2: 0x%04x --> ignore\n", pkg->F3);
break;
default:
- fprintf(stderr, "INVALID\n");
+ fprintf(trb_stderr, "INVALID\n");
}
}
read32_from_FPGA(fifoAddress, &tmp);
/* DEBUG INFO */
if ((trb_debug > 1) && ((tmp & MASK_FIFO_VALID) != 0)) {
- fprintf(stderr, "FLUSH_FIFO_%03d: 0x%08x\n", counter, tmp);
+ fprintf(trb_stderr, "FLUSH_FIFO_%03d: 0x%08x\n", counter, tmp);
counter++;
}
} while ((tmp & MASK_FIFO_VALID) != 0);
if ((counter % 5) == 0) {
/* New Package begins */
if (trb_debug > 0) {
- fprintf(stderr,
+ fprintf(trb_stderr,
"-------------------------------------------------\n");
}
packageCtr++;
/* DEBUG INFO */
if (trb_debug > 1) {
- fprintf(stderr, "FIFO_%03d: 0x%08x\n",
+ fprintf(trb_stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
} else {
/* DEBUG INFO */
if (trb_debug > 1) {
- fprintf(stderr, "FIFO_%03d: 0x%08x\n",
+ fprintf(trb_stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
/* DEBUG INFO */
if (trb_debug > 1) {
- fprintf(stderr, "FIFO_%03d: 0x%08x\n",
+ fprintf(trb_stderr, "FIFO_%03d: 0x%08x\n",
fifoDebugCtr, *tmp);
}
/* DEBUG INFO */
if (trb_debug > 0) {
TRB_Package_dump(&package);
- fprintf(stderr, "-------------------------------------------------\n");
+ fprintf(trb_stderr, "-------------------------------------------------\n");
}
if (trb_lazy == 0) {
int memfd;
uint32_t *mem = NULL;
+ /* set default stderr */
+ trb_stderr = stderr;
+
/* Set signal mask for blocking */
sigemptyset(&blockSet);
sigaddset(&blockSet, SIGINT);
clrbitsPC(0x30000);
if (unlockPorts() == -1) return -1;
-
+
return 0;
}
/* DEBUG INFO */
if (trb_debug > 1) {
- fprintf(stderr, "Flushing FIFO of channel# %d\n", channel);
+ fprintf(trb_stderr, "Flushing FIFO of channel# %d\n", channel);
}
if (lockPorts() == -1) return -1;
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Build up package and start transfer */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_READ started.\n");
+ fprintf(trb_stderr, "CMD_REGISTER_READ started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_REG_READ, data, dsize);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Tranfer done.\n");
+ fprintf(trb_stderr, "Init_Tranfer done.\n");
}
/* Build up package and start transfer */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_READ_MEM started.\n");
+ fprintf(trb_stderr, "CMD_REGISTER_READ_MEM started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_REG_READ_MEM, data, dsize);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Build up package */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_WRITE started.\n");
+ fprintf(trb_stderr, "CMD_REGISTER_WRITE started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0);
const uint32_t *data,
uint16_t size)
{
+ static const uint16_t blockSize = 128;
uint16_t config;
uint16_t i;
- int status;
+ uint16_t ctr = 0;
+ int status = -1;
trb_errno = TRB_NONE;
config = config | (option == 0 ? 0x8000 : 0x0000);
if (lockPorts() == -1) return -1;
-
- /* Init transfer */
- if (trb_init_transfer(3) == -1) {
- unlockPorts();
- return -1;
- }
-
- /* DEBUG INFO */
- if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
- }
-
- /* Build up package */
- write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
- write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, config);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- for (i = 0; i < size; i++) {
+
+ while (ctr < size) {
+ uint16_t len = (size - ctr) >= blockSize ? blockSize : (size - ctr);
+ /* Init transfer */
+ if (trb_init_transfer(3) == -1) {
+ unlockPorts();
+ return -1;
+ }
+
+ /* DEBUG INFO */
+ if (trb_debug > 0) {
+ fprintf(trb_stderr, "Init_Transfer done.\n");
+ }
+
+ /* Build up package */
+ write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, trb_address);
+ write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
+ if (option == 0) {
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address + ctr);
+ } else {
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, reg_address);
+ }
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, config);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, (data[i] >> 16) & 0xffff);
- write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[i] & 0xffff);
write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ for (i = 0; i < len; i++, ctr++) {
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, (data[ctr] >> 16) & 0xffff);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, data[ctr] & 0xffff);
+ write32_to_FPGA(CHANNEL_3_SENDER_DATA, 0x00000000);
+ }
+ write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
+
+ /* DEBUG INFO */
+ if (trb_debug > 0) {
+ fprintf(trb_stderr, "CMD_REGISTER_WRITE_MEM started %d.\n", len);
+ }
+
+ status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0);
}
- write32_to_FPGA(CHANNEL_3_SENDER_CONTROL, CMD_REGISTER_WRITE_MEM);
-
- /* DEBUG INFO */
- if (trb_debug > 0) {
- fprintf(stderr, "CMD_REGISTER_WRITE_MEM started.\n");
- }
-
- status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0);
-
+
if (unlockPorts() == -1) return -1;
return status;
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Build up package and start transfer */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_READ_UNIQUE_ID started.\n");
+ fprintf(trb_stderr, "CMD_READ_UNIQUE_ID started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_UID, (uint32_t*)data, dsize);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Build up package and start transfer */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_SETADDRESS started.\n");
+ fprintf(trb_stderr, "CMD_SETADDRESS started.\n");
}
status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Prepare IPU channel */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "CMD_IPU_DATA_READ started.\n");
+ fprintf(trb_stderr, "CMD_IPU_DATA_READ started.\n");
}
status = trb_fifo_read(1, FIFO_MODE_IPU_DATA, data, dsize);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Prepare trigger channel */
SHORT_TRANSFER | (uint32_t)(type & 0x0f));
if (trb_debug > 0) {
- fprintf(stderr, "trigger started.\n");
+ fprintf(trb_stderr, "trigger started.\n");
}
/* Check for replay packets (trigger) */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "Init_Transfer done.\n");
+ fprintf(trb_stderr, "Init_Transfer done.\n");
}
/* Prepare trigger channel */
SHORT_TRANSFER | (uint32_t)(type & 0x0f));
if (trb_debug > 0) {
- fprintf(stderr, "trigger started.\n");
+ fprintf(trb_stderr, "trigger started.\n");
}
/* Check for replay packets (slowcontrol) */
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "fpga_register_read started.\n");
+ fprintf(trb_stderr, "fpga_register_read started.\n");
}
read32_from_FPGA(reg_address, value);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "fpga_register_write started.\n");
+ fprintf(trb_stderr, "fpga_register_write started.\n");
}
write32_to_FPGA(reg_address, value);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "network_reset started.\n");
+ fprintf(trb_stderr, "network_reset started.\n");
}
write32_to_FPGA(0x10, 0x0000);
/* DEBUG INFO */
if (trb_debug > 0) {
- fprintf(stderr, "com_reset started.\n");
+ fprintf(trb_stderr, "com_reset started.\n");
}
setbitsPC(0x30000);