CPU_ADDRESS : in STD_LOGIC_VECTOR (11 downto 0);
CPU_INTERRUPT_OUT : out STD_LOGIC_VECTOR ( 7 downto 0);
STAT : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0)
+ CTRL : in std_logic_vector (31 downto 0);
+ API_STAT_IN : in std_logic_vector (2**c_MUX_WIDTH*32-1 downto 0);
+ API_OBUF_STAT_IN : in std_logic_vector (2**c_MUX_WIDTH*32-1 downto 0)
);
end entity;
next_CPU_DATA_OUT <= sender_error(channel_address*32+31 downto channel_address*32);
when x"1F" =>
next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32);
+ when x"20" =>
+ next_CPU_DATA_OUT <= API_STAT_IN(channel_address*32+31 downto channel_address*32);
when x"24" =>
next_CPU_DATA_OUT <= receiver_counter(channel_address*32+31 downto channel_address*32);
when x"30" =>
next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32);
+ when x"31" =>
+ next_CPU_DATA_OUT <= API_OBUF_STAT_IN(channel_address*32+31 downto channel_address*32);
when others =>
- next_CPU_DATA_OUT <= "0001000000000000000" & CTRL(31 downto 19);
+ next_CPU_DATA_OUT <= CTRL;
end case;
-- end if;
end process;
gen_api_connect : for i in 0 to CHANNELS-1 generate
APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32);
- api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8);
--- APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)
--- <= fifo_pci_to_net_dout((c_DATA_WIDTH+c_NUM_WIDTH)*i+c_DATA_WIDTH-1 downto (c_DATA_WIDTH+c_NUM_WIDTH)*i);
--- APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= fifo_pci_to_net_dout;
- sender_status(i*32) <= APL_RUN_IN(i);
+ api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8);
+ sender_status(i*32) <= APL_RUN_IN(i);
--api_status(i*32+10 downto i*32+8) <= APL_TYP_IN;
- next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001"
- and reg_CPU_ADDRESS(7 downto 4) = i
- and reg_CPU_ADDRESS(3 downto 0) = "0000"
- and reg_CPU_WR = '1' else '0';
- APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i);
- fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost
+ next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001"
+ and reg_CPU_ADDRESS(7 downto 4) = i
+ and reg_CPU_ADDRESS(3 downto 0) = "0000"
+ and reg_CPU_WR = '1' else '0';
+ APL_DATAREADY_OUT(i) <= fifo_pci_to_net_valid_read(i);
+ fifo_pci_to_net_read(i) <= APL_READ_IN(i); --NOT CORRECT - last packet may be lost
APL_SHORT_TRANSFER_OUT(i) <= sender_control(i*32+8);
- APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32);
+ APL_ERROR_PATTERN_OUT(i*32+31 downto i*32) <= sender_error(i*32+31 downto i*32);
APL_TARGET_ADDRESS_OUT(i*16+15 downto i*16) <= sender_target(i*32+15 downto i*32);
- APL_READ_OUT(i) <= not fifo_net_to_pci_full(i);
- fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i);
+ APL_READ_OUT(i) <= not fifo_net_to_pci_full(i);
+ fifo_net_to_pci_write(i) <= APL_DATAREADY_IN(i);
end generate;
process(CLK_TRB)
STAT(24) <= fifo_net_to_pci_empty(1);
STAT(25) <= fifo_net_to_pci_read(1);
STAT(26) <= fifo_net_to_pci_write(1);
--- FIFO_NET_TO_PCI: trb_net_fifo_16bit_bram_dualport_fallthrough
--- port map(
--- rd_clk => CLK,
--- wr_clk => CLK_TRB,
--- rd_en => fifo_net_to_pci_read(i),
--- wr_en => fifo_net_to_pci_write(i),
--- rst => RESET,
--- din => fifo_net_to_pci_din(32*i+17 downto 32*i),
--- dout => fifo_net_to_pci_dout(32*i+17 downto 32*i),
--- full => fifo_net_to_pci_full(i),
--- empty => fifo_net_to_pci_empty(i),
--- valid => fifo_net_to_pci_valid_read(i)
--- );
+
FIFO_NET_TO_PCI: trb_net_fifo_16bit_bram_dualport
port map(
read_clock_in => CLK,
empty_out => fifo_pci_to_net_empty(i),
valid_read_out => fifo_pci_to_net_valid_read(i)
);
-
end generate;
end if;
end process;
-
register_slow_dat_addr_input : process(CLK_TRB)
begin
if rising_edge(CLK_TRB) then
component trb_net_med_8bit_slow
generic(
- TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 4 --even values only!
+ TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only!
);
port(
+ -- Misc
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
- INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in STD_LOGIC;
- INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media
- INT_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out STD_LOGIC; -- offered word is read
- MED_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
- --(incl. debugging errorbits)
- MED_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
+ -- Internal direction port (MII)
+ INT_DATAREADY_OUT : out STD_LOGIC;
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_READ_IN : in STD_LOGIC;
+ INT_DATAREADY_IN : in STD_LOGIC;
+ INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_READ_OUT : out STD_LOGIC;
+ -- Media direction port
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
+ MED_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
+ -- Status and control port
STAT: out STD_LOGIC_VECTOR (31 downto 0);
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ --STAT(5 downto 2): Debug bits in
+
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_OP : out std_logic_vector(15 downto 0);
+ CTRL_OP : in std_logic_vector(15 downto 0)
);
end component;
CPU_ADDRESS : in STD_LOGIC_VECTOR (11 downto 0);
CPU_INTERRUPT_OUT : out STD_LOGIC_VECTOR ( 7 downto 0);
STAT : out std_logic_vector (31 downto 0);
- CTRL : in std_logic_vector (31 downto 0)
+ CTRL : in std_logic_vector (31 downto 0);
+ API_STAT_IN : in std_logic_vector (2**c_MUX_WIDTH*32-1 downto 0);
+ API_OBUF_STAT_IN : in std_logic_vector (2**c_MUX_WIDTH*32-1 downto 0)
);
end component;
STAT_GEN : out std_logic_vector (31 downto 0);
STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
CTRL_GEN : in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0)
+ STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
);
end component;
signal RESET_i : std_logic;
signal RESET_CNT : std_logic_vector(1 downto 0);
signal counter : std_logic_vector(12 downto 0);
+ signal MED_STAT_OP : std_logic_vector(15 downto 0);
+ signal MED_CTRL_OP : std_logic_vector(15 downto 0);
+ signal API_STAT_IN : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0);
+ signal STAT_INIT_OBUF_DEBUG : std_logic_vector(32*2**c_MUX_WIDTH-1 downto 0);
+
begin
CLK_EN <= '1';
APL_MY_ADDRESS_IN <= x"FF09";
INT_DATA_OUT => MED_DATA_IN,
INT_PACKET_NUM_OUT=> MED_PACKET_NUM_IN,
INT_READ_IN => MED_READ_OUT,
- INT_ERROR_OUT => MED_ERROR_IN,
INT_DATAREADY_IN => MED_DATAREADY_OUT,
INT_DATA_IN => MED_DATA_OUT,
INT_PACKET_NUM_IN => MED_PACKET_NUM_OUT,
MED_DATA_OUT => buf_LVDS_OUT,
MED_DATA_IN => buf_LVDS_IN,
STAT => LVDS_STAT,
- CTRL => LVDS_CTRL
+ CTRL => LVDS_CTRL,
+ STAT_OP => MED_STAT_OP,
+ CTRL_OP => MED_CTRL_OP
);
+MED_CTRL_OP(14 downto 0) <= (others => '0');
+MED_CTRL_OP(15) <= MED_STAT_OP(15);
+
LVDS_OUT(12 downto 8) <= buf_LVDS_OUT(15 downto 11);
LVDS_OUT(7 downto 0) <= buf_LVDS_OUT(7 downto 0);
-- LVDS_OUT(12 downto 0) <= LVDS_STAT(31 downto 19);
+API_STAT_IN <= buf_api_stat_fifo_to_int;
+
MPLEX: trb_net16_io_multiplexer
port map (
CLK => clk_trb,
MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0),
MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
MED_READ_OUT => m_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN,
+ MED_ERROR_IN => MED_STAT_OP(2 downto 0),
-- Internal direction port
INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
STAT_GEN => STAT_GEN((i+1)*32-1 downto i*32),
STAT_IBUF_BUFFER => STAT_INIT_BUFFER((i+1)*32-1 downto i*32),
CTRL_GEN => CTRL_GEN((i+1)*32-1 downto i*32),
- STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32)
+ STAT_CTRL_IBUF_BUFFER => STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32),
+ STAT_INIT_OBUF_DEBUG => STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32)
);
end generate;
SBUF_VERSION => 0,
USE_VENDOR_CORES => c_YES,
SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
+ SECURE_MODE_TO_INT => c_NO,
APL_WRITE_ALL_WORDS => c_YES,
BROADCAST_BITMASK => x"FF"
)
SBUF_VERSION => 0,
USE_VENDOR_CORES => c_YES,
SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
+ SECURE_MODE_TO_INT => c_NO,
APL_WRITE_ALL_WORDS => c_YES,
BROADCAST_BITMASK => x"FF"
)
CPU_INTERRUPT_OUT => TRB_INTERRUPT_OUT,
STAT => APL_STAT,
CTRL(12 downto 0) => LVDS_STAT(31 downto 19),
- CTRL(31 downto 13) => "1111000000000000000"
+ CTRL(31 downto 13) => "1111000000000000000",
+ API_STAT_IN => API_STAT_IN,
+ API_OBUF_STAT_IN => STAT_INIT_OBUF_DEBUG
);
DATA_OUT <= buf_DATA_OUT;
signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic;
signal endpoint_reached : std_logic;
signal sbuf_status : std_logic_vector(2 downto 0);
+ signal buf_APL_RUN_OUT : std_logic;
begin
---------------------------------------
STAT_FIFO_TO_INT(16) <= next_APL_DATAREADY_OUT;
STAT_FIFO_TO_INT(17) <= sbuf_to_apl_free;
STAT_FIFO_TO_INT(18) <= fifo_to_apl_read_before;
- STAT_FIFO_TO_INT(19) <= fifo_to_apl_read;
- STAT_FIFO_TO_INT(20) <= fifo_to_apl_empty;
- STAT_FIFO_TO_INT(21) <= fifo_to_apl_write;
+ STAT_FIFO_TO_INT(19) <= slave_running;
+ STAT_FIFO_TO_INT(20) <= buf_APL_RUN_OUT;
+ STAT_FIFO_TO_INT(21) <= master_running;
STAT_FIFO_TO_INT(24 downto 22) <= next_INT_MASTER_PACKET_NUM_OUT;
STAT_FIFO_TO_INT(25) <= next_INT_MASTER_DATAREADY_OUT;
STAT_FIFO_TO_INT(28 downto 26) <= state_bits_to_int;
fifo_to_int_data_in <= APL_DATA_IN;
fifo_to_int_packet_num_in <= APL_PACKET_NUM_IN(2) & APL_PACKET_NUM_IN(0);
fifo_to_int_write <= (APL_DATAREADY_IN and not fifo_to_int_full);
- APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
+
+ APL_READ_OUT <= not fifo_to_int_full; -- APL has to stop writing
-- connect receiver
fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
begin
if rising_edge(CLK) then
if RESET = '1' then
- APL_RUN_OUT <= '0';
+ buf_APL_RUN_OUT <= '0';
elsif CLK_EN = '1' then
if API_TYPE = 0 then
if slave_start = '1' then
- APL_RUN_OUT <= '1';
+ buf_APL_RUN_OUT <= '1';
elsif slave_running = '0' and state_to_int = INACTIVE then
- APL_RUN_OUT <= '0';
+ buf_APL_RUN_OUT <= '0';
end if;
else --API_TYPE = 1
if master_start = '1' then
- APL_RUN_OUT <= '1';
+ buf_APL_RUN_OUT <= '1';
elsif master_running = '0' and state_to_apl = sa_INACTIVE then
- APL_RUN_OUT <= '0';
+ buf_APL_RUN_OUT <= '0';
end if;
end if;
end if;
end if;
end process;
+ APL_RUN_OUT <= buf_APL_RUN_OUT;
RUNNING_gen : process(CLK)
begin
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
- RESET_TRBNET_IN : in std_logic;
+
-- Media direction port
MED_DATAREADY_OUT : out std_logic;
MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
+
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-- APL Transmitter port
APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
begin
- reset_internal <= RESET_TRBNET_IN or RESET;
- MED_CTRL_OP(15) <= MED_STAT_OP(15);
- MED_CTRL_OP(14 downto 0) <= (others => '0');
+ reset_internal <= MED_STAT_OP_IN(13) or RESET;
+ MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15);
+ MED_CTRL_OP_OUT(14 downto 0) <= (others => '0');
--Connections for data channel
genmuxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
STAT_api_control_signals(19 downto 16) <= MED_INIT_DATA_OUT(3 downto 0);
STAT_api_control_signals(21 downto 20) <= MED_INIT_PACKET_NUM_OUT(1 downto 0);
STAT_api_control_signals(22) <= MED_INIT_DATAREADY_OUT and MED_INIT_READ_IN;
-STAT_api_control_signals(28 downto 23) <= (others => '0');
+STAT_api_control_signals(23) <= apl_to_buf_REPLY_DATAREADY;
+STAT_api_control_signals(24) <= MED_REPLY_DATAREADY_OUT;
+STAT_api_control_signals(25) <= MED_INIT_DATAREADY_OUT;
+STAT_api_control_signals(26) <= apl_to_buf_INIT_DATAREADY;
+STAT_api_control_signals(27) <= reset_internal;
+STAT_api_control_signals(28) <= '0';
--STAT_api_control_signals(30 downto 13) <= (others => '0');
STAT_api_control_signals(31) <= buf_to_apl_INIT_READ;
MED_DATA_IN => MED_IO_DATA_IN,
MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
MED_READ_OUT => MED_IO_READ_OUT,
- MED_ERROR_IN => MED_ERROR_IN,
+ MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0),
MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
--API: interfaces
--generate media resync
gen_resync : for i in 0 to MII_NUMBER-1 generate
resync(i) <= MED_STAT_OP(i*16+15);
- MED_CTRL_OP(15+i*16) <= reg_resync;
+ MED_CTRL_OP(15+i*16) <= combined_resync;
end generate;
combined_resync <= or_all(resync);
---insert deadtime here
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- resync_counter <= (others => '0');
- reg_resync <= '0';
- else
- if combined_resync = '1' then
- reg_resync <= '1';
- elsif resync_counter = x"FE" then
- reg_resync <= '0';
- end if;
- if reg_resync = '1' then
- resync_counter <= resync_counter + 1;
- end if;
- end if;
- end if;
- end process;
-
--generate multiplexers
gen_muxes: for i in 0 to MII_NUMBER-1 generate
CTRL => MPLEX_CTRL((i+1)*32-1 downto i*32),
STAT => MPLEX_STAT((i+1)*32-1 downto i*32)
);
+ m_ERROR_IN((i+1)*3-1 downto i*3) <=MED_STAT_OP(i*16+2 downto i*16);
end generate;
MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
end generate;
gen_MED_CON : for i in 0 to MII_NUMBER-1 generate
- process(MED_ERROR_IN)
+ process(m_ERROR_IN)
begin
- if MED_ERROR_IN((i+1)*3-1 downto i*3) /= ERROR_OK then
+ if m_ERROR_IN((i+1)*3-1 downto i*3) /= ERROR_OK then
HUB_MED_CONNECTED(i) <= '0';
else
HUB_MED_CONNECTED(i) <= '1';
buf_STAT_DEBUG(12) <= m_DATAREADY_OUT(0);
buf_STAT_DEBUG(15 downto 13) <= m_PACKET_NUM_OUT(2 downto 0);
- buf_STAT_DEBUG(17 downto 16) <= hub_to_buf_INIT_DATAREADY(1 downto 0);
- buf_STAT_DEBUG(20 downto 18) <= hub_to_buf_INIT_PACKET_NUM(2 downto 0);
- buf_STAT_DEBUG(30 downto 21) <= IOBUF_STAT_INIT_OBUF_DEBUG(9 downto 0);
+-- buf_STAT_DEBUG(17 downto 16) <= hub_to_buf_INIT_DATAREADY(1 downto 0);
+-- buf_STAT_DEBUG(20 downto 18) <= hub_to_buf_INIT_PACKET_NUM(2 downto 0);
+ buf_STAT_DEBUG(31 downto 16) <= IOBUF_STAT_INIT_OBUF_DEBUG(15 downto 0);
-- STAT_DEBUG(0) <= comb_dataready;
-- STAT_DEBUG(3 downto 1) <= transfer_counter;
MED_READ_IN: in std_logic;
--STAT
STAT_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_BUFFER: in std_logic_vector (31 downto 0)
+ CTRL_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_DEBUG : out std_logic_vector (31 downto 0)
);
end component;
end generate;
genINITOBUF2 : if INIT_CAN_SEND_DATA = 0 generate
gen_INITOBUF3 : if USE_ACKNOWLEDGE = 1 generate
- STAT_INIT_OBUF_DEBUG <= (others => '0');
INITOBUF : trb_net16_obuf_nodata
port map (
CLK => CLK,
MED_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
MED_READ_IN => MED_INIT_READ_IN,
STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer,
- CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer
+ CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer,
+ STAT_DEBUG => STAT_INIT_OBUF_DEBUG
);
INT_INIT_READ_OUT <= '0';
end generate;
end generate;
genREPLYOBUF2 : if REPLY_CAN_SEND_DATA = 0 generate
gen_REPLYOBUF3 : if USE_ACKNOWLEDGE = 1 generate
- STAT_REPLY_OBUF_DEBUG <= (others => '0');
+
REPLYOBUF : trb_net16_obuf_nodata
port map (
CLK => CLK,
MED_PACKET_NUM_OUT => MED_REPLY_PACKET_NUM_OUT,
MED_READ_IN => MED_REPLY_READ_IN,
STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer,
- CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer
+ CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer,
+ STAT_DEBUG => STAT_REPLY_OBUF_DEBUG
);
INT_REPLY_READ_OUT <= '0';
end generate;
INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_IN : in std_logic;
- INT_ERROR_OUT : out std_logic_vector (2 downto 0);
INT_DATAREADY_IN : in std_logic;
INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
signal rx_fifo_data_out : std_logic_vector(17 downto 0);
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
+ signal rx_fifostatus_out : std_logic_vector(3 downto 0);
+ signal rx_valid_read_out : std_logic;
+ signal rx_almost_empty_out : std_logic;
+ signal rx_almost_full_out : std_logic;
signal buf_INT_DATAREADY_OUT : std_logic;
signal buf_INT_READ_OUT : std_logic;
signal tx_clock_enable : std_logic;
signal next_tx_reset : std_logic;
- signal buf_tx_reset : std_logic;
- signal buf_tx_clk, buf2_tx_clk : std_logic;
- signal C_D0, C_D1,Q : std_logic_vector(0 downto 0);
+ signal buf_tx_reset : std_logic;
+ signal buf_tx_clk : std_logic;
signal recv_clk_real_locked : std_logic;
signal locked_counter : std_logic_vector(19 downto 0);
-
+ signal led_counter : std_logic_vector(18 downto 0);
+ signal send_resync_counter : std_logic_vector(11 downto 0);
+ signal send_resync : std_logic;
+ signal rx_led, tx_led, link_led : std_logic;
+ signal med_error : std_logic_vector(2 downto 0);
+ signal trbnet_reset : std_logic;
begin
next_tx_reset <= CTRL_OP(15) or (recv_clk_real_locked and wait_for_startup_slow);
--- clk_ddr : dualdatarate_flipflop
--- port map(
--- C0 => CLK,
--- C1 => not CLK,
--- CE => '1',
--- CLR => not tx_clock_enable,
--- D0 => C_D0,
--- D1 => C_D1,
--- PRE => '0',
--- Q => Q
--- );
--- C_D0(0) <= buf_tx_clk;
--- C_D1(0) <= buf_tx_clk;
--- TX_CLK_OUT <= Q(0);
---TX_CLK_OUT <= buf_tx_clk;
process(CLK)
begin
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or med_reset = '1' then
+ if med_reset = '1' then
tx_datavalid <= '0';
tx_reset <= '1';
buf_tx_reset <= '1';
tx_first_packet <= '0';
tx_parity <= '0';
buf_tx_clk <= '0';
- buf2_tx_clk <= '0';
else
buf_INT_DATA_IN <= INT_DATA_IN;
tx_datavalid <= INT_DATAREADY_IN and buf_INT_READ_OUT;
buf_tx_reset <= next_tx_reset;
tx_parity <= xor_all(INT_DATA_IN);
buf_tx_clk <= not buf_tx_clk;
--- buf2_tx_clk <= buf_tx_clk;
end if;
end if;
end process;
read_data_out => rx_fifo_data_out,
full_out => rx_fifo_full,
empty_out => rx_fifo_empty,
- fifostatus_out => open,
- valid_read_out => open,
- almost_empty_out => open,
- almost_full_out => open
+ fifostatus_out => rx_fifostatus_out,
+ valid_read_out => rx_valid_read_out,
+ almost_empty_out => rx_almost_empty_out,
+ almost_full_out => rx_almost_full_out
);
rx_fifo_read_enable <= INT_READ_IN;
packet_counter_p : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or med_reset = '1' then
+ if med_reset = '1' then
rx_packet_counter <= "100";
elsif buf_INT_DATAREADY_OUT = '1' then
if rx_packet_counter = c_max_word_number then
rx_dataready_p : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' or med_reset = '1' then
+ if med_reset = '1' then
buf_INT_DATAREADY_OUT <= '0';
else
buf_INT_DATAREADY_OUT <= rx_fifo_read_enable and not rx_fifo_empty;
begin
if rising_edge(CLK) then
if recv_clk_real_locked = '0' or rx_clock_detect = '0' then
- INT_ERROR_OUT <= ERROR_NC;
+ med_error <= ERROR_NC;
elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error
- INT_ERROR_OUT <= ERROR_ENCOD;
+ med_error <= ERROR_ENCOD;
elsif (rx_packet_counter /= "100" and buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(17) = '1') then
- INT_ERROR_OUT <= ERROR_FATAL; --Counter error
+ med_error <= ERROR_FATAL; --Counter error
else
- INT_ERROR_OUT <= ERROR_OK;
+ med_error <= ERROR_OK;
end if;
end if;
end process;
--STAT & CTRL Ports
-------------------------
- STAT_OP(14 downto 0) <= (others => '0');
+
+--LED
+ link_led <= rx_clock_detect and not wait_for_startup_slow;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if led_counter(18) = '1' then
+ led_counter <= (others => '0');
+ else
+ led_counter <= led_counter + 1;
+ end if;
+ if rx_fifo_empty = '0' then
+ rx_led <= '1';
+ elsif led_counter(18) = '1' then
+ rx_led <= '0';
+ end if;
+ if tx_datavalid = '1' then
+ tx_led <= '1';
+ elsif led_counter(18) = '1' then
+ tx_led <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ STAT_OP(2 downto 0) <= med_error;
+ STAT_OP(8 downto 3) <= (others => '0');
+ STAT_OP(9) <= link_led;
+ STAT_OP(10) <= rx_led;
+ STAT_OP(11) <= tx_led;
+ STAT_OP(12) <= '0';
+ STAT_OP(13) <= trbnet_reset;
+ STAT_OP(14) <= rx_clock_detect;
STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0';
STAT(12) <= rx_parity_match;
STAT(2) <= next_tx_reset;
STAT(1) <= buf_RX_CLK;
- STAT(31 downto 13) <= (others => '0');
+ STAT(13) <= or_all(rx_fifostatus_out);
+ STAT(14) <= rx_valid_read_out;
+ STAT(15) <= rx_almost_empty_out;
+ STAT(16) <= rx_almost_full_out;
+ STAT(31 downto 17) <= (others => '0');
+
+ med_reset <= RESET or send_resync;
+ trbnet_reset <= rx_reset or not recv_clk_real_locked;
- med_reset <= RESET or CTRL_OP(15);
+
+--detect resync
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ send_resync <= '0';
+ send_resync_counter <= (others => '0');
+ else
+ if not (send_resync_counter = 0) then
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
+ send_resync <= '1';
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if send_resync_counter = x"00F" then
+ send_resync <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
end architecture;
\ No newline at end of file
MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
MED_DATAREADY_OUT : out std_logic;
MED_READ_IN : in std_logic;
- MED_ERROR_OUT : out std_logic_vector(2 downto 0);
REFCLK2CORE_OUT : out std_logic;
--SFP Connection
SD_RXD_P_IN : in std_logic;
end if;
if CTRL_OP(15) = '1' and send_resync_counter = 0 then
next_send_resync <= '1';
- send_resync_counter <= x"001";
+ send_resync_counter <= send_resync_counter + 1;
end if;
if send_resync_counter = x"00F" then
next_send_resync <= '0';
signal next_send_resync : std_logic_vector(0 downto 0);
signal buf_RESET_TRBNET_OUT : std_logic;
- signal led_counter : std_logic_vector(17 downto 0);
+ signal led_counter : std_logic_vector(18 downto 0);
signal rx_led, tx_led, link_led : std_logic;
begin
process(CLK)
begin
if rising_edge(CLK) then
- led_counter <= led_counter + 1;
-
+ if led_counter(18) = '1' then
+ led_counter <= (others => '0');
+ else
+ led_counter <= led_counter + 1;
+ end if;
if buf_med_dataready_out = '1' then
rx_led <= '1';
- elsif led_counter = 0 then
+ elsif led_counter(18) = '1' then
rx_led <= '0';
end if;
if MED_DATAREADY_IN = '1' then
tx_led <= '1';
- elsif led_counter = 0 then
+ elsif led_counter(18) = '1' then
tx_led <= '0';
end if;
end if;
end process;
- link_led <= (timing_ctr(24) or tx_allow_q) and not sfp_los;
+ link_led <= (counter(24) or tx_allow) and not sfp_los;
stat_op(2 downto 0) <= buf_MED_ERROR_OUT;
stat_op(8 downto 3) <= (others => '0'); -- unused
STAT(58 downto 57) <= "00";
STAT(59) <= TLK_CLK_neg;
STAT(60) <= fifo_wr_en_m;
- STAT(61) <= buf_RESET_TRBNET_OUT;
- STAT(63 downto 62) <= resync_counter(1 downto 0);
+ STAT(63 downto 61) <= resync_counter(2 downto 0);
--STAT(63 downto 57) <= (others => '0');
STAT_MONITOR(17 downto 0) <= fifo_din_a;
--Detect resync (incl. SFP_LOS)
---------------
-RESET_TRBNET_OUT <= buf_RESET_TRBNET_OUT;
process(CLK)
begin
buf_STAT_OP(15) <= '0';
buf_RESET_TRBNET_OUT <= '0';
if RESET = '1' or internal_reset = '1' then
- buf_RESET_TRBNET_OUT <= '0';
+ buf_RESET_TRBNET_OUT <= '1';
+ resync_counter <= "000";
end if;
if buf_MED_DATAREADY_OUT = '1' then
- if fifo_dout_a(7 downto 0) = x"7F" then
+ if fifo_dout_a(15 downto 0) = x"007F" then
resync_counter <= resync_counter + 1;
else
resync_counter <= "000";
next_internal_reset <= '0';
end if;
when WAIT_FOR_RX_LOCK =>
+ next_internal_reset <= '0';
if counter(28) = '1' then
counter_reset <= '1';
next_rx_allow <= '1';
end if;
when WAIT_FOR_TX_ALLOW =>
next_MED_ERROR_OUT <= ERROR_WAIT;
+ next_internal_reset <= '0';
if counter(28) = '1' then
next_tx_allow <= '1';
next_state <= WORKING;
end if;
when WORKING =>
next_MED_ERROR_OUT <= ERROR_OK;
+ next_internal_reset <= '0';
end case;
if reg_RX_ER = '1' and internal_reset = '0' then
next_rx_allow <= '0';
STAT_DEBUG(7 downto 5) <= buf_MED_PACKET_NUM_OUT;
STAT_DEBUG(8) <= sbuf_free;
STAT_DEBUG(9) <= comb_next_read;
-
+STAT_DEBUG(10) <= SEND_ACK_IN;
+STAT_DEBUG(11) <= reg_SEND_ACK_IN;
+STAT_DEBUG(12) <= RESET;
+STAT_DEBUG(14 downto 13) <= TRANSMITTED_BUFFERS;
+STAT_DEBUG(17 downto 15) <= REC_BUFFER_SIZE_IN(2 downto 0);
+STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0);
+STAT_DEBUG(20) <= '1';
end architecture;
\ No newline at end of file
MED_READ_IN : in std_logic;
--STAT
STAT_BUFFER : out std_logic_vector (31 downto 0);
- CTRL_BUFFER : in std_logic_vector (31 downto 0)
+ CTRL_BUFFER : in std_logic_vector (31 downto 0);
+ STAT_DEBUG : out std_logic_vector (31 downto 0)
);
end entity;
signal SEND_BUFFER_SIZE_IN : std_logic_vector(3 downto 0);
signal SEND_ACK_IN : std_logic;
- signal current_NOP_word : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal current_ACK_word : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+-- signal transfer_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal buf_MED_DATAREADY_OUT, next_MED_DATAREADY_OUT : std_logic;
- signal buf_MED_DATA_OUT, next_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_MED_DATAREADY_OUT : std_logic;
+ signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal sending_ACK, next_sending_ACK : std_logic;
- signal send_ACK : std_logic;
- signal reg_SEND_ACK_IN_2, next_SEND_ACK_IN_2 : std_logic;
- signal reg_SEND_ACK_IN, next_SEND_ACK_IN : std_logic;
+ signal reg_SEND_ACK_IN_2 : std_logic;
+ signal reg_SEND_ACK_IN : std_logic;
+
+
begin
SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0);
SEND_ACK_IN <= CTRL_BUFFER(8);
- send_ACK <= SEND_ACK_IN or reg_SEND_ACK_IN or reg_SEND_ACK_IN_2;
- next_SEND_ACK_IN_2 <= (reg_SEND_ACK_IN_2 or SEND_ACK_IN) and reg_SEND_ACK_IN;
MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
MED_DATA_OUT <= buf_MED_DATA_OUT;
- process(current_NOP_word, SEND_ACK, current_ACK_word, transfer_counter, MED_READ_IN,reg_SEND_ACK_IN)
+ process(CLK)
+ variable transfer_counter : std_logic_vector(2 downto 0);
begin
- next_MED_DATA_OUT <= current_NOP_word;
- next_MED_DATAREADY_OUT <= '0';
- next_SEND_ACK_IN <= send_ACK;
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ buf_MED_DATAREADY_OUT <= '0';
+ reg_SEND_ACK_IN_2 <= '0';
+ reg_SEND_ACK_IN <= '0';
+ transfer_counter := c_H0;
+ elsif CLK_EN = '1' then
+ reg_SEND_ACK_IN_2 <= (reg_SEND_ACK_IN_2 or SEND_ACK_IN) and reg_SEND_ACK_IN;
- if reg_SEND_ACK_IN = '1' then
- next_MED_DATA_OUT <= current_ACK_word;
- next_MED_DATAREADY_OUT <= '1';
- if transfer_counter <= c_F3 and MED_READ_IN = '1' then
- next_SEND_ACK_IN <= '0';
- end if;
- end if;
- end process;
+ if MED_READ_IN = '1' and reg_SEND_ACK_IN = '1' then
+ if transfer_counter = c_max_word_number then
+ transfer_counter := "000";
+ else
+ transfer_counter := transfer_counter + 1;
+ end if;
+ end if;
- REG_SEND_DATA : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
buf_MED_DATA_OUT <= (others => '0');
- buf_MED_PACKET_NUM_OUT <= (others => '0');
+ if transfer_counter = c_F1 then
+ buf_MED_DATA_OUT(3 downto 0) <= SEND_BUFFER_SIZE_IN;
+ elsif transfer_counter = c_H0 then
+ buf_MED_DATA_OUT(2 downto 0) <= TYPE_ACK;
+ end if;
+
buf_MED_DATAREADY_OUT <= '0';
- else
- buf_MED_DATA_OUT <= next_MED_DATA_OUT;
- buf_MED_PACKET_NUM_OUT <= transfer_counter;
- buf_MED_DATAREADY_OUT <= next_MED_DATAREADY_OUT;
- end if;
- end if;
- end process;
+ reg_SEND_ACK_IN <= SEND_ACK_IN or reg_SEND_ACK_IN or reg_SEND_ACK_IN_2;
- GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN)
- begin
- current_NOP_word <= (others => '0');
- current_NOP_word(2 downto 0) <= TYPE_ILLEGAL;
- current_ACK_word <= (others => '0');
- if transfer_counter = c_F1 then
- current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN;
- elsif transfer_counter = c_H0 then
- current_ACK_word(2 downto 0) <= TYPE_ACK;
- end if;
- end process;
+ if (SEND_ACK_IN or reg_SEND_ACK_IN or reg_SEND_ACK_IN_2) = '1' then
+ buf_MED_DATAREADY_OUT <= '1';
+ end if;
- REG_TRANSFER_COUNTER : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- transfer_counter <= (others => '0');
- elsif buf_MED_DATAREADY_OUT = '1' and MED_READ_IN = '1' then
- if transfer_counter = c_max_word_number then
- transfer_counter <= (others => '0');
- else
- transfer_counter <= transfer_counter + 1;
+ if transfer_counter = c_F3 and MED_READ_IN = '1' then
+ reg_SEND_ACK_IN <= '0';
end if;
+ if transfer_counter = c_F3 and reg_SEND_ACK_IN = '0' then
+ transfer_counter := c_H0;
+ end if;
+ buf_MED_PACKET_NUM_OUT <= transfer_counter;
end if;
end if;
end process;
- REG_SEND_ACK : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_SEND_ACK_IN <= '0';
- reg_SEND_ACK_IN_2 <= '0';
- elsif CLK_EN = '1' then
- reg_SEND_ACK_IN <= next_SEND_ACK_IN;
- reg_SEND_ACK_IN_2 <= next_SEND_ACK_IN_2;
- end if;
- end if;
- end process;
+
STAT_BUFFER <= (others => '0');
+ STAT_DEBUG(0) <= SEND_ACK_IN;
+ STAT_DEBUG(1) <= reg_SEND_ACK_IN;
+ STAT_DEBUG(2) <= buf_MED_DATAREADY_OUT;
+ STAT_DEBUG(5 downto 3) <= buf_MED_PACKET_NUM_OUT;
+ STAT_DEBUG(6) <= MED_READ_IN;
+ STAT_DEBUG(31 downto 7) <= (others => '0');
+
end architecture;
INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
INT_READ_IN : in STD_LOGIC;
- INT_ERROR_OUT : out STD_LOGIC_VECTOR (2 downto 0);
INT_DATAREADY_IN : in STD_LOGIC;
INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
STAT: out STD_LOGIC_VECTOR (31 downto 0);
--STAT(5 downto 2): Debug bits in
- CTRL: in STD_LOGIC_VECTOR (31 downto 0)
- --CTRL(24..31) -> lvds-data(63 downto 56) via lvds
- --once for each packet
+ CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ STAT_OP : out std_logic_vector(15 downto 0);
+ CTRL_OP : in std_logic_vector(15 downto 0)
);
end entity trb_net_med_8bit_slow;
signal last_MED_TRANSMISSION_CLK_IN : std_logic;
signal last_MED_FIRST_PACKET_IN : std_logic;
- signal reg_MED_DATA_IN : std_logic_vector(7 downto 0);
+ signal reg_MED_DATA_IN : std_logic_vector(11 downto 0);
signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic;
signal reg_MED_PARITY_IN : std_logic;
signal recv_counter : std_logic_vector(3 downto 0);
signal transmission_running, next_transmission_running : std_logic;
signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0);
+ signal led_counter : std_logic_vector(18 downto 0);
+ signal send_resync_counter : std_logic_vector(11 downto 0);
+ signal send_resync : std_logic;
+ signal rx_led, tx_led, link_led : std_logic;
+ signal trbnet_reset : std_logic;
+
begin
INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
INT_DATA_OUT <= buf_INT_DATA_OUT;
INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT;
- INT_ERROR_OUT <= my_error;
INT_READ_OUT <= buf_INT_READ_OUT;
STAT <= buf_STAT;
buf_STAT(1 downto 0) <= (others => '0');
buf_STAT(5 downto 2) <= MED_DATA_IN(11 downto 8);
buf_STAT(18 downto 6)<= (others => '0');
- buf_STAT(31 downto 19) <= reg_MED_PARITY_IN & reg_MED_CARRIER_IN & reg_MED_TRANSMISSION_CLK_IN & reg_MED_FIRST_PACKET_IN & MED_DATA_IN(11) & reg_MED_DATA_IN;
+ buf_STAT(31 downto 19) <= reg_MED_PARITY_IN & reg_MED_CARRIER_IN & reg_MED_TRANSMISSION_CLK_IN & reg_MED_FIRST_PACKET_IN & reg_MED_DATA_IN(11) & reg_MED_DATA_IN(7 downto 0);
MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT;
-
- MED_DATA_OUT(10 downto 8) <= buf_MED_DATA_IN(2 downto 0);
-
-
- MED_DATA_OUT(11) <= not reset;
+ MED_DATA_OUT(10 downto 8) <= (others => '0');
+ MED_DATA_OUT(11) <= (not reset or send_resync);
MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT;
MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT;
MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT;
MED_DATA_OUT(15) <= buf_MED_PARITY_OUT;
+--LED & Stat_OP
+ STAT_OP(2 downto 0) <= my_error;
+ STAT_OP(8 downto 3) <= (others => '0');
+ STAT_OP(9) <= link_led;
+ STAT_OP(10) <= rx_led;
+ STAT_OP(11) <= tx_led;
+ STAT_OP(12) <= '0';
+ STAT_OP(13) <= not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN;
+ STAT_OP(14) <= (not reg_MED_DATA_IN(11) and reg_MED_CARRIER_IN) or media_not_connected;
+ STAT_OP(15) <= (not reg_MED_DATA_IN(11) and not last_MED_TRANSMISSION_CLK_IN and reg_MED_TRANSMISSION_CLK_IN and reg_MED_CARRIER_IN) or media_not_connected;
+
+ link_led <= reg_MED_DATA_IN(11);
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if reset = '1' then
+ led_counter <= (others => '0');
+ rx_led <= '0';
+ tx_led <= '0';
+ else
+ if led_counter(18) = '1' then
+ led_counter <= (others => '0');
+ else
+ led_counter <= led_counter + 1;
+ end if;
+ if reg_MED_CARRIER_IN = '1' then
+ rx_led <= '1';
+ elsif led_counter(18) = '1' then
+ rx_led <= '0';
+ end if;
+ if next_MED_CARRIER_OUT = '1' then
+ tx_led <= '1';
+ elsif led_counter(18) = '1' then
+ tx_led <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ send_resync <= '0';
+ send_resync_counter <= (others => '0');
+ else
+ if not (send_resync_counter = 0) then
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then
+ send_resync <= '1';
+ send_resync_counter <= send_resync_counter + 1;
+ end if;
+ if send_resync_counter = x"00F" then
+ send_resync <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
--TODO:
--------------------------------
fatal_error <= '0';
-
-
--My error bits
--------------------------------
reg_my_error: process(CLK,RESET)
buf_MED_PARITY_OUT)
begin
next_media_not_connected <= '0';
- if last_TRCLK = '0' and this_TRCLK = '1' then
+ if RESET = '1' then
+ next_CLK_counter <= x"1F";
+ elsif last_TRCLK = '0' and this_TRCLK = '1' then
next_CLK_counter <= (others => '0');
- elsif CLK_counter = 255 then
+ elsif CLK_counter = 31 then
next_media_not_connected <= '1';
next_CLK_counter <= CLK_counter;
else
next_transmission_running <= '0';
end if;
end if;
+ if send_resync = '1' then
+ next_MED_CARRIER_OUT <= '1';
+ end if;
end process;
if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then
if recv_counter(0) = '1' or (reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0') then
- next_buf_MED_DATA_IN <= reg_MED_DATA_IN;
+ next_buf_MED_DATA_IN <= reg_MED_DATA_IN(7 downto 0);
else
- next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN;
+ next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN(7 downto 0);
next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN;
next_INT_PACKET_NUM_OUT <= recv_counter(3 downto 1);
next_INT_DATAREADY_OUT <= '1';
reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13);
reg_MED_CARRIER_IN <= MED_DATA_IN(14);
reg_MED_PARITY_IN <= MED_DATA_IN(15);
- reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0);
+ reg_MED_DATA_IN <= MED_DATA_IN(11 downto 0);
reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12);
end if;
end process;
jspc29 / trbnet.git / commitdiff