CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
+
INT_DATAREADY_OUT : out std_logic;
INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_IN : in std_logic;
+
INT_DATAREADY_IN : in std_logic;
INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_OUT : out std_logic;
- -- "mini" APL, just to see terminations coming in
- APL_DTYPE_OUT : out std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- APL_GOT_TRM : out std_logic;
- APL_RELEASE_TRM : in std_logic;
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
+ APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0)
);
end component;