rx_control: Use system clock for sampling rx_allow

rx_allow is synchronous to the system clock. ct_fifo_reset is
asynchronous and can therefore be produced with the system clock to
avoid timing errors.

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index 88c91fbce327fa3e934927ca49dbc15f6bc73b08..8e8085b1874999403acdda175359d8d8a03aa678 100644 (file)
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -128,7 +128,7 @@ THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg
     AlmostFull        => ct_fifo_afull
     );
 
-ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200);    
+ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_100);    
 
 
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