CTS_REPLY_READ_IN : in std_logic;
--Event information coming from CTS
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
- CTS_START_READOUT_OUT : out std_logic;
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high
+ CTS_START_READOUT_OUT : out std_logic; --goes high after request is transported through hub, goes low
+ --after user send information to cts.
--Information sent to CTS
--status data, equipped with DHDR
CTS_DATA_IN : in std_logic_vector (31 downto 0);
CTS_DATAREADY_IN : in std_logic;
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle
CTS_READ_OUT : out std_logic;
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0); --valid when raising dataready for first time
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high
-- Data from Frontends
- FEE_DATA_OUT : out std_logic_vector (31 downto 0);
- FEE_DATAREADY_OUT : out std_logic;
+ FEE_DATA_OUT : out std_logic_vector (31 downto 0); --data from FEE
+ FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid
FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
- FEE_BUSY_OUT : out std_logic;
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again
+ FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE
+ --has been read.
MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
CTRL_SEQNR_RESET : in std_logic;
signal APL_CTS_DATAREADY_OUT : std_logic;
signal APL_CTS_READ_IN : std_logic;
signal APL_CTS_SEQNR_OUT : std_logic_vector(7 downto 0);
+ signal APL_CTS_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
signal APL_FEE_DTYPE_IN : std_logic_vector(3 downto 0);
signal APL_FEE_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
--will be low every second cycle due to 32bit -> 16bit conversion
IPU_READ_OUT => CTS_READ_OUT,
IPU_LENGTH_IN => CTS_LENGTH_IN,
- IPU_ERROR_PATTERN_IN => CTS_ERROR_PATTERN_IN,
+ IPU_ERROR_PATTERN_IN => CTS_STATUS_BITS_IN,
STAT_DEBUG => open
);