API_PACKET_NUM_OUT: out std_logic_vector(1 downto 0);
API_DATAREADY_OUT : out std_logic;
API_READ_IN : in std_logic;
- ADDRESS_REJECTED : out std_logic;
+ ADDRESS_REJECTED : out std_logic;
+ API_SEND_OUT : out std_logic;
ADDRESS_OUT : out std_logic_vector(15 downto 0)
);
end entity;
signal next_read_uid_1, read_uid_1 : std_logic;
signal next_read_uid_2, read_uid_2 : std_logic;
-
+signal finished, next_finished : std_logic;
begin
end if;
end if;
end if;
+ if (read_uid_1 or read_uid_2 or read_UNIQUE_ID) = '1' then
+ ram_read_addr1 <= "000";
+ end if;
end if;
end if;
end process;
ram_read_addr2 <= "000";
next_read_uid_1 <= read_uid_1;
next_read_uid_2 <= read_uid_2;
-
case state is
when IDLE =>
- if write_ADDRESS = '1' then
+ API_SEND_OUT <= '0';
+ if write_ADDRESS = '1' then
ram_read_addr2 <= "111";
next_state <= SEND1;
elsif read_UNIQUE_ID = '1' then
next_state <= SEND1;
end if;
when SEND1 =>
+ API_SEND_OUT <= '1';
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "01";
if read_uid_1 = '1' then
next_state <= SEND2;
end if;
when SEND2 =>
+ API_SEND_OUT <= '1';
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "10";
if read_uid_1 = '1' then
next_state <= SEND3;
end if;
when SEND3 =>
+ API_SEND_OUT <= '1';
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "11";
if read_uid_1 = '1' then
if RESET = '1' then
read_uid_1 <= '0';
read_uid_2 <= '0';
+ finished <= '0';
else
state <= next_state;
read_uid_1 <= next_read_uid_1;
read_uid_2 <= next_read_uid_2;
+ finished <= next_finished;
end if;
-- buf_API_READ_OUT <= next_API_READ_OUT;
end if;
HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
--media interfaces
MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4;
TRG_SEQNR_OUT : out std_logic_vector (VAL(TRG_NUMBER*8) downto 0);
TRG_ERROR_PATTERN_IN : in std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
TRG_RELEASE_IN : in std_logic_vector (VAL(TRG_NUMBER) downto 0);
+ ONEWIRE : inout std_logic;
--Status ports (for debugging)
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
signal combined_resync : std_logic;
signal reg_resync : std_logic;
signal resync_counter : std_logic_vector(7 downto 0);
-
+ signal IDRAM_DATA_IN, IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
+ signal IDRAM_WR_IN : std_logic;
+ signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
+ signal TEMP_OUT : std_logic_vector(11 downto 0);
+
component trb_net16_hub_logic is
generic (
--media interfaces
);
end component;
+ component trb_net_onewire is
+ generic(
+ USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
+ CLK_PERIOD : integer := 10 --clk period in ns
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ --connection to 1-wire interface
+ ONEWIRE : inout std_logic;
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(2 downto 0);
+ WRITE_OUT: out std_logic;
+ TEMP_OUT : out std_logic_vector(11 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
begin
end generate;
combined_resync <= or_all(resync);
+--insert deadtime here
+
process(CLK)
begin
if rising_edge(CLK) then
REGISTERS_IN => HC_STAT_REGS,
REGISTERS_OUT => HC_CTRL_REGS,
--Port to write Unique ID
- IDRAM_DATA_IN => (others => '0'),
+ IDRAM_DATA_IN => IDRAM_DATA_IN,
IDRAM_DATA_OUT => open,
- IDRAM_ADDR_IN => (others => '0'),
- IDRAM_WR_IN => '0',
+ IDRAM_ADDR_IN => IDRAM_ADDR_IN,
+ IDRAM_WR_IN => IDRAM_WR_IN,
DAT_ADDR_OUT => open,
DAT_READ_ENABLE_OUT => open,
DAT_WRITE_ENABLE_OUT=> open,
DAT_NO_MORE_DATA_IN => '0'
);
+ onewire_interface : trb_net_onewire
+ generic map(
+ USE_TEMPERATURE_READOUT => 1,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ --connection to 1-wire interface
+ ONEWIRE => ONEWIRE,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => IDRAM_DATA_IN,
+ ADDR_OUT => IDRAM_ADDR_IN,
+ WRITE_OUT=> IDRAM_WR_IN,
+ TEMP_OUT => TEMP_OUT,
+ STAT => open
+ );
+
--8x CTRL, 8x STAT
buf_HUB_STAT_GEN(0) <= MED_DATA_IN(14);
buf_HUB_STAT_GEN(1) <= buf_to_hub_REPLY_DATA(14);
buf_HUB_STAT_GEN(2) <= buf_to_hub_REPLY_DATAREADY(0);
- buf_HUB_STAT_GEN(31 downto 3) <= (others => '0');
+ buf_HUB_STAT_GEN(19 downto 3) <= (others => '0');
+ buf_HUB_STAT_GEN(31 downto 20) <= TEMP_OUT;
HUB_STAT_GEN <= buf_HUB_STAT_GEN;
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING);
signal current_state, next_state : tlk_state_t;
signal next_tx_allow, next_rx_allow : std_logic;
- signal counter, next_counter : std_logic_vector(27 downto 0);
+ signal counter, next_counter : std_logic_vector(28 downto 0);
signal next_internal_reset : std_logic;
signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0);
signal state_bits : std_logic_vector(2 downto 0);
next_internal_reset <= '0';
end if;
when WAIT_FOR_RX_LOCK =>
- if counter(27) = '1' then
+ if counter(28) = '1' then
counter_reset <= '1';
next_rx_allow <= '1';
next_state <= WAIT_FOR_TX_ALLOW;
API_PACKET_NUM_OUT: out std_logic_vector(1 downto 0);
API_DATAREADY_OUT : out std_logic;
API_READ_IN : in std_logic;
- ADDRESS_REJECTED : out std_logic;
+ API_SEND_OUT : out std_logic;
+ ADDRESS_REJECTED : out std_logic;
ADDRESS_OUT : out std_logic_vector(15 downto 0)
);
end component;
signal state_bits : std_logic_vector(2 downto 0);
+ signal ADR_SEND_OUT : std_logic;
signal ADR_DATAREADY_IN : std_logic;
signal ADR_READ_OUT : std_logic;
signal ADR_DATA_OUT : std_logic_vector(15 downto 0);
API_DATAREADY_OUT => ADR_DATAREADY_OUT,
API_PACKET_NUM_OUT=> ADR_PACKET_NUM_OUT,
API_READ_IN => ADR_READ_IN,
+ API_SEND_OUT => ADR_SEND_OUT,
RAM_DATA_IN => IDRAM_DATA_IN,
RAM_DATA_OUT => IDRAM_DATA_OUT,
RAM_ADDR_IN => IDRAM_ADDR_IN,
next_address <= address;
next_Reg_high <= saved_Reg_high;
next_Reg_low <= saved_Reg_low;
--- next_API_READ_OUT <= '1';
ADR_DATAREADY_IN <= '0';
ADR_READ_IN <= '0';
buf_API_READ_OUT <= '1';
next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
next_API_DATA_OUT <= ADR_DATA_OUT;
next_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
- if ADR_PACKET_NUM_OUT = "11" and API_READ_IN = '1' then
+ if ADR_SEND_OUT = '0' and API_READ_IN = '1' then
next_state <= SEND_REPLY_DATA_finish;
end if;
jspc29 / trbnet.git / commitdiff