signal sgl_debug : std_logic_vector(15 downto 0);
signal blink_counter : unsigned(9 downto 0);
-
+
signal oob_reg_0_int : std_logic_vector(31 downto 0);
signal oob_reg_1_int : std_logic_vector(31 downto 0);
signal oob_reg_2_int : std_logic_vector(31 downto 0);
signal oob_reg_3_int : std_logic_vector(31 downto 0);
-
+
signal dlm_found_int : std_logic;
signal dlm_inject_int : std_logic;
signal dlm_tx_data_int : std_logic_vector(7 downto 0);
signal dlm_rx_data_int : std_logic_vector(7 downto 0);
-
+
signal dlm_ctr : unsigned(23 downto 0);
signal rst_dlm_ctr_x : std_logic;
signal rst_dlm_ctr : std_logic;
-
+
+ signal dlm_tag_ctr : unsigned(7 downto 0);
+ signal inc_dlm_tag : std_logic;
+
begin
---------------------------------------------------------------------------
LED_GREEN_OUT => open
);
-
---------------------------------------------------------------------------
+-- LED blink generator
---------------------------------------------------------------------------
THE_BLINK_COUNTER_PROC: process( clk_sys )
begin
end if;
end process THE_BLINK_COUNTER_PROC;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- DLM timing generator
+---------------------------------------------------------------------------
THE_DLM_SEND_PROC: process( clk_sys )
begin
if( rising_edge(clk_sys) ) then
+ inc_dlm_tag <= rst_dlm_ctr;
rst_dlm_ctr <= rst_dlm_ctr_x;
if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
dlm_ctr <= (others => '0');
rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+-- DLM "tag" for blinking LEDs :)
+THE_DLM_TAG_CTR_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ if( (reset_i = '1') or (aux_reg(31) = '0') ) then
+ dlm_tag_ctr <= (others => '0');
+ elsif( inc_dlm_tag = '1' ) then
+ dlm_tag_ctr <= dlm_tag_ctr + 1;
+ end if;
+ end if;
+end process THE_DLM_TAG_CTR_PROC;
+
---------------------------------------------------------------------------
-- GbE interface (SFP)
---------------------------------------------------------------------------
GBE_SFP_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 0
+ SERDES_NUM => 0,
+ INCLUDE_DLM => 1
)
port map(
RESET => reset_i,
---------------------------------------------------------------------------
GBE_COPPER_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 3
+ SERDES_NUM => 3,
+ INCLUDE_DLM => 1
)
port map(
RESET => reset_i,
);
dlm_inject_int <= rst_dlm_ctr;
- dlm_tx_data_int <= control_reg(7 downto 0);
+ dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr);
---------------------------------------------------------------------------
---------------------------------------------------------------------------
DEBUG => sgl_debug --open
);
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
-
--- debug(7 downto 0) <= ul_rx_data(7 downto 0);
--- debug(15 downto 8) <= ul_tx_data(7 downto 0);
--- debug(16) <= ul_rx_data(9);
--- debug(17) <= ul_tx_data(9);
--- debug(18) <= ul_rx_data(10);
--- debug(19) <= ul_tx_data(10);
--- debug(20) <= ul_rx_data(8);
--- debug(21) <= ul_tx_data(8);
--- debug(22) <= ul_rx_frame_req;
--- debug(23) <= ul_rx_frame_ack;
--- debug(24) <= ul_rx_frame_avail;
--- debug(25) <= dl_rx_frame_req(0);
--- debug(26) <= dl_rx_frame_ack(0);
--- debug(27) <= dl_rx_frame_avail(0);
--- debug(31 downto 28) <= sgl_debug(3 downto 0);
--- debug(32) <= dl_rx_port_mux(1);
--- debug(33) <= clk_sys;
-
---------------------------------------------------------------------------
-- Multiplexers for data streams
---------------------------------------------------------------------------
LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
- LED(3) <= not std_logic(blink_counter(6)); --additional_reg(7); --'0';
- LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
- LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
- LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
+ LED(3) <= not std_logic(blink_counter(8)); --additional_reg(7); --'0';
+ LED(2) <= not dlm_rx_data_int(7); --additional_reg(6); --'0';
+ LED(1) <= not dlm_rx_data_int(6); --additional_reg(5); --'0';
+ LED(0) <= not dlm_rx_data_int(5); --additional_reg(4); --'0';
-- 0 red
-- 1 orange
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(31 downto 28) <= sgl_debug(3 downto 0);
+-- debug(32) <= dl_rx_port_mux(1);
+-- debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- debug(19..0) are on INTCOM
signal sgl_debug : std_logic_vector(15 downto 0);
signal blink_counter : unsigned(9 downto 0);
-
+
signal oob_reg_0_int : std_logic_vector(31 downto 0);
signal oob_reg_1_int : std_logic_vector(31 downto 0);
signal oob_reg_2_int : std_logic_vector(31 downto 0);
signal oob_reg_3_int : std_logic_vector(31 downto 0);
-
+
signal dlm_found_int : std_logic;
signal dlm_inject_int : std_logic;
signal dlm_tx_data_int : std_logic_vector(7 downto 0);
signal rst_dlm_ctr_x : std_logic;
signal rst_dlm_ctr : std_logic;
+ signal dlm_tag_ctr : unsigned(7 downto 0);
+ signal inc_dlm_tag : std_logic;
+
begin
---------------------------------------------------------------------------
LED_GREEN_OUT => open
);
-
---------------------------------------------------------------------------
+-- LED blink generator
---------------------------------------------------------------------------
THE_BLINK_COUNTER_PROC: process( clk_sys )
begin
end if;
end process THE_BLINK_COUNTER_PROC;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- DLM timing generator
+---------------------------------------------------------------------------
THE_DLM_SEND_PROC: process( clk_sys )
begin
if( rising_edge(clk_sys) ) then
+ inc_dlm_tag <= rst_dlm_ctr;
rst_dlm_ctr <= rst_dlm_ctr_x;
if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
dlm_ctr <= (others => '0');
rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+-- DLM "tag" for blinking LEDs :)
+THE_DLM_TAG_CTR_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ if( (reset_i = '1') or (aux_reg(31) = '0') ) then
+ dlm_tag_ctr <= (others => '0');
+ elsif( inc_dlm_tag = '1' ) then
+ dlm_tag_ctr <= dlm_tag_ctr + 1;
+ end if;
+ end if;
+end process THE_DLM_TAG_CTR_PROC;
+
---------------------------------------------------------------------------
-- GbE interface (SFP)
---------------------------------------------------------------------------
GBE_SFP_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 3
+ SERDES_NUM => 3,
+ INCLUDE_DLM => 1
)
port map(
RESET => reset_i,
);
dlm_inject_int <= rst_dlm_ctr;
- dlm_tx_data_int <= control_reg(7 downto 0);
+ dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr);
debug(127 downto 64) <= (others => '0');
---------------------------------------------------------------------------
GBE_COPPER_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 0
+ SERDES_NUM => 0,
+ INCLUDE_DLM => 1
)
port map(
RESET => reset_i,
DEBUG => sgl_debug --open
);
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
-
--- debug(7 downto 0) <= ul_rx_data(7 downto 0);
--- debug(15 downto 8) <= ul_tx_data(7 downto 0);
--- debug(16) <= ul_rx_data(9);
--- debug(17) <= ul_tx_data(9);
--- debug(18) <= ul_rx_data(10);
--- debug(19) <= ul_tx_data(10);
--- debug(20) <= ul_rx_data(8);
--- debug(21) <= ul_tx_data(8);
--- debug(22) <= ul_rx_frame_req;
--- debug(23) <= ul_rx_frame_ack;
--- debug(24) <= ul_rx_frame_avail;
--- debug(25) <= dl_rx_frame_req(0);
--- debug(26) <= dl_rx_frame_ack(0);
--- debug(27) <= dl_rx_frame_avail(0);
--- debug(31 downto 28) <= sgl_debug(3 downto 0);
--- debug(32) <= dl_rx_port_mux(1);
--- debug(33) <= clk_sys;
-
---------------------------------------------------------------------------
-- Multiplexers for data streams
---------------------------------------------------------------------------
LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
- LED(3) <= not std_logic(blink_counter(9)); --additional_reg(7); --'0';
- LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
- LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
- LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
+ LED(3) <= not std_logic(blink_counter(8)); --additional_reg(7); --'0';
+ LED(2) <= not dlm_rx_data_int(7); --additional_reg(6); --'0';
+ LED(1) <= not dlm_rx_data_int(6); --additional_reg(5); --'0';
+ LED(0) <= not dlm_rx_data_int(5); --additional_reg(4); --'0';
-- 0 red
-- 1 orange
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(31 downto 28) <= sgl_debug(3 downto 0);
+-- debug(32) <= dl_rx_port_mux(1);
+-- debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- debug(19..0) are on INTCOM