Empty: out std_logic; Full: out std_logic);
end component;
+ signal buf_empty_out, buf_full_out : std_logic;
+
BEGIN
FIFO_DP_BRAM : lattice_ecp2m_fifo_16bit_dualport
port map (
Reset => fifo_gsr_in,
RPReset => '0',
Q => read_data_out,
- Empty => empty_out,
- Full => full_out
+ Empty => buf_empty_out,
+ Full => buf_full_out
);
-almost_empty_out <= empty_out;
-almost_full_out <= full_out;
+almost_empty_out <= buf_empty_out;
+almost_full_out <= buf_full_out;
fifostatus_out <= (others => '0');
valid_read_out <= '0';
end architecture trb_net_fifo_16bit_bram_dualport_arch;