pexor kernel module update regarding iowrite read operations

diff --git a/pexor/kernel-module/pexor_trb.c b/pexor/kernel-module/pexor_trb.c
index a8f9e74011014b3a44fe287183736c9e4c5763b0..716d657b6c102772ef322d9f21dfb911e929aa8c 100644 (file)
--- a/pexor/kernel-module/pexor_trb.c
+++ b/pexor/kernel-module/pexor_trb.c
@@ -24,14 +24,14 @@
 //#define PEXOR_TRB_DEBUG
 
 #ifdef PEXOR_DEBUGPRINT
-#define pexor_dbg( args... ) \
+#define pexor_dbg( args... )  \
   printk( args );
 #else
 #define pexor_dbg( args... ) ;
 #endif
 
 
-#define pexor_msg( args... ) \
+#define pexor_msg( args... )  \
   printk( args );
 
 /* ---------------------------------------------------------------------- */
@@ -720,7 +720,7 @@ ssize_t pexor_read(struct file*  filp,
   *f_pos += count;
   retval = count;
 
-out_read:
+ out_read:
   up(&privdata->sem);
   return retval;
 }
@@ -755,7 +755,7 @@ ssize_t pexor_write(struct file*  filp,
   *f_pos += count;
   retval = count;
 
-out_read:
+ out_read:
   up(&privdata->sem);
   return retval;
 }
@@ -810,12 +810,18 @@ int pexor_mmap(struct file* filp,
   return 0;
 }
 
+inline static void iowrite32_mb(u32 val, void __iomem *addr)
+{
+  iowrite32be(val, addr);
+  wmb();
+}
+
 int pexor_ioctl_read_register(struct pexor_privdata* priv, 
                               unsigned long arg)
 {
   int retval = 0;
   u32* ad = 0;
-  u32 val = 0;
+  volatile u32 val = 0;
   int bar = 0;
   struct pexor_reg_io descriptor;
   
@@ -850,7 +856,7 @@ int pexor_ioctl_read_register(struct pexor_privdata* priv,
   }
   ad = (u32* ) ((unsigned long)priv->iomem[bar] + (unsigned long)ad);
 
-  val = ioread32(ad);
+  val = ioread32be(ad);
   rmb();
   ndelay(20);
   pexor_dbg(KERN_NOTICE
@@ -905,8 +911,7 @@ int pexor_ioctl_write_register(struct pexor_privdata* priv,
   pexor_dbg(KERN_NOTICE
             "** pexor_ioctl_write_register writes value %x to mapped "
             "PCI address %p !\n", val, ad);
-  iowrite32(val, ad);
-  wmb();
+  iowrite32_mb(val, ad);
   ndelay(20);
   
  OUT_WRITE_REG:
@@ -1166,7 +1171,8 @@ static int pexor_copy_fifo_to_dma(struct pexor_privdata* priv,
     for (i = 0; i < sg_length; i++) {
       timeout = 0;
       do {
-        val = ioread32(priv->pexor.trbnet_receiver_data[channel]);
+        val = ioread32be(priv->pexor.trbnet_receiver_data[channel]);
+        rmb();
         if ((val & MASK_FIFO_TRB_ACT) == 0) {
           pexor_read_buffer_ctr += ctr * 4;
           return ctr;
@@ -1223,17 +1229,15 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
   case PEXOR_TRBNETCOM_REG_WRITE:
     // first send trbnet request
     iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-    iowrite32(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
-    iowrite32((descriptor.arg0 >> 16) & 0xffff,
-              priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg0 & 0xffff, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    wmb();
+    iowrite32_mb(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb((descriptor.arg0 >> 16) & 0xffff,
+                 priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg0 & 0xffff, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
     ndelay(20);
-    iowrite32((((u32) descriptor.trb_address << 16) |
-               PEXOR_TRB_CMD_REGISTER_WRITE),
-              priv->pexor.trbnet_sender_ctl[3]);
-    wmb();
+    iowrite32_mb((((u32) descriptor.trb_address << 16) |
+                  PEXOR_TRB_CMD_REGISTER_WRITE),
+                 priv->pexor.trbnet_sender_ctl[3]);
     ndelay(20);
     break;
 
@@ -1250,24 +1254,22 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
       
       // first send trbnet request
       iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-      iowrite32(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
-      iowrite32(descriptor.arg0, priv->pexor.trbnet_sender_data[3]);
-      iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-      iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
+      iowrite32_mb(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
+      iowrite32_mb(descriptor.arg0, priv->pexor.trbnet_sender_data[3]);
+      iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+      iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
       for (i = 0; (i < descriptor.arg1) && (i < PEXOR_MEMWRITE_SIZE); i++) {
-        iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-        iowrite32((priv->memwrite_buffer[i] >> 16) & 0xffff,
-                  priv->pexor.trbnet_sender_data[3]);
-        iowrite32(priv->memwrite_buffer[i] & 0xffff,
-                  priv->pexor.trbnet_sender_data[3]);
-        iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
+        iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+        iowrite32_mb((priv->memwrite_buffer[i] >> 16) & 0xffff,
+                     priv->pexor.trbnet_sender_data[3]);
+        iowrite32_mb(priv->memwrite_buffer[i] & 0xffff,
+                     priv->pexor.trbnet_sender_data[3]);
+        iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
       }
-      wmb();
       ndelay(20);
-      iowrite32((((u32) descriptor.trb_address << 16) |
-                 PEXOR_TRB_CMD_REGISTER_WRITE_MEM),
-                priv->pexor.trbnet_sender_ctl[3]);
-      wmb();
+      iowrite32_mb((((u32) descriptor.trb_address << 16) |
+                    PEXOR_TRB_CMD_REGISTER_WRITE_MEM),
+                   priv->pexor.trbnet_sender_ctl[3]);
       ndelay(20);
     }
     break;
@@ -1275,90 +1277,81 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
   case PEXOR_TRBNETCOM_REG_READ:
     // first send trbnet request
     iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-    iowrite32(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    wmb();
+    iowrite32_mb(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
     ndelay(20);
-    iowrite32((((u32) descriptor.trb_address << 16) |
-               PEXOR_TRB_CMD_REGISTER_READ),
-              priv->pexor.trbnet_sender_ctl[3]);
-    wmb();
+    iowrite32_mb((((u32) descriptor.trb_address << 16) |
+                  PEXOR_TRB_CMD_REGISTER_READ),
+                 priv->pexor.trbnet_sender_ctl[3]);
     ndelay(20);    
     break;
     
   case PEXOR_TRBNETCOM_REG_READ_MEM:
     // first send trbnet request
     iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-    iowrite32(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg0, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    wmb();
+    iowrite32_mb(descriptor.reg_address, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg0, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
     ndelay(20);    
-    iowrite32((((u32) descriptor.trb_address << 16) |
-               PEXOR_TRB_CMD_REGISTER_READ_MEM),
-              priv->pexor.trbnet_sender_ctl[3]);
-    wmb();
+    iowrite32_mb((((u32) descriptor.trb_address << 16) |
+                  PEXOR_TRB_CMD_REGISTER_READ_MEM),
+                 priv->pexor.trbnet_sender_ctl[3]);
     ndelay(20);
     break;
 
   case PEXOR_TRBNETCOM_READ_UID:
     // first send trbnet request
     iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-    iowrite32(PEXOR_TRB_NET_READUNIQUEID, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    wmb();
+    iowrite32_mb(PEXOR_TRB_NET_READUNIQUEID, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
     ndelay(20);
-    iowrite32((((u32) descriptor.trb_address << 16) |
-               PEXOR_TRB_CMD_NETADMINISTRATION),
-              priv->pexor.trbnet_sender_ctl[3]);
-    wmb();
+    iowrite32_mb((((u32) descriptor.trb_address << 16) |
+                  PEXOR_TRB_CMD_NETADMINISTRATION),
+                 priv->pexor.trbnet_sender_ctl[3]);
     ndelay(20);
     break;
 
   case PEXOR_TRBNETCOM_SET_ADDRESS:
     // first send trbnet request
     iowrite32(0x00000000, priv->pexor.trbnet_sender_err[3]);
-    iowrite32(PEXOR_TRB_NET_SETADDRESS, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg0 & 0xffff, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg0 >> 16 & 0xffff,
-              priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg1 & 0xffff, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg1 >> 16 & 0xffff,
-              priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.arg2, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(descriptor.trb_address, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0x00000000, priv->pexor.trbnet_sender_data[3]);
-    iowrite32(0xffff0000 | PEXOR_TRB_CMD_NETADMINISTRATION,
-              priv->pexor.trbnet_sender_ctl[3]);
+    iowrite32_mb(PEXOR_TRB_NET_SETADDRESS, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg0 & 0xffff, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg0 >> 16 & 0xffff,
+                 priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg1 & 0xffff, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg1 >> 16 & 0xffff,
+                 priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.arg2, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(descriptor.trb_address, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0x00000000, priv->pexor.trbnet_sender_data[3]);
+    iowrite32_mb(0xffff0000 | PEXOR_TRB_CMD_NETADMINISTRATION,
+                 priv->pexor.trbnet_sender_ctl[3]);
     break;
 
   case PEXOR_TRBNETCOM_IPU_DATA_READ:
-    iowrite32(((descriptor.arg1 & 0xff) << 24) | (descriptor.arg2 & 0xffffff),
-              priv->pexor.trbnet_sender_err[1]);
-    wmb();
+    iowrite32_mb(((descriptor.arg1 & 0xff) << 24) | (descriptor.arg2 & 0xffffff),
+                 priv->pexor.trbnet_sender_err[1]);
     ndelay(20);
-    iowrite32((descriptor.arg0 & 0x0f) | PEXOR_TRB_CMD_SHORT_TRANSFER,
-              priv->pexor.trbnet_sender_ctl[1]);
-    wmb();
+    iowrite32_mb((descriptor.arg0 & 0x0f) | PEXOR_TRB_CMD_SHORT_TRANSFER,
+                 priv->pexor.trbnet_sender_ctl[1]);
     ndelay(20);
     channel = 1;
     break;
 
   case PEXOR_TRBNETCOM_SEND_TRIGGER:
-    iowrite32(((descriptor.arg1 & 0xff) << 24) | (descriptor.arg2 & 0xffffff),
-              priv->pexor.trbnet_sender_err[0]);
-    iowrite32((descriptor.arg1 >> 8) & 0xffff,
-              priv->pexor.trbnet_sender_trigger_info);
-    wmb();
+    iowrite32_mb(((descriptor.arg1 & 0xff) << 24) | 
+                 (descriptor.arg2 & 0xffffff),
+                 priv->pexor.trbnet_sender_err[0]);
+    iowrite32_mb((descriptor.arg1 >> 8) & 0xffff,
+                 priv->pexor.trbnet_sender_trigger_info);
     ndelay(20);
-    iowrite32((descriptor.arg0 & 0x0f) | PEXOR_TRB_CMD_SHORT_TRANSFER,
-              priv->pexor.trbnet_sender_ctl[0]);
-    wmb();
+    iowrite32_mb((descriptor.arg0 & 0x0f) | PEXOR_TRB_CMD_SHORT_TRANSFER,
+                 priv->pexor.trbnet_sender_ctl[0]);
     ndelay(20);
     channel = 0;
     break;
@@ -1373,10 +1366,11 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
     /* only channel 3 supports DMA */
     
     /* Credential check */
-    u32 cred1;
-    u32 cred2;
-    cred1 = ioread32(priv->pexor.dma_debug2);
-    
+    volatile u32 cred1;
+    volatile u32 cred2;
+    cred1 = ioread32be(priv->pexor.dma_debug2);
+    rmb();
+
     pexor_read_buffer_ctr = 0;
 
     /* Start DMA transfer */
@@ -1391,14 +1385,14 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
                                  DMA_FROM_DEVICE);
       mb();
 
-      iowrite32(sg_dma_address(&priv->dma.sglist[sg_ctr]),
-                priv->pexor.dma_dest);
-      iowrite32(sg_dma_len(&priv->dma.sglist[sg_ctr]) / 4,
-                priv->pexor.dma_len);
-      wmb();
+      iowrite32_mb(sg_dma_address(&priv->dma.sglist[sg_ctr]),
+                   priv->pexor.dma_dest);
+      iowrite32_mb(sg_dma_len(&priv->dma.sglist[sg_ctr]) / 4,
+                   priv->pexor.dma_len);
+
       /* wait for dma complete */
       for (loops = 0; loops < PEXOR_DMA_MAXPOLLS; loops++) {
-        dmastat = ioread32(priv->pexor.dma_control_stat);
+        dmastat = ioread32be(priv->pexor.dma_control_stat);
         rmb();
         if ((dmastat & PEXOR_TRB_BIT_DMA_FINISHED) != 0) {
           /* DMA is completed */
@@ -1420,7 +1414,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
                     "Status: 0x%08x\n",
                     (unsigned int)dmastat);
           /* reset DMA */
-          iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
+          iowrite32_mb(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
           ndelay(1000);
           /* do we need to flush the fifo-buffer, no libtrbnet takes care */
           status = -201;
@@ -1443,7 +1437,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
                   PEXOR_DMA_MAXPOLLS, PEXOR_DMA_POLLDELAY,
                   (unsigned int)dmastat);
         /* reset DMA */
-        iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
+        iowrite32_mb(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
         ndelay(1000);
         /* do we need to flush the fifo-buffer, no libtrbnet takes care */
         status = -202;
@@ -1460,7 +1454,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
         pexor_msg(KERN_ERR
                   "ERROR> no more DMA buffers available, aborting DMA\n");
         /* reset DMA */
-        iowrite32(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
+        iowrite32_mb(PEXOR_TRB_DMA_RESET, priv->pexor.dma_control_stat);
         ndelay(1000);
         /* do we need to flush the fifo-buffer, no libtrbnet takes care */
         status = -203;
@@ -1488,7 +1482,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
     }
 
     /* Check Credentials */
-    cred2 = ioread32(priv->pexor.dma_debug2);
+    cred2 = ioread32be(priv->pexor.dma_debug2);
     rmb();
     if (cred2 != cred1) {
       pexor_msg(KERN_ERR 
@@ -1504,8 +1498,8 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
       pexor_msg(KERN_ERR "DMA: dmaSize: %d   pexor_read_buffer_ctr: %d\n",
                 dmaSize, (int)pexor_read_buffer_ctr);
       for (i = 0; i < dmaSize; i++) {
-        u32 val = 0;
-        val = ioread32((i % 2 == 0)
+        volatile u32 val = 0;
+        val = ioread32be((i % 2 == 0)
                        ? priv->pexor.dma_debug0 : priv->pexor.dma_debug1);
         rmb();
         pexor_msg(KERN_ERR "DMA: %d 0x%08x   DEBUG:0x%08x\n", i,
@@ -1524,7 +1518,7 @@ int pexor_ioctl_trbnet_request(struct pexor_privdata* priv,
     }
   }
   
-OUT_IOCTL:
+ OUT_IOCTL:
   spin_unlock((&(priv->dma_lock)));
   return status;
 }