development status 0

diff --git a/cores/pmi_fifo_dcEEan163201024102410241818p12701671.ngo b/cores/pmi_fifo_dcEEan163201024102410241818p12701671.ngo
new file mode 100644 (file)
index 0000000..4127c97
Binary files /dev/null and b/cores/pmi_fifo_dcEEan163201024102410241818p12701671.ngo differ

diff --git a/cores/pmi_fifo_dcLEan71301616161010p11f296ee.ngo b/cores/pmi_fifo_dcLEan71301616161010p11f296ee.ngo
new file mode 100644 (file)
index 0000000..0f5e1ad
Binary files /dev/null and b/cores/pmi_fifo_dcLEan71301616161010p11f296ee.ngo differ

diff --git a/cores/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo b/cores/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo
index 52aaa2b95a2aa952a82f99f1f02be3ccb0b84792..43684e4e4168799b23d34aba623673b5d6211182 100644 (file)
Binary files a/cores/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo and b/cores/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo differ

diff --git a/cores/serdes_gbe.lpc b/cores/serdes_gbe.lpc
new file mode 100644 (file)
index 0000000..5aac97f
--- /dev/null
+++ b/cores/serdes_gbe.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um5g
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM5G-85F-8BG381C
+PartType=LFE5UM5G-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=06/27/2022
+ModuleName=serdes_gbe
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=13:46:14
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=SGMII
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Disabled
+PPORT_TX_RDY=Disabled
+PROTOCOL=SGMII
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Disabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M1-S1
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Disabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1000
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_gbe.pp=pp
+serdes_gbe.sym=sym
+serdes_gbe.tft=tft
+serdes_gbe.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH0

diff --git a/cores/serdes_gbe.vhd b/cores/serdes_gbe.vhd
index 0ded55e4c6bca6bda5ac048eae886513f7cc8ccb..a2fb73089e2493e7021db3f73417bf3e9bf2d9dc 100644 (file)
--- a/cores/serdes_gbe.vhd
+++ b/cores/serdes_gbe.vhd
@@ -61,11 +61,11 @@ end entity serdes_gbe;
 architecture v1 of serdes_gbe is 
     component serdes_gbesll_core is
         generic (PPROTOCOL: string := "SGMII";
-            PLOL_SETTING: integer := 0;
+            PLOL_SETTING: integer := 1;
             PDYN_RATE_CTRL: string := "DISABLED";
-            PPCIE_MAX_RATE: string := "2.5";
+            PPCIE_MAX_RATE: string := "1.25";
             PDIFF_VAL_LOCK: integer := 20;
-            PDIFF_VAL_UNLOCK: integer := 39;
+            PDIFF_VAL_UNLOCK: integer := 131;
             PPCLK_TC: integer := 65536;
             PDIFF_DIV11_VAL_LOCK: integer := 0;
             PDIFF_DIV11_VAL_UNLOCK: integer := 0;
@@ -100,7 +100,7 @@ begin
     tx_pclk <= tx_pclk_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b0",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
@@ -113,14 +113,14 @@ begin
         CH0_MATCH_4_ENABLE=>"0b0",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x000",
         CH0_CC_MATCH_2=>"0x000",CH0_CC_MATCH_3=>"0x000",CH0_CC_MATCH_4=>"0x000",
         CH0_UDF_COMMA_MASK=>"0x3ff",CH0_UDF_COMMA_A=>"0x283",CH0_UDF_COMMA_B=>"0x17C",
-        CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
-        CH0_RATE_MODE_TX=>"0b1",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
+        CH0_RX_DCO_CK_DIV=>"0b010",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
+        CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
         CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b01",CH0_TDRV_SLICE1_SEL=>"0b00",
         CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",
-        CH0_TDRV_SLICE5_SEL=>"0b01",CH0_TDRV_SLICE0_CUR=>"0b101",CH0_TDRV_SLICE1_CUR=>"0b000",
+        CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b011",CH0_TDRV_SLICE1_CUR=>"0b000",
         CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b11",
         CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0",
-        CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b1",CH0_RX_DIV11_SEL=>"0b0",
+        CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0",
         CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0",
         CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0",
         CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00",
@@ -128,8 +128,8 @@ begin
         CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
         CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
         CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
-        CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2.5",CH0_CDR_MAX_RATE=>"2.5",
-        CH0_TXAMPLITUDE=>"0d1100",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
+        CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH0_CDR_MAX_RATE=>"1.25",
+        CH0_TXAMPLITUDE=>"0d1000",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
         CH0_PROTOCOL=>"SGMII",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
         D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
         D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00",
@@ -145,7 +145,7 @@ begin
         D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
         D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
         D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d8",
-        D_REFCK_MODE=>"0b000",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b00",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b01",
         D_RG_EN=>"0b0",D_RG_SET=>"0b00")
      port map (CH0_HDINP=>hdinp,CH1_HDINP=>n115,CH0_HDINN=>hdinn,CH1_HDINN=>n115,
     D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,

diff --git a/cores/sgmii_gbe.lpc b/cores/sgmii_gbe.lpc
new file mode 100644 (file)
index 0000000..d37f4c5
--- /dev/null
+++ b/cores/sgmii_gbe.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00g
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM5G-85F-8BG381C
+PartType=LFE5UM5G-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=SGMII/Gb Ethernet PCS
+CoreRevision=4.2
+CoreStatus=Demo
+CoreType=IPCFG
+Date=06/27/2022
+ModuleName=sgmii_gbe
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=13:46:42
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+CH_MODE=Rx and Tx
+CORE_SYNP=1
+Channel=CH0
+DCUA=DCU0
+EasyConnect=1
+MAX_RATE=1.250
+NUM_CHS=1
+PROTOCOL=SGMII
+REFCLK_RATE=125.0000
+RX_CTC=2
+RX_CTC_HIGH=32
+RX_CTC_LOW=16
+SBP=1
+SOFTLOL=Enabled
+TX_MAX_RATE=2.5
+[SYSTEMPNR]
+LN0=DCU0_CH0

diff --git a/cores/sgmii_gbe_core.ngo b/cores/sgmii_gbe_core.ngo
index 99b5fc91d8ecfc2d46e6994cafccdb117d6d73e4..7ad45c66c0414e644d8c102859c48914bc5a348d 100644 (file)
Binary files a/cores/sgmii_gbe_core.ngo and b/cores/sgmii_gbe_core.ngo differ

diff --git a/cores/tsmac_gbe.lpc b/cores/tsmac_gbe.lpc
new file mode 100644 (file)
index 0000000..43794b8
--- /dev/null
+++ b/cores/tsmac_gbe.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00g
+PartType=LFE5UM5G-85F
+PartName=LFE5UM5G-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=IPCFG
+CoreStatus=Demo
+CoreName=Tri-Speed Ethernet MAC
+CoreRevision=4.1
+ModuleName=tsmac_gbe
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/27/2022
+Time=13:47:01
+
+[Parameters]
+MIIM=No
+MODE=Gbit MAC
+MODS_TOOL=0
+ALDC_TOOL=0
+MULT_WB=NO
+LOOPBACK=NO
+STAT_REGS=NO
+CORE_SYNP=1
+
+[Files]
+Synthesis=
+Simulation=
+Logical=
+Physical=
+Misc=

diff --git a/cores/tsmac_gbe.ngo b/cores/tsmac_gbe.ngo
index 5c032abc9854071d89cdc9e53329b8140ce8b9c9..33bffa804d7513058eabdb55d26cae19bf7fb176 100644 (file)
Binary files a/cores/tsmac_gbe.ngo and b/cores/tsmac_gbe.ngo differ

diff --git a/gbe/tomcat_gbe.lpf b/gbe/tomcat_gbe.lpf
index 13d212b04d1c1f60e32046d6c30882ece65c4a86..10feea9f9584033cde43f28cc16ad9199e649974 100644 (file)
--- a/gbe/tomcat_gbe.lpf
+++ b/gbe/tomcat_gbe.lpf
@@ -34,3 +34,6 @@ GSR_NET NET "clear_i";
 REGION               "MEDIA" "R81C44D" 13 25;
 LOCATE UGROUP        "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
 
+FREQUENCY NET "GBE/clk_125_rx_from_pcs"            125.000 MHz;
+FREQUENCY NET "CLK_125_c"                          125.000 MHz;
+FREQUENCY NET "GBE/physical/gbe_serdes/tx_pclk"    125.000 MHz;

diff --git a/gbe/tomcat_gbe.prj b/gbe/tomcat_gbe.prj
index ed6c19928267e0a98bcbaa56a0efdbff4b1d6109..2e809902852e5c5036987f22f6aa37b3194afcd0 100644 (file)
--- a/gbe/tomcat_gbe.prj
+++ b/gbe/tomcat_gbe.prj
@@ -238,9 +238,11 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in12
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
 #GbE
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_single_5G.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_single_5G.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
@@ -269,6 +271,8 @@ add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
 add_file -vhdl -lib work "../../TOMcat/cores/serdes_gbe.vhd"
 add_file -verilog -lib work "../../TOMcat/cores/serdes_gbe_softlogic.v"
 
+
+
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"

diff --git a/gbe/tomcat_gbe.vhd b/gbe/tomcat_gbe.vhd
index 6d1048cbd53c269f528076e39490810df926a08e..772206142e80a3b37e2da4d0ad3b446afdc06484 100644 (file)
--- a/gbe/tomcat_gbe.vhd
+++ b/gbe/tomcat_gbe.vhd
@@ -188,7 +188,7 @@ begin
 -------------------------------------------------------------------------------
 -- GbE interface
 -------------------------------------------------------------------------------
-  GBE : entity work.gbe_wrapper_5G
+  GBE : entity work.gbe_wrapper_single_5G
     generic map(
       DO_SIMULATION             => 0,
       INCLUDE_DEBUG             => 0,
@@ -203,7 +203,7 @@ begin
       UP_DOWN_LIMIT             => 100,
       FIXED_DELAY               => 100,
 
-      NUMBER_OF_GBE_LINKS       => 4,
+      NUMBER_OF_GBE_LINKS       => 1,
       LINKS_ACTIVE              => "0001",
 
       LINK_HAS_READOUT          => "0000",
@@ -221,9 +221,9 @@ begin
       -- Trigger
       TRIGGER_IN               => '0', --cts_rdo_rx.data_valid,
       -- SFP
-      SD_PRSNT_N_IN(0)         => SFP_MOD_0,
-      SD_LOS_IN(0)             => SFP_LOS,
-      SD_TXDIS_OUT(0)          => SFP_TX_DIS,
+      SD_PRSNT_N_IN            => SFP_MOD_0,
+      SD_LOS_IN                => SFP_LOS,
+      SD_TXDIS_OUT             => SFP_TX_DIS,
       -- trigger channel
       CTS_NUMBER_IN            => (others => '0'), --gbe_cts_number,          
       CTS_CODE_IN              => (others => '0'), --gbe_cts_code,            

diff --git a/pinout/tomcat_prototype.lpf b/pinout/tomcat_prototype.lpf
index 8c542ff58778926478f03067a7e25abaf915add1..532d231a68dc1528d2b2c13bd0bda85d6c2c2b95 100644 (file)
--- a/pinout/tomcat_prototype.lpf
+++ b/pinout/tomcat_prototype.lpf
@@ -54,7 +54,7 @@ LOCATE COMP  "I2C_SCL"         SITE "L1" ;
 IOBUF  PORT  "I2C_SCL"         IO_TYPE=LVCMOS33 ;
 
 LOCATE COMP  "PROGRAMN"        SITE "V1";
-IOBUF  PORT  "PROGRAMN"        IO_TYPE=LVCMOS33 PULLMODE=UP DRIVE="8" ;
+IOBUF  PORT  "PROGRAMN"        IO_TYPE=LVCMOS33 DRIVE="8" ;
 
 LOCATE COMP  "FLASH_HOLD"      SITE "W1" ;
 IOBUF  PORT  "FLASH_HOLD"      IO_TYPE=LVCMOS33 PULLMODE=NONE ;