end process;
MED_READ_OUT <= reg_read_out;
-
+
reg_buffer: process(CLK)
begin
if rising_edge(CLK) then
fifo_read <= '0';
got_locked <= is_locked;
next_last_header <= current_last_header;
-
+
if fifo_empty = '0' then
if sbuf_free = '1' and fifo_data_out(TYPE_POSITION) = TYPE_DAT then
-- next data word can be registered
end process;
--BUGBUG HDR retransmit needed
-
+
release_locked <= CTRL_LOCKED(0);
STAT_LOCKED(0) <= is_locked;
STAT_LOCKED(15 downto 1) <= (others => '0');
-
+
reg_locked: process(CLK)
begin
if rising_edge(CLK) then
entity trb_net_iobuf is
generic (
--- INIT_DEPTH : integer := 0;
+ SWITCH_OFF_BUFFER_CHECK : integer := 0;
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
REPLY_DEPTH : integer := 3); -- or the replyibuf
component trb_net_obuf is
generic (
- DATA_COUNT_WIDTH : integer := 4);
+ DATA_COUNT_WIDTH : integer := 4;
+ SWITCH_OFF_BUFFER_CHECK : integer := 0
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ );
port(
-- Misc
CLK : in std_logic;
INITOBUF : trb_net_obuf
generic map (
- DATA_COUNT_WIDTH => 16)
+ DATA_COUNT_WIDTH => 16,
+ SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ )
port map (
CLK => CLK,
RESET => RESET,
REPLYOBUF : trb_net_obuf
generic map (
- DATA_COUNT_WIDTH => 16)
+ DATA_COUNT_WIDTH => 16,
+ SWITCH_OFF_BUFFER_CHECK => SWITCH_OFF_BUFFER_CHECK
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ )
port map (
CLK => CLK,
RESET => RESET,
--Entity decalaration for clock generator
entity trb_net_obuf is
generic (
- DATA_COUNT_WIDTH : integer := 4);
-
+ DATA_COUNT_WIDTH : integer := 4;
+ SWITCH_OFF_BUFFER_CHECK : integer := 0
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ );
port(
-- Misc
CLK : in std_logic;
--finally, block data read if the rec buffer is full
if sent_data = '0' or
- (next_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0)) or
- next_TRANSMITTED_BUFFERS(1) = '1'
- then
+ (next_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0))
+ or (next_TRANSMITTED_BUFFERS(1) = '1' and SWITCH_OFF_BUFFER_CHECK = 0)
+ then
next_INT_READ_OUT <= '0';
end if;
--In any case: if sbuf not free, then we stop data taking
current_NOP_word(47 downto 0) <= (others => '0');
current_DATA_word(50 downto 0) <= INT_DATA_IN;
- sent_DATA <= not TRANSMITTED_BUFFERS(1);
+ sent_DATA <= '1' when (TRANSMITTED_BUFFERS(1) = '0' or SWITCH_OFF_BUFFER_CHECK = 1) else '0';
-- generate max_DATA_COUNT, comb. operation which should be registered
-- next_max_DATA_COUNT <= "0000000000000100" when REC_BUFFER_SIZE_IN="0001" else
component trb_net_iobuf is
- generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
+ generic (SWITCH_OFF_BUFFER_CHECK : integer := 0;
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if
-- the initibuf
REPLY_DEPTH : integer := 3); -- or the replyibuf
IOBUF: trb_net_iobuf
- generic map (INIT_DEPTH => INIT_DEPTH,
+ generic map (SWITCH_OFF_BUFFER_CHECK => 0,
+ --switching off erroneous output buffer counter. MUST ONLY be
+ --used for short transfers!!!!
+ INIT_DEPTH => INIT_DEPTH,
REPLY_DEPTH => REPLY_DEPTH)
port map (
if trigger_num_is_read = '1' and trigger_time_is_read = '1' then
next_trigger_num_is_read <= '0';
next_trigger_time_is_read <= '0';
- next_fifo_read <= '1';
+ fifo_read <= '1';
next_TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR;
end if;