D_OUT(2) => rx_allow_del
);
- THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => rx_allow,
- CLK0 => CLK,
- CLK1 => ff_rxfullclk,
- D_OUT(0) => rx_allow_qrx
- );
+ THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow,
+ CLK0 => CLK,
+ CLK1 => ff_rxfullclk,
+ D_OUT(0) => rx_allow_qrx
+ );
--LED Signals
---------------------
architecture trb_net16_med_ecp_fot_4_arch of trb_net16_med_ecp_fot_4 is
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of trb_net16_med_ecp_fot_4_arch : architecture is "GROUP_PCS";
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_med_ecp_fot_4_arch : architecture is "GROUP_PCS";
attribute syn_sharing : string;
- attribute syn_sharing of trb_net16_med_ecp_fot_4_arch : architecture is "off";
+ attribute syn_sharing of trb_net16_med_ecp_fot_4_arch : architecture is "false";
+
component serdes_fot_full_quad is
generic(
signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
signal sfp_los : std_logic_vector(3 downto 0);
- type led_counter_t is array(0 to 3) of std_logic_vector(15 downto 0);
- signal led_counter : led_counter_t;
+-- type led_counter_t is array(0 to 3) of std_logic_vector(15 downto 0);
+ signal led_counter : std_logic_vector(15 downto 0);
signal rx_led : std_logic_vector(3 downto 0);
signal tx_led : std_logic_vector(3 downto 0);
signal FSM_STAT_DEBUG : std_logic_vector(4*64-1 downto 0);
signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0);
+ attribute syn_keep : boolean;
+ attribute syn_keep of led_counter : signal is true;
+
begin
THE_SERDES: serdes_fot_full_quad
THE_TX_RX_LED_PROC: process( clk )
begin
if( rising_edge(CLK) ) then
- led_counter(i) <= led_counter(i) + 1;
if ( buf_med_dataready_out(i) = '1' ) then
rx_led(i) <= '1';
- elsif( led_counter(i) = 0 ) then
+ elsif( led_counter = 0 ) then
rx_led(i) <= '0';
end if;
if( tx_fifo_valid_read_q(i) = '1') then
tx_led(i) <= '1';
- elsif led_counter(i) = 0 then
+ elsif led_counter = 0 then
tx_led(i) <= '0';
end if;
end if;
STAT_DEBUG(i*64+48 downto i*64+41) <= last_rx_fifo_dout(i*8+7 downto i*8);
STAT_DEBUG(i*64+63 downto i*64+49) <= (others => '0');
- PROC_LED : process(CLK_25)
+ PROC_DEBUG_OUT : process(CLK_25)
begin
if rising_edge(CLK_25) then
buf_rx_data_reg <= rx_data_reg;
end generate;
+ PROC_LED_COUNTER : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ led_counter <= led_counter + 1;
+ end if;
+ end process;
gen_lsm : for i in 0 to 3 generate
THE_SFP_LSM: trb_net16_lsm_sfp
signal sfp_los : std_logic_vector(3 downto 0); -- synchronized input signals
- type led_counter_t is array(0 to 3) of std_logic_vector(15 downto 0);
- signal led_counter : led_counter_t;
+ signal led_counter : std_logic_vector(16 downto 0);
signal rx_led, tx_led : std_logic_vector(3 downto 0);
-
+ attribute syn_keep : boolean;
+ attribute syn_keep of led_counter : signal is true;
begin
THE_TX_RX_LED_PROC: process( SYSCLK )
begin
if( rising_edge(SYSCLK) ) then
- led_counter(i) <= led_counter(i) + 1;
+
if ( buf_med_dataready_out(i) = '1' ) then
rx_led(i) <= '1';
- elsif( led_counter(i) = 0 ) then
+ elsif( led_counter = 0 ) then
rx_led(i) <= '0';
end if;
if( last_fifo_tx_empty(i) = '0') then
tx_led(i) <= '1';
- elsif led_counter(i) = 0 then
+ elsif led_counter = 0 then
tx_led(i) <= '0';
end if;
end if;
STAT_DEBUG(i*64+47 downto i*64+32) <= rx_data(i*16+15 downto i*16);
STAT_DEBUG(i*64+57 downto i*64+48) <= link_error(i);
STAT_DEBUG(i*64+58) <= ffs_plol;
- STAT_DEBUG(i*64+63 downto i*64+59) <= (others => '0');
+ STAT_DEBUG(i*64+60 downto i*64+59) <= rx_k_q(i*2+1 downto i*2);
+ STAT_DEBUG(i*64+63 downto i*64+61) <= (others => '0');
end generate;
+
+ PROC_LED_COUNTER : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ led_counter <= led_counter + 1;
+ end if;
+ end process;
+
-- fsm_stat_debug(3 downto 0) <= state_bits;
-- fsm_stat_debug(4) <= align_me;
-- fsm_stat_debug(5) <= buf_swap_bytes;
# TIMEGRP "TLK_RX" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "TLK_RX_CLK";
-INST "ADO_LV_IN<*>" TNM = "VIRT_CLK_IN";
-INST "ADO_LV_OUT<*>" TNM = "VIRT_CLK_OUT";
-TIMEGRP "VIRT_CLK_OUT" OFFSET = OUT 9 ns AFTER "VIRT_CLK" HIGH;
-TIMEGRP "VIRT_CLK_IN" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "VIRT_CLK";
\ No newline at end of file
+#INST "ADO_LV_IN<*>" TNM = "VIRT_CLK_IN";
+#INST "ADO_LV_OUT<*>" TNM = "VIRT_CLK_OUT";
+#TIMEGRP "VIRT_CLK_OUT" OFFSET = OUT 9 ns AFTER "VIRT_CLK" HIGH;
+#TIMEGRP "VIRT_CLK_IN" OFFSET = IN 3.2 ns VALID 6 ns BEFORE "VIRT_CLK";
\ No newline at end of file
type PAS_API_TO_APL_STATE_T is (sa_IDLE, sa_INACTIVE, sa_WRONG_ADDR, sa_MY_ADDR);
signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T;
- type state_to_int_t is ( INACTIVE, IDLE, SEND_SHORT, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN);
+ type state_to_int_t is ( INACTIVE, IDLE, SEND_HEADER, RUNNING, SEND_TRAILER, SHUTDOWN);
signal state_to_int, next_state_to_int : state_to_int_t;
-- type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR);
if slave_start = '1' then
next_state_to_int <= IDLE;
elsif send_trm_wrong_addr = '1' then
- next_state_to_int <= SEND_SHORT;
+ next_state_to_int <= SEND_TRAILER;
end if;
else --API_TYPE = 1
if state_to_apl = sa_INACTIVE then
end if;
end if;
- when SEND_SHORT =>
- if APL_SEND_IN = '0' then
- next_state_to_int <= SEND_TRAILER;
- update_registered_trailer <= '1';
- end if;
+-- when SEND_SHORT =>
+-- if APL_SEND_IN = '0' then
+-- next_state_to_int <= SEND_TRAILER;
+-- end if;
when SEND_HEADER =>
out_select <= HDR;
when SEND_HEADER => state_bits_to_int <= "001";
when RUNNING => state_bits_to_int <= "010";
when SHUTDOWN => state_bits_to_int <= "011";
- when SEND_SHORT => state_bits_to_int <= "100";
+-- when SEND_SHORT => state_bits_to_int <= "100";
when SEND_TRAILER => state_bits_to_int <= "101";
when INACTIVE => state_bits_to_int <= "110";
when others => state_bits_to_int <= "111";
component trb_net16_hub_base is
- generic (
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 3;
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
- -- settings for external api connections
- INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
- INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
- INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6)
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media interfacces
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
- --INT: interfaces to connect APIs
- INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_OUT : out std_logic;
- ONEWIRE_MONITOR_IN : in std_logic;
- --Fixed status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
- STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- --Additional access to registers
- REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0);
- REGIO_EXT_REG_WRITE_IN: in std_logic;
- REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
-
- --Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
- );
+ generic (
+ --hub control
+ HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
+ HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
+ -- settings for external api connections
+ INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
+ INT_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
+ INT_IBUF_DEPTH : hub_api_config_t := (6,6,6,6,6,6,6,6)
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ --Media interfacces
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+ --INT: interfaces to connect APIs
+ INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
+ INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
+ INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
+ INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
+ INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
+ INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
+ INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
+ INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
+ INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
+ INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
+ INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
+ INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ ONEWIRE_MONITOR_OUT : out std_logic;
+ --Fixed status and control ports
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+
+
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ );
end component;
signal saved_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_type : std_logic_vector(POINT_NUMBER*3-1 downto 0);
signal last_reply_packet_number : std_logic_vector(POINT_NUMBER*3-1 downto 0);
- signal current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_H0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F0 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal reply_reading_F1 : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0);
signal next_current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0);
--- signal reply_reading_HDR : std_logic_vector(POINT_NUMBER-1 downto 0);
--- signal reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_reply_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
--- signal reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
signal current_muxed_reading_DAT : std_logic;
+ signal reg_current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reg_current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reg_current_reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal reg_current_reply_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
--general signals
signal locked, next_locked : std_logic;
signal get_locked, release_locked : std_logic;
------------------------------
gen_read_out : for i in 0 to POINT_NUMBER-1 generate
- buf_REPLY_READ_OUT(i) <= current_reply_reading_TRM(i)
- or current_reply_reading_HDR(i)
- or current_reply_auto_reading_DHDR(i)
+ buf_REPLY_READ_OUT(i) <= reg_current_reply_reading_TRM(i) --current_reply_reading_TRM(i)
+ or reg_current_reply_reading_HDR(i) --current_reply_reading_HDR(i)
+ or current_reply_auto_reading_DHDR(i) --current_reply_auto_reading_DHDR(i)
or saved_reading_padding(i)
or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2))
or (reply_fsm_state(4) and reply_reading_H0(i));
current_reply_reading_TRM(i) <= '1' when current_reply_packet_type((i+1)*3-1 downto i*3) = TYPE_TRM else '0';
current_reply_auto_reading_DHDR(i) <= '1' when current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0'
else '0';
+
+ PROC_reading_signals : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i);
+ reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i);
+ reg_current_reply_reading_DHDR(i) <= current_reply_reading_DHDR(i);
+ reg_current_reply_auto_reading_DHDR(i) <= current_reply_auto_reading_DHDR(i);
+ end if;
+ end process;
+
end generate;
case address(0) is
when '0' =>
next_API_DATA_OUT <= global_time_i(31 downto 16);
- when '1' =>
+ when others => --'1' =>
next_API_DATA_OUT <= time_since_last_trg_i(31 downto 16);
end case;
when x"8" | x"9" | x"A" | x"B" =>
case address(0) is
when '0' =>
next_API_DATA_OUT <= global_time_i(15 downto 0);
- when '1' =>
+ when others => --'1' =>
next_API_DATA_OUT <= time_since_last_trg_i(15 downto 0);
end case;
when x"8" | x"9" | x"A" | x"B" =>
+
+
+
+
+
component adc_ltc2308_readout is
generic(
CLOCK_FREQUENCY : integer := 100 --MHz
+
+ component etrax_interface is
+ generic(
+ STATUS_REGISTERS : integer := 4;
+ CONTROL_REGISTERS : integer := 4
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ --Connection to Etrax
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ ETRAX_BUS_BUSY : out std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
+ --Connection to internal FPGA logic (all addresses above 0x100)
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ INTERNAL_READ_OUT : out std_logic;
+ INTERNAL_WRITE_OUT : out std_logic;
+ INTERNAL_DATAREADY_IN : in std_logic;
+ INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)
+ FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
+ FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
+ --Reset FPGA via Etrax
+ EXTERNAL_RESET : out std_logic
+ );
+ end component;
+
+
+
+
component trb_net16_fifo is
generic (
USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+
+
+ component trb_net16_med_8_SDR_OS is
+ generic(
+ TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ INT_DATAREADY_OUT : out std_logic;
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_IN : in std_logic;
+
+ INT_DATAREADY_IN : in std_logic;
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_READ_OUT : out std_logic;
+
+ -- Media direction port
+ TX_DATA_OUT : out std_logic_vector (7 downto 0);
+ TX_CLK_OUT : out std_logic;
+ TX_CTRL_OUT : out std_logic_vector (1 downto 0);
+ RX_DATA_IN : in std_logic_vector (7 downto 0);
+ RX_CLK_IN : in std_logic;
+ RX_CTRL_IN : in std_logic_vector (1 downto 0);
+
+ -- Status and control port
+ STAT_OP: out std_logic_vector (15 downto 0);
+ CTRL_OP: in std_logic_vector (15 downto 0);
+
+ STAT: out std_logic_vector (31 downto 0);
+ CTRL: in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+
+
+
+
+
+
component trb_net16_med_ecp_fot is
port(
CLK : in std_logic;
STAT_OP : out std_logic_vector (15 downto 0);
CTRL_OP : in std_logic_vector (15 downto 0);
STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ CTRL_DEBUG : in std_logic_vector (15 downto 0)
+ );
+ end component;
+
+
+
+
+ component trb_net16_med_ecp_fot_4 is
+ port(
+ CLK : in std_logic;
+ CLK_25 : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_READ_OUT : out std_logic_vector(3 downto 0);
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+ --SFP Connection
+ TXP : out std_logic_vector(3 downto 0);
+ TXN : out std_logic_vector(3 downto 0);
+ RXP : in std_logic_vector(3 downto 0);
+ RXN : in std_logic_vector(3 downto 0);
+ SD : in std_logic_vector(3 downto 0);
+ -- Status and control port
+ STAT_OP : out std_logic_vector (63 downto 0);
+ CTRL_OP : in std_logic_vector (63 downto 0);
+ STAT_DEBUG : out std_logic_vector (255 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
);
end component;
+ component trb_net16_med_tlk is
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector(15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector(15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ STAT : out std_logic_vector (63 downto 0);
+ STAT_MONITOR : out std_logic_vector ( 100 downto 0);
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0)
+ --connect STAT(0) to LED
+ );
+ end component;
+
+
+
+
component trb_net_onewire is
generic(
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
-
+
INT_DATAREADY_OUT : out std_logic;
INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_IN : in std_logic;
-
+
INT_DATAREADY_IN : in std_logic;
INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
component xilinx_fifo_18x16
- port (
- clk: IN std_logic;
- sinit: IN std_logic;
- din: IN std_logic_VECTOR(17 downto 0);
- wr_en: IN std_logic;
- rd_en: IN std_logic;
- dout: OUT std_logic_VECTOR(17 downto 0);
- full: OUT std_logic;
- empty: OUT std_logic
- );
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic);
end component;
-- attribute box_type of xilinx_fifo_18x16 : component is "black_box";
rd_en => READ_ENABLE_IN,
wr_en => WRITE_ENABLE_IN,
din => din,
- sinit => RESET,
+ rst => RESET,
dout => dout,
full => FULL_OUT,
empty => EMPTY_OUT
jspc29 / trbnet.git / commitdiff