signal control_reg : std_logic_vector(31 downto 0);
+ signal tick_ms_int : std_logic;
+ signal tick_us_int : std_logic;
+
begin
---------------------------------------------------------------------------
CLEAR_OUT => clear_i,
CLEAR_N_OUT => clear_n_i,
--
- TICK_MS_OUT => open, --tick_int,
- TICK_US_OUT => tick_int,
+ TICK_MS_OUT => tick_ms_int,
+ TICK_US_OUT => tick_us_int,
--
LED_RED_OUT => open,
LED_GREEN_OUT => open
-- Status
PCS_AN_READY_OUT => pcs_an_ready,
LINK_ACTIVE_OUT => link_active,
+ TICK_MS_IN => tick_us_int,
-- Debug
STATUS_OUT => status(7 downto 0),
DEBUG_OUT => open --debug(63 downto 0)
FWD_ENABLE_IN => additional_reg(31),
FWD_DELAY_IN => control_reg(31 downto 16),
-- FWD_SIZE_IN => control_reg(15 downto 0),
- FWD_START_IN => tick_int,
+ FWD_START_IN => tick_us_int,
FWD_BUSY_OUT => fwd_busy_int, --open
--
FWD_READY_IN => fwd_ready_int,