fixes

diff --git a/gbe_trb/base/gbe_med_interface_5G.vhd b/gbe_trb/base/gbe_med_interface_5G.vhd
index af30e7fceefd6833827490b455e4ec21a4cb278a..aa28c468762c4383393c8c44faedab0caae1eadb 100644 (file)
--- a/gbe_trb/base/gbe_med_interface_5G.vhd
+++ b/gbe_trb/base/gbe_med_interface_5G.vhd
@@ -64,7 +64,7 @@ end entity gbe_med_interface_5G;
 
 architecture RTL of gbe_med_interface_5G is
   
-  component sgmii_core -- checked for ECP5-5G core 
+  component sgmii_gbe_core -- checked for ECP5-5G core 
   port( 
     rst_n                  : in  std_logic;
     signal_detect          : in  std_logic;
@@ -153,7 +153,7 @@ architecture RTL of gbe_med_interface_5G is
   );
   end component;
 
-  component tsmac -- checked for ECP5-5G core
+  component tsmac_gbe -- checked for ECP5-5G core
   port(
     --------------- clock and reset port declarations ------------------
     hclk            : in  std_logic;
@@ -277,43 +277,54 @@ begin
     
       pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate
 
-      -- BUG: needs some attention!!!
-        gbe_serdes: entity work.serdes_gbe
+        gbe_serdes: entity serdes_gbe
         port map(
-          pcs_gbe_hdinp             => SD_RXD_P_IN(i),
-          pcs_gbe_hdinn             => SD_RXD_N_IN(i),
-          pcs_gbe_hdoutp            => SD_TXD_P_OUT(i),
-          pcs_gbe_hdoutn            => SD_TXD_P_OUT(i),
-          pcs_gbe_pll_refclki       => CLK_125_IN,
-          pcs_gbe_rxrefclk          => CLK_125_IN,
-          pcs_gbe_txi_clk           => CLK_125_IN, -- REALLY?
-          pcs_gbe_tx_pclk           => sd_tx_clk(i), -- TO BE IMPLEMENTED
-          pcs_gbe_rx_pclk           => sd_rx_clk(i), -- recovered RX clock
-          pcs_gbe_txdata            => sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8),
-          pcs_gbe_tx_k              => sd_tx_kcntl_q(i downto i),
-          pcs_gbe_tx_disp_correct   => sd_tx_correct_disp_q(i downto i),
-          pcs_gbe_xmit              => xmit(i downto i),
-          pcs_gbe_rxdata            => sd_rx_data( (i + 1) * 8 - 1 downto i * 8),
-          pcs_gbe_rx_k              => sd_rx_kcntl(i downto i),
-          pcs_gbe_rx_disp_err       => sd_rx_disp_error(i downto i),
-          pcs_gbe_rx_cv_err         => sd_rx_cv_error(i downto i),
-          pcs_gbe_lsm_status_s      => signal_detected(i),
-          pcs_gbe_signal_detect_c   => '1', -- enable internal LSM
-          pcs_gbe_rsl_disable       => '0', -- enable internal reset state machine
-          pcs_gbe_rsl_rst           => '0', -- should do
-          pcs_gbe_pll_lol           => open, -- BUG --out std_logic;
-          pcs_gbe_rx_cdr_lol_s      => open, -- BUG --out std_logic;
-          pcs_gbe_rst_dual_c        => '0', -- BUG --in  std_logic;
-          pcs_gbe_rx_pcs_rst_c      => '0', -- BUG --in  std_logic;
-          pcs_gbe_rx_serdes_rst_c   => '0', -- BUG --in  std_logic;
-          pcs_gbe_tx_pcs_rst_c      => '0', -- BUG --in  std_logic;
-          pcs_gbe_rx_pwrup_c        => rx_power(i),
-          pcs_gbe_tx_pwrup_c        => tx_power(i),
-          pcs_gbe_serdes_pdb        => '1', -- DUAL is powered up
-          pcs_gbe_serdes_rst_dual_c => '0',
-          pcs_gbe_tx_serdes_rst_c   => '0'
+          hdinp             => SD_RXD_P_IN(i),
+          hdinn             => SD_RXD_N_IN(i),
+          hdoutp            => SD_TXD_P_OUT(i),
+          hdoutn            => SD_TXD_N_OUT(i),
+          pll_refclki       => CLK_125_IN,
+          rxrefclk          => CLK_125_IN,
+          txi_clk           => CLK_125_IN, -- REALLY?
+          tx_pclk           => sd_tx_clk(i), -- TO BE IMPLEMENTED
+          rx_pclk           => sd_rx_clk(i), -- recovered RX clock
+          txdata            => sd_tx_data_q( (i + 1) * 8 - 1 downto i * 8),
+          tx_k              => sd_tx_kcntl_q(i downto i),
+          tx_disp_correct   => sd_tx_correct_disp_q(i downto i),
+          xmit              => xmit(i downto i),
+          rxdata            => sd_rx_data( (i + 1) * 8 - 1 downto i * 8),
+          rx_k              => sd_rx_kcntl(i downto i),
+          rx_disp_err       => sd_rx_disp_error(i downto i),
+          rx_cv_err         => sd_rx_cv_error(i downto i),
+          lsm_status_s      => signal_detected(i),
+          signal_detect_c   => '1', -- enable internal LSM
+          rsl_disable       => '0', -- enable internal reset state machine
+          rsl_rst           => '0', -- should do
+          pll_lol           => open, -- BUG --out std_logic;
+          rx_cdr_lol_s      => open, -- BUG --out std_logic;
+          rst_dual_c        => '0', -- BUG --in  std_logic;
+          rx_pcs_rst_c      => '0', -- BUG --in  std_logic;
+          rx_serdes_rst_c   => '0', -- BUG --in  std_logic;
+          tx_pcs_rst_c      => '0', -- BUG --in  std_logic;
+          rx_pwrup_c        => rx_power(i),
+          tx_pwrup_c        => tx_power(i),
+          serdes_pdb        => '1', -- DUAL is powered up
+          serdes_rst_dual_c => '0',
+          tx_serdes_rst_c   => '0',
+          sli_rst           => '0', --
+          sci_wrdata        => (others => '0'), --
+          sci_addr          => (others => '0'), --
+          sci_rddata        => open, --
+          sci_en_dual       => '0', --
+          sci_sel_dual      => '0', --
+          sci_en            => '0', --
+          sci_sel           => '0', --
+          sci_rd            => '0', --
+          sci_wrn           => '1', --
+          sci_int           => open, --
+          cyawstn           => '1' --
         );
-
+     
         -- one register between SGMII and SerDes
         SYNC_TX_PROC : process(CLK_125_IN)
         begin
@@ -336,7 +347,7 @@ begin
         end process SYNC_RX_PROC;      
         
         -- SGMII core
-        SGMII_GBE_PCS : sgmii_core
+        SGMII_GBE_PCS : sgmii_gbe_core
         port map(
           rst_n                   => synced_rst,
           signal_detect           => signal_detected(i),
@@ -424,7 +435,7 @@ begin
           mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
         );
         
-        MAC: tsmac
+        MAC: tsmac_gbe
         port map(
         ----------------- clock and reset port declarations ------------------
           hclk            => CLK_SYS_IN,

diff --git a/gbe_trb/base/gbe_wrapper_5G.vhd b/gbe_trb/base/gbe_wrapper_5G.vhd
index fc4863712b46cdbb7cd713e14f5837e0c70a0ff5..25f2f56249d7135ddf923217fff6266e45d59c5c 100644 (file)
--- a/gbe_trb/base/gbe_wrapper_5G.vhd
+++ b/gbe_trb/base/gbe_wrapper_5G.vhd
@@ -282,10 +282,10 @@ begin
       );
   end generate physical_impl_gen;
 
-  -- sfp8
+  -- 
   GEN_LINK_3 : if (LINKS_ACTIVE(3) = '1') generate
     gbe_inst3 : entity work.gbe_logic_wrapper
-      generic map(DO_SIMULATION             => DO_SIMULATION,
+      generic map(DO_SIMULATION           => DO_SIMULATION,
                 INCLUDE_DEBUG             => INCLUDE_DEBUG,
                 USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
                 RX_PATH_ENABLE            => RX_PATH_ENABLE,
@@ -433,7 +433,7 @@ begin
     mlt_cts_error_pattern(4 * 32 - 1 downto 3 * 32) <= (others => '0');
   end generate NO_LINK3_GEN;
 
-  -- sfp7
+  -- 
   GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate
     gbe_inst2 : entity work.gbe_logic_wrapper
       generic map(DO_SIMULATION             => DO_SIMULATION,
@@ -584,7 +584,7 @@ FWD_FULL_OUT => FWD_FULL_OUT(2),
     mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32) <= (others => '0');                
   end generate NO_LINK2_GEN;
 
-  -- sfp6
+  -- 
   GEN_LINK_1 : if (LINKS_ACTIVE(1) = '1') generate
     gbe_inst1 : entity work.gbe_logic_wrapper
       generic map(DO_SIMULATION             => DO_SIMULATION,
@@ -736,7 +736,7 @@ FWD_FULL_OUT => FWD_FULL_OUT(1),
     mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32) <= (others => '0');                
   end generate NO_LINK1_GEN;
 
-  -- sfp5
+  -- 
   GEN_LINK_0 : if (LINKS_ACTIVE(0) = '1') generate
     gbe_inst0 : entity work.gbe_logic_wrapper
       generic map(DO_SIMULATION             => DO_SIMULATION,