IPU_HDR_DATA_READ_IN : in std_logic;
IPU_HDR_DATA_EMPTY_OUT : out std_logic;
+ TMG_TRG_ERROR_IN : in std_logic;
--Status
STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);
end generate;
- header_buffer_data_in <= "0000000" & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN;
+ header_buffer_data_in <= "000000" & TMG_TRG_ERROR_IN & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN;
---------------------------------------------------------------------------
signal state_bits : std_logic_vector(3 downto 0);
signal error_not_found, next_error_not_found : std_logic;
+ signal error_lvl1, next_error_lvl1 : std_logic;
signal error_sync : std_logic;
signal error_missing, next_error_missing : std_logic;
signal error_not_configured : std_logic;
THE_FSM : process(current_state, error_not_found, IPU_START_READOUT_IN, DAT_HDR_DATA_EMPTY_IN,
DAT_HDR_DATA_IN, last_hdr_fifo_valid_read, ipu_dataready_i, IPU_READ_IN,
- error_missing, dat_fifo_valid_read, next_dat_fifo_number,
+ error_missing, dat_fifo_valid_read, next_dat_fifo_number, error_lvl1,
dat_fifo_finished, dat_fifo_number, DAT_DATA_IN, suppress_output)
begin
next_state <= current_state;
next_error_not_found <= error_not_found;
next_error_missing <= error_missing;
+ next_error_lvl1 <= error_lvl1;
next_hdr_fifo_read <= '0';
next_lvl1_fifo_read <= '0';
next_ipu_data_i <= (others => '0');
end if;
next_error_not_found <= '0';
next_error_missing <= '0';
+ next_error_lvl1 <= '0';
next_dat_fifo_number <= 0;
end if;
if last_hdr_fifo_valid_read = '1' then
next_state <= SEND_DHDR;
next_suppress_output <= DAT_HDR_DATA_IN(28);
+ next_error_lvl1 <= DAT_HDR_DATA_IN(29);
end if;
-- when GOT_LENGTH =>
next_ipu_dataready_i <= (dat_fifo_valid_read or (ipu_dataready_i and not IPU_READ_IN));
next_ipu_data_i <= DAT_DATA_IN(dat_fifo_number*32+31 downto dat_fifo_number*32);
+
when END_READOUT =>
next_ipu_finished_i <= '1';
if IPU_START_READOUT_IN = '0' then
ipu_error_pattern_i(21) <= error_missing; --part of data missing
ipu_error_pattern_i(22) <= error_sync; --severe sync problem
ipu_error_pattern_i(23) <= error_not_configured; --FEE not configured
- ipu_error_pattern_i(31 downto 24) <= (others => '0');
+ ipu_error_pattern_i(26 downto 24) <= (others => '0');
+ ipu_error_pattern_i(27) <= error_lvl1;
+ ipu_error_pattern_i(31 downto 28) <= (others => '0');
+
error_not_configured <= '0';
FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ TMG_TRG_ERROR_IN : in std_logic;
+
--Status Registers
STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);
IPU_HDR_DATA_OUT => ipu_header,
IPU_HDR_DATA_READ_IN => ipu_header_read,
IPU_HDR_DATA_EMPTY_OUT => ipu_header_empty,
+ TMG_TRG_ERROR_IN => TMG_TRG_ERROR_IN,
--Status
STAT_DATA_BUFFER_LEVEL => STAT_DATA_BUFFER_LEVEL,
STAT_HEADER_BUFFER_LEVEL => STAT_HEADER_BUFFER_LEVEL,
LVL1_TRG_RELEASE_IN : in std_logic := '0';
LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
--Data Port
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
signal buf_LVL1_TRG_DATA_VALID_OUT : std_logic;
signal int_lvl1_delay : std_logic_vector(15 downto 0);
- signal int_multiple_trg : std_logic;
signal int_trg_reset : std_logic;
signal reset_trg_logic : std_logic;
signal stat_lvl1_handler : std_logic_vector(63 downto 0);
signal stat_counters_lvl1_handler: std_logic_vector(63 downto 0);
signal trg_invert_i : std_logic;
+ signal int_multiple_trg : std_logic;
signal int_lvl1_timeout_detected : std_logic;
signal int_lvl1_spurious_trg : std_logic;
signal int_lvl1_missing_tmg_trg : std_logic;
DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT
);
-
+ TRG_SPIKE_DETECTED_OUT <= int_spike_detected;
+ TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;
+ TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
+ TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;
+ TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;
-- THE_TRG_SYNC : signal_sync
-- generic map(
LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
+
--Response from FEE
FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
signal debug_data_handler_i : std_logic_vector(31 downto 0);
signal debug_ipu_handler_i : std_logic_vector(31 downto 0);
+ signal int_multiple_trg : std_logic;
+ signal int_lvl1_timeout_detected : std_logic;
+ signal int_lvl1_spurious_trg : std_logic;
+ signal int_lvl1_missing_tmg_trg : std_logic;
+ signal int_spike_detected : std_logic;
+ signal tmg_trg_error_i : std_logic;
+
+
begin
---------------------------------------------------------------------------
-- TrbNet Endpoint
LVL1_TRG_RELEASE_IN => lvl1_release_i,
LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number_i,
+ --Information about trigger handler errors
+ TRG_SPIKE_DETECTED_OUT => int_spike_detected,
+ TRG_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg,
+ TRG_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected,
+ TRG_MULTIPLE_TRG_OUT => int_multiple_trg,
+ TRG_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg,
--Data Port
IPU_NUMBER_OUT => ipu_number_i,
IPU_READOUT_TYPE_OUT => ipu_readout_type_i,
FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN,
FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT,
+ TMG_TRG_ERROR_IN => tmg_trg_error_i,
--Status Registers
STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level,
STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level,
lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i;
STAT_DEBUG_IPU_HANDLER_OUT <= debug_ipu_handler_i;
STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i;
+ tmg_trg_error_i <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg
+ or int_spike_detected;
---------------------------------------------------------------------------
-- Connect Status Registers
-- Connect I/O Ports
---------------------------------------------------------------------------
+ TRG_SPIKE_DETECTED_OUT <= int_spike_detected;
+ TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;
+ TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
+ TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;
+ TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;
+
LVL1_TRG_DATA_VALID_OUT <= lvl1_data_valid_i;
LVL1_VALID_TIMING_TRG_OUT <= lvl1_valid_timing_i;
LVL1_VALID_NOTIMING_TRG_OUT <= lvl1_valid_notiming_i;
end case;
when c_F3 =>
- next_API_DATA_OUT <= (others => '0');
+ next_API_DATA_OUT <= global_time_i(19 downto 4);
if API_READ_IN = '1' then
next_state <= SEND_REPLY_DATA_finish;
end if;
next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
next_API_DATAREADY_OUT <= '1';
when c_F3 =>
- next_API_DATA_OUT <= (others => '0');
+ next_API_DATA_OUT <= global_time_i(19 downto 4);--(others => '0');
next_API_DATAREADY_OUT <= '1';
if API_READ_IN = '1' then
next_length <= length-1;
when c_F0 => next_API_DATA_OUT <= address;
when c_F1 => next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
when c_F2 => next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
- when c_F3 => next_API_DATA_OUT <= (others => '0');
+ when c_F3 => next_API_DATA_OUT <= global_time_i(19 downto 4);--(others => '0');
if API_READ_IN = '1' then
next_state <= SEND_REPLY_DATA_finish;
end if;
when c_F0 => next_API_DATA_OUT <= address;
when c_F1 => next_API_DATA_OUT <= dat_data_counter;
when c_F2 => next_API_DATA_OUT <= (others => '0');
- when c_F3 => next_API_DATA_OUT <= (others => '0');
+ when c_F3 => next_API_DATA_OUT <= global_time_i(19 downto 4);--(others => '0');
if API_READ_IN = '1' then
next_state <= SEND_REPLY_DATA_finish;
end if;
LVL1_TRG_RELEASE_IN : in std_logic := '0';
LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
-
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
--Data Port
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
+
--Slow Control Port
--common registers
REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
IPU_HDR_DATA_READ_IN : in std_logic;
IPU_HDR_DATA_EMPTY_OUT : out std_logic;
+ TMG_TRG_ERROR_IN : in std_logic;
--Status
STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);
FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ TMG_TRG_ERROR_IN : in std_logic;
--Status Registers
STATUS_OUT : out std_logic_vector(127 downto 0);
STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
jspc29 / trbnet.git / commitdiff