+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-use work.trb_net_std.all;
-
-
-entity trb_net16_hub_control is
- generic (
- MY_ADDRESS : std_logic_vector(15 downto 0)
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- APL Transmitter port
- APL_DATA_OUT: out std_logic_vector (15 downto 0);
- APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- APL_WRITE_OUT: out std_logic;
- APL_FIFO_FULL_IN: in std_logic;
- APL_SHORT_TRANSFER_OUT: out std_logic;
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0);
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
- APL_SEND_OUT: out std_logic;
- APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0);
- -- Receiver port
- APL_DATA_IN: in std_logic_vector (15 downto 0);
- APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0);
- APL_TYP_IN: in std_logic_vector (2 downto 0);
- APL_DATAREADY_IN: in std_logic;
- APL_READ_OUT: out std_logic;
- -- APL Control port
- APL_RUN_IN: in std_logic;
- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0);
- APL_SEQNR_IN: in std_logic_vector (7 downto 0)
- );
-end entity;
-
-architecture trb_net16_hub_control_arch of trb_net16_hub_control is
-
-
-
-begin
-
- hub_control : trb_net16_regIO
- generic map(
- MY_ADDRESS => x"F001",
- REGISTER_WIDTH => 32,
- ADDRESS_WIDTH => 16,
- ADDRESS_USED_WIDTH => 4,
- NO_DAT_PORT => '1'
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Port to API
- API_DATA_OUT => HC_DATA_IN,
- API_PACKET_NUM_OUT => HC_PACKET_NUM_IN,
- API_WRITE_OUT => HC_WRITE_IN,
- API_FIFO_FULL_IN => HC_FIFO_FULL_OUT,
- API_SHORT_TRANSFER_OUT => HC_SHORT_TRANSFER_IN,
- API_DTYPE_OUT => HC_DTYPE_IN,
- API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN,
- API_SEND_OUT => HC_SEND_IN,
- API_TARGET_ADDRESS_OUT => (others => '0'),
- -- Receiver port
- API_DATA_IN => HC_DATA_OUT,
- API_PACKET_NUM_IN => HC_PACKET_NUM_OUT,
- API_TYP_IN => HC_TYP_OUT,
- API_DATAREADY_IN => HC_DATAREADY_OUT,
- API_READ_OUT => HC_READ_IN,
- -- HC Control port
- API_RUN_IN => HC_RUN_OUT,
- API_MY_ADDRESS_OUT => HC_MY_ADDRESS_IN,
- API_SEQNR_IN => HC_SEQNR_OUT,
- REGISTERS_IN => HC_STAT_REGS,
- REGISTERS_OUT => HC_CTRL_REGS,
- DAT_ADDR_OUT => open,
- DAT_READ_ENABLE_OUT => open,
- DAT_WRITE_ENABLE_OUT=> open,
- DAT_DATA_OUT => open,
- DAT_DATA_IN => (others => '0'),
- DAT_DATAREADY_IN => '0'
- );
-
-
-
-end architecture;
\ No newline at end of file
--full buffers (despite the sbuf) can only occur on the last packet.
COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word,
CURRENT_DATA_COUNT, reg_SEND_ACK_IN, INT_DATAREADY_IN, INT_DATA_IN,
- reg_INT_READ_OUT, reg_SEND_ACK_IN, saved_packet_type,
+ reg_INT_READ_OUT, saved_packet_type,
current_DATA_word, send_ACK, send_EOB, sbuf_free,
current_ACK_word, current_EOB_word,
next_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS, send_DATA)