\title{A novel approach for pulse width measurements with a high resolution
-($8.7~ps$) TDC in an FPGA}
+(8.7~ps) TDC in an FPGA}
\author{C. Ugur$^a$\thanks{Corresponding author.}~,
S. Linev$^b$,
of the TDC channels for leading and trailing edge time measurements
individually. This method however, requires double the number of resources and
therefore this paper presents a novel way of measuring pulse width using a
-single TDC channel, while still achieving high precision (as low as $12ps
-RMS$).}
+single TDC channel, while still achieving high precision (as low as 12~ps RMS).}
\keywords{Front-end electronics for detector readout; Digital electronic
circuits}
Custom data acquisition (DAQ) needs and short implementation time make the FPGA
based TDCs more desirable in some applications. There are many different TDC
-architectures implemented in FPGAs from below $10~ps$ up to $ns$ levels in
+architectures implemented in FPGAs from below 10~ps up to nanosecond levels in
precision depending on the measurement methods \cite{WUL}\cite{tdc_counter}.
These methods apply approaches such as simple counters with high frequency
clocks (or phase shifted clocks), two oscillators with slightly different
This study is based on the previous TDC design \cite{tdc_ieee} for single edge
measurements applying tapped delay line method, as its superiority in range,
-dead time and especially in precision. The work is further developed to react to
-both edges of a signal for a ToT measurement with a novel approach.
+dead time and especially in precision. The work is further developed to react
+to both edges of a signal for a ToT measurement with a novel approach.
\section{Architecture}
As explained in our previous paper the architecture of the TDC is based on the
interpolation method \cite{kalisz}, where the interpolator is built as a tapped
-delay line with the wave union launcher \cite{WUL} for the precision
-enhancement.
-The full architecture of the TDC and a diagram of the tapped delay line method
-can be seen in figure~\ref{fig:tdcArch}. The start signal for the delay line is
-the digital output signal from the front-end electronics (FEE), where as the
-propagation of the signal is stopped with the next rising edge of the $200~MHz$
-clock signal. The output of the delay line, as thermometer code, is then sent to
-the decoder for the conversion to the binary code. This data, as well as the
-time stamp from the epoch and coarse counters with $5~ns$ granularity, are
-saved in ring-buffer. The readout and slow control of the TDC is based on the
+delay line combined with a wave union launcher \cite{WUL} for the precision
+enhancement. The full architecture of the TDC and a diagram of the tapped delay
+line method can be seen in figure~\ref{fig:tdcArch}. The start signal for the
+delay line is the digital output signal from the front-end electronics (FEE),
+whereas the propagation of the signal is stopped with the next rising edge of
+the 200~MHz clock signal. The output of the delay line, as thermometer code, is
+then sent to the decoder for the conversion to binary code. This data, as well
+as the time stamp from the epoch and coarse counters with 5~ns granularity, are
+saved in a ring-buffer. The readout and slow control of the TDC is based on the
TRBNet protocol \cite{trbnet}.
\begin{figure}[tbp]
before the delay line. The goal of this semi-asynchronous stretcher is to keep
the asynchronous timing of the leading edge and stretch the signal until the
second rising edge of the clock signal [figure~\ref{fig:stretcherSemiAsync}].
-With this stretcher method pulses with width of $500~ps$ were measured
-successfully \cite{tdc_ieee}.
+With this stretcher method 500~ps wide pulses were measured successfully
+\cite{tdc_ieee}.
\begin{figure}[tbp]
\centering
\includegraphics[width=.5\textwidth]
{../figures/tdc/stretcher_semiAsync.eps}
\caption{Semi-asynchronous stretcher logic is implemented before the delay
-line in order to keep the timing of the leading edge of the input signal
-($hit$) and stretch the trailing edge beyond the clock period. The $hit_{in}$
-signal to forwarded to the delay line.}
+line in order to keep the timing of the leading edge of the input signal ($hit$)
+and stretch the trailing edge beyond the clock period. The $hit_{in}$ signal to
+forwarded to the delay line.}
\label{fig:stretcherSemiAsync}
\end{figure}
\section{Time over threshold measurement}
-As stated above ToT measurements have certain advantages over the amplitude and
+As stated above, ToT measurements have certain advantages over amplitude and
charge measurements and with the development in high precision TDCs ToT method
became more desired in some applications. In the FEE part the analogue signal is
discriminated with a certain threshold and a digital pulse is generated, where
In conventional TDCs the input pulse is internally split and the leading and
trailing edges are measured in two separate TDC channels. Although this method
-is straightforward and easy to implement, it is not resource efficient. For
-both edges double the amount of resources in the FPGA must be used.
+is straightforward and easy to implement, it is not resource efficient. For both
+edges double the amount of resources in the FPGA must be used.
\subsection{Semi-asynchronous stretcher for ToT measurements}
As the TDC channels are once again active as soon as the dead time after a
-successful measurement is over (in our case this value is $20~ns$), for pulses
-longer than this dead time the channel resources could be reused. With this way,
-a channel first measures the leading edge of the input pulse and then, when the
-channel is active again, it measures the trailing edge.
+successful measurement is over (in our case this value is 20~ns), for pulses
+longer than this dead time the channel resources are active again. With this
+way, a channel first measures the leading edge of the input pulse and then, when
+the channel is active again, it measures the trailing edge.
As our TDC architecture is sensitive to the rising edges of positive input
pulses, we generate two short positive pulses (still longer than a clock period)
original input pulse. This is done by using two semi-asynchronous stretchers,
one sensitive to the rising and the other sensitive to the falling edge of the
input pulse. The timing diagram for this method is shown in
-figure~\ref{fig:stretcherTimingSemi}. The rising edges of the pulses $hit_l$
-and $hit_t$ are correlated with the leading and trailing edges of the input
-signal respectively. First the pulse $hit_l$ and then the second pulse $hit_t$
-are measured in the same channel without any problem, as the time gap between
-them is larger then the dead time. In this way, the channel functions as always
-without any alteration. At the end, the data are written in the ring-buffer
-with one extra bit as an edge type marker.
+figure~\ref{fig:stretcherTimingSemi}. The rising edges of the pulses $hit_l$ and
+$hit_t$ are correlated with the leading and trailing edges of the input signal
+respectively. First the pulse $hit_l$ and then the second pulse $hit_t$ are
+measured in the same channel, as long as the time gap between them is larger
+then the dead time. At the end, the data are written in the ring-buffer with one
+extra bit as an edge type marker.
Reusing the resources in this manner enables a compacter design with double the
number of channels in an FPGA. However, this is only possible, if the width of
\label{fig:stretcherTimingFull}
\end{subfigure}%
-\caption{The asynchronous stretchers placed at the input are sensitive to
-rising and falling edges. The small pulses are measured as usual in a TDC
-channel. The delay circuit guarantees that even short pulses can be measured
-without any problem.}
+\caption{The asynchronous stretchers placed at the input are sensitive to rising
+and falling edges. The small pulses are measured as usual in a TDC channel. The
+delay circuit guarantees that even short pulses can be measured.}
\label{fig:stretcherTiming}
\end{figure}
The full-asynchronous stretcher consists of two semi-asynchronous stretchers
(sensitive to two different edges as explained above) and a delay circuit for
the trailing edge. The timing diagram for this method is shown in
-figure~\ref{fig:stretcherTimingFull}. The pulse $hit_l$ is measured as
-normal in the TDC channel, while the $hit_t$ pulse is delayed in the FPGA
-($hit_d$) and injected back in to the channel. The delay circuit is a chain of
-several inverters connected one after another. The inverters are placed far away
-from each other in the FPGA in order to take advantage of the long propagation
-time of the normal routing through the switching circuitry, buffers and metal
-interconnects. In the FPGA that we use - Lattice ECP3 FPGA with $150K$ logic
+figure~\ref{fig:stretcherTimingFull}. The pulse $hit_l$ is measured as normal in
+the TDC channel, while the $hit_t$ pulse is delayed in the FPGA ($hit_d$) and
+injected back in to the channel. The delay circuit is a chain of several
+inverters connected one after another. The inverters are placed far away from
+each other in the FPGA in order to take advantage of the long propagation time
+of the normal routing through the switching circuitry, buffers and metal
+interconnects. In the FPGA that we use - Lattice ECP3 FPGA with 150K logic
elements - the routing from one corner to the diagonally opposite corner takes
-approximately $10~ns$. By increasing the number of laps between the corners
-delays longer than the dead time are easily achievable.
+approximately 10~ns. By increasing the number of laps between the corners delays
+longer than the intrinsic TDC dead time are achievable.
-Using this delay circuitry allows us to measure both edges of pulses shorter
-than the dead time of the TDC on a single channel. The disadvantage of this
-method is the extra dead time after the measurement of the trailing edge, which
-limits the measurement of double pulse with offsets less than the dead time.
-Also the non-deterministic stretching time between the channels and the
-design compilations has to be tackled to get the real time information.
+Using this circuitry allows us to measure both edges of pulses shorter than the
+dead time of the TDC on a single channel. The disadvantage of this method is the
+extra dead time after the measurement of the trailing edge, which limits the
+measurement of double pulse with offsets less than the total dead time (pulse
+length + stretcher delay + conversion dead time). Also, the non-deterministic
+stretching time between the channels and the design compilations has to be
+tackled to get the real time information.
% \subsection{Stretcher offset calculation and calibration}
% With the method mentioned above the time measured is the sum of the pulse width
%
% We overcome this problem by generating a fix width pulse in the FPGA and
% injecting it to each channel before the stretcher circuitry. The fix width pulse
-% ($30~ns$) is generated by an on-chip PLL and sent to the input multiplexers
+% (30~ns) is generated by an on-chip PLL and sent to the input multiplexers
% of the channels. The multiplexers are controlled by the trigger type sent by
% the central trigger system of the setup.
The test setup consists of two FPGA boards; one as the pulse generator and the
other as the TDC board (TRB3 \cite{trb3}). The pulse generator board uses an
ecp2m-100 FPGA, where as the TDC is implemented in an ecp3-150 FPGA both from
-Lattice. The pulse generator design generates groups of $4$ bit data with
-$150~MHz$ and this data is serialised with a DDR2 module from the FPGA vendor
-at $600~MHz$ clock frequency. This way pulses or patterns with
-$1.67~ns$ resolution are possible to generate. These pulses/patterns
-are sent to the TDC for leading edge and ToT measurements. The output of the
-pulser is split at fanout chips to fire every channel of the TDC. For
-calibration of the channels we use bin-by-bin calibration \cite{calibration} and
-automatically update the calibration table after every $200~000$ events. In the
-measurement time distributions we do not apply any cuts or curve fittings.
+Lattice. The pulse generator design generates groups of 4 bit data with 150~MHz
+and this data is serialised with a DDR2 module from the FPGA vendor at 600~MHz
+clock frequency. This way, pulses or patterns with 1.67~ns resolution are
+possible to be generated. These pulses/patterns are sent to the TDC for leading
+edge and ToT measurements. The output of the pulser is split in fanout chips to
+fire every channel of the TDC. For calibration of the channels we use bin-by-bin
+calibration \cite{calibration} and automatically update the calibration table
+after every 200~000 events. In the measurement time distributions we do not
+apply any cuts or curve fittings.
\begin{figure}[tbp]
\centering
\centering
\includegraphics[width=.8\linewidth]
{../figures/tdc/t_diff_tot_alternating.eps}
- \caption{ToT measurement with conventional method.}
+ \caption{Conventional method.}
\label{fig:precisionToTalt}
\end{subfigure}%
\begin{subfigure}{.5\textwidth}
\centering
\includegraphics[width=.8\linewidth]
{../figures/tdc/t_diff_tot_stretcher_high_precision.eps}
- \caption{ToT measurement with novel method.}
+ \caption{Novel method.}
\label{fig:precisionToTstretch}
\end{subfigure}%
-\caption{The architecture of the TDC and the tapped delay line method.}
+\caption{The width of a pulse is measured both with the conventional and novel
+methods. A negligible change in the precision is inspected between the two
+methods.}
\label{fig:precisionToT}
\end{figure}
First, the precision of the leading edge measurements between the channels are
-tested by selecting one of the $64$ channels as the reference channel and
+tested by selecting one of the 64 channels as the reference channel and
calculating the time difference between each channel and the reference channel.
-The precision of the measurement is calculated as the RMS of the time
-distribution of the measurement and among the $64$ measurements precision
-values fluctuate between $8.7~ps$ and $10.9~ps$. In
-figure~\ref{fig:precisionLeading} the precision of an example measurement with
-$8.7~ps$ is shown. This value yields a $6.15~ps$ precision on a single channel.
+The precision is calculated as the RMS of the time distribution of the
+measurement and among 64 channels precision values fluctuate between 8.7~ps and
+10.9~ps. In figure~\ref{fig:precisionLeading} an exemplary measurement shows a
+precision of 8.7~ps. As this value combines the precision of two channels, the
+single channel precision can be determined as 6.15~ps.
The same test is applied for the ToT measurement by generating a short pulse
-($1.67~ns$) at the pulse generator and splitting to each channel.
-First the conventional method - two channels for the measurement - is used and
-the best precision is calculated as $12.2~ps$
-(figure~\ref{fig:precisionToTalt}). The same test is done the with the novel
-method for comparison and the best precision is calculated as $12.1~ps$
-(figure~\ref{fig:precisionToTstretch}). The precision among the channels varied
-between $12.1~ps$ and $17.9~ps$.
+(1.67~ns) at the pulse generator and splitting to each channel. First the
+conventional method - two channels for the measurement - is used and the best
+precision is calculated as 12.2~ps (figure~\ref{fig:precisionToTalt}). The same
+test is done the with the novel method for comparison and the best precision is
+calculated as 12.1~ps (figure~\ref{fig:precisionToTstretch}). The precision
+among the channels varied between 12.1~ps and 17.9~ps.
The mean values of the histograms with the conventional and novel method do not
-match with the measured pulse width - ($1.67~ns$) - because of the
-offset between the channels and the offset induced by the stretcher
-respectively. In order to test the pulse width measurement we applied a pulse
-width sweep and measured the shift in the mean value with both an oscilloscope
-and the TDC (figure~\ref{fig:totSweep}). The maximum deviation in the measured
-mean value relative to the oscilloscope results was observed as $38~ps$.
+match with the measured pulse width - (1.67~ns) - because of the offset between
+the channels and the offset induced by the stretcher respectively, which have
+not yet been accounted for. In order to test the pulse width measurement we
+applied a pulse width sweep and measured the shift in the mean value with both
+an oscilloscope and the TDC (figure~\ref{fig:totSweep}). The maximum deviation
+in the measured mean value relative to the oscilloscope results was observed as
+38~ps.
\begin{figure}[tbp]
\centering
\includegraphics[width=.6\textwidth]{../figures/tdc/tot_sweep.pdf}
- \caption{ToT sweep with $1.6~ns$ granularity.}
+ \caption{ToT sweep with 1.6~ns granularity.}
\label{fig:totSweep}
\end{figure}
We also tested the quality of the long time interval measurements as this is
both important for the long time of flight (ToF) and ToT measurements. The test
setup consists of the FPGA-TDC and a pulse generator (Tektronix AWG7000) with
-two outputs controlled over a general purpose interface bus (GPIB). The
-two outputs of the pulser are sent to two different channels of the TDC, where
-the time interval is measured. Starting with $0~s$ time interval one output is
-shifted with $1~ns$ after each successful measurement until a time interval of
-$1~us$ is reached. The precision is recorded for each measurement. The
+two outputs controlled over a general purpose interface bus (GPIB). The two
+outputs of the pulser are sent to two different channels of the TDC, where the
+time interval between the outputs is measured. Starting with 0~s time interval
+one output is shifted with 1~ns after each successful measurement until a time
+interval of 1~us is reached. The precision is recorded for each measurement. The
calibration of the channels is done only once at the beginning of the test.
In figure~\ref{fig:rmsWITHdcdc} the precision of a channel as a function of the
measured interval is shown. It was observed that over a microsecond time
-interval the precision value oscillates with an amplitude of $48~ps$ and this
-effect was thought to be from the DC-DC converters. Next, the board was
-stripped down of the converters and the FPGA was powered with a linear power
-supply (HMP4040). The test was repeated to be noted that the oscillation
-amplitude is improved by a factor of $\sim12$. The exposed secondary oscillation
-has an amplitude of $\sim3~ps$ and a frequency of $25~MHz$
-(figure~\ref{fig:rmsNOdcdc}). This trivial oscillation is not further
-investigated as the amplitude is negligible.
+interval the precision value oscillates with an amplitude of 48~ps and this
+effect was thought to be from the DC-DC converters. Next, the board was stripped
+down of the converters and the FPGA was powered with a linear power supply
+(HMP4040). The test was repeated to be noted that the oscillation amplitude is
+improved by a factor of $\sim$12. The exposed secondary oscillation has an
+amplitude of $\sim$3~ps and a frequency of 25~MHz (figure~\ref{fig:rmsNOdcdc}).
+This additional oscillation is not further investigated as the amplitude is
+negligible.
\begin{figure}[tbp]
\begin{subfigure}{.5\textwidth}
\centering
\includegraphics[width=.8\linewidth]
{../figures/tdc/rms_trb3_with_dcdc.eps}
- \caption{With DC-DC converters to power the FPGA.}
+ \caption{With DC-DC converters.}
\label{fig:rmsWITHdcdc}
\end{subfigure}%
\begin{subfigure}{.5\textwidth}
\centering
\includegraphics[width=.8\linewidth]
{../figures/tdc/rms_trb3_without_dcdc.eps}
- \caption{Linear power supply to power the FPGA.}
+ \caption{With a linear power supply.}
\label{fig:rmsNOdcdc}
\end{subfigure}%
-\caption{Time interval sweep is done with and without DC-DC converters.}
+\caption{The precision of the measurements is recorded over a microsecond time
+interval between two outputs of a pulse generator. The oscillation amplitude is
+reduced to 3~ps by powering the FPGA with a linear power supply instead of DC-DC
+converters.}
\label{fig:rmsVSdcdc}
\end{figure}
\subsection{Effect of temperature over ToT}
-The effect of the temperature on the the ToT measurements are observed by
-building a setup consisting of a ventilator and a TRB3 board. The temperature of
-the FPGA is varied by adjusting the ventilator speed. The temperature of the
-FPGA is measured by the temperature sensor on the board close to the FPGA. $14$
-different measurements are done in the temperature range of $36.8^{\circ}C$ and
-$42.8^{\circ}C$. The mean of the ToT measurements are plotted as a function of
+The effect of the temperature on the ToT measurements are observed by building a
+setup consisting of a ventilator and a TRB3 board. The temperature of the FPGA
+is varied by adjusting the ventilator speed. The temperature of the FPGA is
+measured by a temperature sensor on the board close to the FPGA. 14 different
+measurements are done in the temperature range of 36.8$^{\circ}$C and
+42.8$^{\circ}$C. The mean of the ToT measurements are plotted as a function of
temperature (figure~\ref{fig:totVStemp}). In order to see the change the ToT
values at the initial temperature are subtracted from the measured values.
-From the plot it can be seen that there are two different disturbances to
-be corrected. One is the change in the ToT on a single channel with the changing
+From the plot it can be seen that there are two different disturbances to be
+corrected. One is the change in the ToT on a single channel with the changing
temperature. The other is the secondary effect of the temperature change on
different ToT offsets, as the effect of temperature is higher on the longer
-stretcher offsets due to larger intrinsic delays of the electronic components on
-the delay lines.
+stretcher offsets due to larger intrinsic delays of the electronic components
+on the delay lines.
-The temperature correction is done by fitting a linear line at the temperature
+The temperature correction is done by fitting a linear line to the temperature
curve of a channel (e.g. channel 12) - which lies in the middle of the spread -
and using the slope for correction. By selecting a channel in the middle the
absolute deviations of the ToT of the channels from the initial values are
in the temperature and the initial ToT value, independent of the channel.
Applying only the temperature correction of the above equation, the maximum ToT
-shift can be corrected by a factor of $\sim4$
+shift can be corrected by a factor of $\sim$4
(figure~\ref{fig:totVStemp_tempCorr}). This correction factor increases to
-$\sim10$ limiting the ToT shift with $\sim50~ps$ over $6^{\circ}C$ temperature
+$\sim$10 limiting the ToT shift with $\sim$50~ps over 6$^{\circ}$C temperature
change, when both - temperature and offset - corrections are applied.
\begin{figure}[tbp]
\centering
\includegraphics[width=1\linewidth]
{../figures/tdc/temp_TOToffset_vs_TOTshift_@43C.pdf}
- \caption{ToT shift $@42.8^{\circ}C$ as a function of stretcher offset.}
+ \caption{ToT shift @42.8$^{\circ}$C as a function of stretcher offset.}
\label{fig:totVSoffset}
\end{subfigure}%
\caption{The effect of temperature is seen more drastically on channels with
\caption{Correction with temperature \& offset coefficients.}
\label{fig:totVStempCorrected2}
\end{subfigure}%
-\caption{The shift of ToT is corrected by a factor of $\sim10$ over $6^{\circ}C$
+\caption{The shift of ToT is corrected by a factor of $\sim$10 over 6$^{\circ}$C
temperature change.}
\label{fig:temp2}
\end{figure}
\section{Conclusion}
-In this paper we presented our novel way of measuring ToT on an FPGA TDC using
-a single channel. Based on the conducted tests precision of the leading edge
-measurement is recorded as low as $8.7~ps$, suggesting $6.15~ps$ error on a
-single channel. The precisions for ToT measurements with the conventional and
-novel methods are recorded as $12.2~ps$ and $12.1~ps$ respectively. The novel
-method is investigated further to find out, that the ToT value differs maximum
-$38~ps$ from the oscilloscope measurements once the stretcher offset is
-eliminated. It is also discovered that the deterioration in the long time
-interval measurement precision can be limited to $3~ps$, if the FPGA is powered
-with a linear power supply. The effect of the temperature change on the ToT
-measurement is also assessed and the degeneration is improved by a factor of
-$\sim10$ and limited to $\sim50ps$ with a correction model.
+In this paper we presented our novel way of measuring ToT on an FPGA TDC using a
+single channel. Based on the conducted tests precision of the leading edge
+measurement is recorded as low as 8.7~ps, suggesting 6.15~ps error on a single
+channel. The precisions for ToT measurements with the conventional and novel
+methods are recorded as 12.2~ps and 12.1~ps respectively. The novel method is
+investigated further to find out, that the ToT value differs maximum 38~ps from
+the oscilloscope measurements once the stretcher offset is eliminated. It is
+also discovered that the deterioration in the long time interval measurement
+precision can be limited to 3~ps, if the FPGA is powered with a linear power
+supply. The effect of the temperature change on the ToT measurement is also
+assessed and the degeneration is improved by a factor of $\sim$10 and limited to
+$\sim$50~ps with a correction model.
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