end process;
+process begin
+ wait until rising_edge(CLK_TDC);
+ if RESET_IN = '1' then
+ count_edges1 <= (others => '0');
+ elsif hit_buffer_write = '1' then
+ count_edges1 <= count_edges1 + 1;
+ end if;
+end process;
+
process begin
wait until rising_edge(CLK_TDC);
if RESET_IN = '1' then
hit_buffer_read <= '0';
hit_buffer_reset <= '0';
DATA_EMPTY <= '0';
-
--- if hit_buffer_read = '1' then
--- count_edges1 <= count_edges1 + 1;
--- end if;
case buffer_state is
when EMPTY =>
if RESET_IN = '1' then
buffer_state <= EMPTY;
hit_buffer_reset <= '1';
--- count_edges1 <= (others => '0');
end if;
end process;
BUS_TX.data <= status_rdo_handler(31 downto 0);
elsif BUS_RX.addr = x"0011" then
BUS_TX.data <= status_rdo_handler(63 downto 32);
+ elsif BUS_RX.addr = x"0020" then
+ BUS_TX.data <= x"00" & x"01" & x"0a" & std_logic_vector(to_unsigned(NUM_CHANNELS,8)); --1e:hit buffer size 32, 01: data format leading/trailing
elsif BUS_RX.addr(15 downto 5) = x"01" & "000" then
BUS_TX.data <= hitbuffer_status(addr)(31 downto 0);
elsif BUS_RX.addr(15 downto 5) = x"01" & "001" then