32bit flash read and endian option, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index da219b8fbda69e4605f562f65d942cee44391110..f59260f9ca24dfac5dfa961305fa975ab3716651 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -16,8 +16,9 @@
 --  0x5C : control register\r
 --         Bit 0 : Enable cfg flash\r
 --         Bit 1 : Master start (starts unpacking = booting)\r
---  0x5D : Flash memory return buswidth:\r
+--  0x5D : Bits 0/1: Flash memory read buswidth:\r
 --         00 : 8 Bit, 01 : 16 Bit, 11 : 32 Bit (if available)\r
+--         Bit 8: 0: Little Endian; 1: Big Endian\r
 --  0x5E-5F : Debug registers\r
 \r
 \r
@@ -251,16 +252,24 @@ PROC_SELECTOR : process begin
     else --continue\r
       reg_SPI_READY_OUT <= '0';\r
       if (memreg(1) = '1') then\r
-        -- at least 32 bit burst\r
+        -- at least 24 bit burst\r
         spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); --prepare nibble3\r
       end if;\r
-      reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1\r
+      if (memreg(8) = '1') then\r
+        reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) <= ram_data_o;\r
+      else\r
+        reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1\r
+      end if;\r
       out_delay <= "011";\r
     end if;\r
   elsif (out_delay = "011") then\r
     reg_LOC_READ_OUT  <= '0';\r
-    reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);\r
+    if (memreg(8) = '1') then\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) & ram_data_o;\r
+    else\r
+      reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);\r
     -- write nibble2\r
+    end if;\r
     if (memreg(1) = '0' or DATA_BUS_WIDTH < 32) then\r
       out_delay <= "000";\r
       reg_SPI_READY_OUT <= '1';\r
@@ -273,12 +282,21 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "100" and DATA_BUS_WIDTH > 16) then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '0';\r
-    reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);\r
+    if (memreg(8) = '1') then\r
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-24) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) & ram_data_o;\r
+    else\r
+      reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);\r
+    end if;\r
     out_delay <= "101";\r
   elsif (out_delay = "101" and DATA_BUS_WIDTH > 24) then\r
     reg_LOC_READ_OUT  <= '0';\r
     reg_SPI_READY_OUT <= '1';\r
-    reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);\r
+    if (memreg(8) = '1') then\r
+      reg_SPI_DATA_OUT(31 downto 0) <= reg_SPI_DATA_OUT(31 downto 8) & ram_data_o;\r
+    else\r
+      reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);\r
+    end if;\r
+    out_delay <= "000";\r
   else\r
     out_delay <= "000";\r
   end if;\r